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Commit 29d789db authored by Andrey Filippov's avatar Andrey Filippov
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Added compact input primitives logging and FPGA-based profiling of the host/device communication

parent 260e7464
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.project
View file @ 29d789db
...@@ -52,87 +52,87 @@ ...@@ -52,87 +52,87 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160307105701067.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoBitstream-20160308235749196.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160307105701067.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOpt-20160308235749196.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160307105701067.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPhys-20160308235749196.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160307105701067.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoOptPower-20160308235749196.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160307105701067.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoPlace-20160308235749196.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160307105701067.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoRoute-20160308235749196.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160307105520276.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoSynthesis-20160308235632422.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160307105701067.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportImplemented-20160308235749196.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160307105520276.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160308235632422.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160307105701067.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportImplemented-20160308235749196.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160307105520276.log</location> <location>/home/andrey/git/x393_sata/vivado_logs/VivadoTimingReportSynthesis-20160308235632422.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-phys.dcp</name> <name>vivado_state/x393_sata-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160307105701067.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-phys-20160308235749196.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt-power.dcp</name> <name>vivado_state/x393_sata-opt-power.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160307105701067.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-power-20160308235749196.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-opt.dcp</name> <name>vivado_state/x393_sata-opt.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160307105701067.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-opt-20160308235749196.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-place.dcp</name> <name>vivado_state/x393_sata-place.dcp</name>
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<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160307105701067.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-place-20160308235749196.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-route.dcp</name> <name>vivado_state/x393_sata-route.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160307105701067.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-route-20160308235749196.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393_sata-synth.dcp</name> <name>vivado_state/x393_sata-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160307105520276.dcp</location> <location>/home/andrey/git/x393_sata/vivado_state/x393_sata-synth-20160308235632422.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
ahci/ahci_fsm.v
View file @ 29d789db
...@@ -270,7 +270,8 @@ module ahci_fsm ...@@ -270,7 +270,8 @@ module ahci_fsm
reg [2:0] fsm_jump; reg [2:0] fsm_jump;
wire fsm_next; wire fsm_next;
// reg fsm_next_r; // reg fsm_next_r;
reg fsm_actions; // processing actions reg fsm_actions; // processing actions
reg dis_actions; // disable actions during async jump
reg fsm_act_busy; reg fsm_act_busy;
reg [1:0] fsm_transitions; // processing transitions reg [1:0] fsm_transitions; // processing transitions
reg fsm_preload; // read first sequence data (2 cycles for regen) reg fsm_preload; // read first sequence data (2 cycles for regen)
...@@ -288,7 +289,7 @@ module ahci_fsm ...@@ -288,7 +289,7 @@ module ahci_fsm
wire fsm_wait_act_w = pgm_data[16]; // this action requires waiting for done wire fsm_wait_act_w = pgm_data[16]; // this action requires waiting for done
wire fsm_last_act_w = pgm_data[17]; wire fsm_last_act_w = pgm_data[17];
wire fsm_pre_act_w = fsm_actions && fsm_next; // use it as CS for generated actions (registered) wire fsm_pre_act_w = !dis_actions && fsm_actions && fsm_next; // use it as CS for generated actions (registered)
reg [1:0] async_pend_r; // waiting to process cominit_got reg [1:0] async_pend_r; // waiting to process cominit_got
reg async_from_st; // change to multi-bit if there will be more sources for async transitions reg async_from_st; // change to multi-bit if there will be more sources for async transitions
...@@ -381,6 +382,11 @@ module ahci_fsm ...@@ -381,6 +382,11 @@ module ahci_fsm
else if (fsm_jump[2]) fsm_actions <= 1; else if (fsm_jump[2]) fsm_actions <= 1;
else if (fsm_last_act_w && fsm_next) fsm_actions <= 0; else if (fsm_last_act_w && fsm_next) fsm_actions <= 0;
if (hba_rst) dis_actions <= 0;
else if (|async_pend_r) dis_actions <= 1;
else if (fsm_jump[2]) dis_actions <= 0;
if (fsm_actions && fsm_next) was_last_action_r <= fsm_last_act_w; if (fsm_actions && fsm_next) was_last_action_r <= fsm_last_act_w;
if (hba_rst || pre_jump_w) fsm_transitions <= 0; if (hba_rst || pre_jump_w) fsm_transitions <= 0;
......
ahci/ahci_sata_layers.v
View file @ 29d789db
...@@ -308,8 +308,32 @@ assign debug_phy = debug_phy0; ...@@ -308,8 +308,32 @@ assign debug_phy = debug_phy0;
// .cominit_got (cominit_got), // output wire // .cominit_got (cominit_got), // output wire
// .comwake_got (serr_DW), // output wire // .comwake_got (serr_DW), // output wire
`ifdef DATASCOPE_INCOMING_RAW
assign datascope_di = {5'b0,debug_link[5],datascope0_di[25:0]};// aligns_pair tx assign datascope_di = {5'b0,debug_link[5],datascope0_di[25:0]};// aligns_pair tx
`else
// Mix transmitted alignes pair, but only to the closest group of 6 primitives
reg dbg_was_link5; // alignes pair sent
wire dbg_was_link5_xclk; // alignes pair sent
always @ (posedge datascope_clk) begin
if (dbg_was_link5_xclk) dbg_was_link5 <= 1;
else if (datascope_we) dbg_was_link5 <= 0;
end
pulse_cross_clock #(
.EXTRA_DLY(0)
) dbg_was_link5_i (
.rst (rst), // input
.src_clk (clk), // input
.dst_clk (datascope_clk), // input
.in_pulse (debug_link[5]), // input// is actually a two-cycle
.out_pulse (dbg_was_link5_xclk), // output
.busy() // output
);
assign datascope_di = {dbg_was_link5,datascope0_di[30:0]};// aligns_pair tx
`endif
link #( link #(
.DATA_BYTE_WIDTH(4) .DATA_BYTE_WIDTH(4)
) link ( ) link (
......
ahci/ahci_top.v
View file @ 29d789db
...@@ -1156,310 +1156,271 @@ wire [9:0] xmit_dbg_01; ...@@ -1156,310 +1156,271 @@ wire [9:0] xmit_dbg_01;
`ifdef USE_DATASCOPE `ifdef USE_DATASCOPE
`ifdef DATASCOPE_V2 `ifdef DATASCOPE_V2
reg [ADDRESS_BITS-1:0] datascope_waddr_r; reg [ADDRESS_BITS-1:0] datascope_waddr_r;
reg [1:0] datascope_run; reg [1:0] datascope_run;
// reg [1:0] datascope_run; // reg [1:0] datascope_run;
assign datascope_we = datascope_run[1];
assign datascope_clk = mclk;
assign datascope_waddr = datascope_waddr_r;
assign datascope_di = {
debug_dma_h2d[3], // done_flush_mclk,
debug_dma_h2d[2], // dout_vld,
debug_dma_h2d[1], // dout_re,
debug_dma_h2d[0], // last_DW,
dma_dout[27:16],
debug_dma_h2d[19:18], // 2'b0
debug_dma_h2d[17], // fifo_rd
debug_dma_h2d[16:12], // raddr[4:0]
debug_dma_h2d[11:8], //fifo_do_vld[3:0]
debug_dma_h2d[7], // fifo_dav
debug_dma_h2d[6], // fifo_dav2_w
debug_dma_h2d[5], // fifo_dav2
debug_dma_h2d[4] // flushing_mclk
};
// dma_dout[
always @ (posedge mclk) begin
if (mrst) datascope_run[0] <= 0;
else if (dma_cmd_start) datascope_run[0] <= 1;
else if (dma_cmd_done) datascope_run[0] <= 0;
if (mrst || !datascope_run[0]) datascope_run[1] <= 0; assign datascope_we = datascope_run[1];
else if (dma_dav) datascope_run[1] <= 1; assign datascope_clk = mclk;
assign datascope_waddr = datascope_waddr_r;
if (fsnd_cfis_xmit) datascope_waddr_r <= 0;
else if (datascope_we) datascope_waddr_r <= datascope_waddr_r + 1;
end assign datascope_di = {
/* debug_dma_h2d[3], // done_flush_mclk,
debug_dma_h2d[3], // done_flush_mclk, debug_dma_h2d[2], // dout_vld,
debug_dma_h2d[2], // dout_vld, debug_dma_h2d[1], // dout_re,
debug_dma_h2d[1], // dout_re, debug_dma_h2d[0], // last_DW,
debug_dma_h2d[0], // last_DW,
dma_dout[27:16],
dma_dout[27:16], debug_dma_h2d[19:18], // 2'b0
debug_dma_h2d[19:18], // 2'b0 debug_dma_h2d[17], // fifo_rd
debug_dma_h2d[17], // fifo_rd debug_dma_h2d[16:12], // raddr[4:0]
debug_dma_h2d[16:12], // raddr[4:0] debug_dma_h2d[11:8], //fifo_do_vld[3:0]
debug_dma_h2d[11:8], //fifo_do_vld[3:0]
debug_dma_h2d[7], // fifo_dav
debug_dma_h2d[6], // fifo_dav2_w
debug_dma_h2d[5], // fifo_dav2
debug_dma_h2d[4] // flushing_mclk
debug_dma_h2d
assign debug_dma_h2d = {
14'b0,
17 fifo_rd,
16:12 raddr[4:0],
11: 8 fifo_do_vld[3:0],
7 fifo_dav, debug_dma_h2d[7], // fifo_dav
6 fifo_dav2_w, debug_dma_h2d[6], // fifo_dav2_w
5 fifo_dav2, debug_dma_h2d[5], // fifo_dav2
4 flushing_mclk, debug_dma_h2d[4] // flushing_mclk
};
3 done_flush_mclk,
2 dout_vld, // dma_dout[
1 dout_re,
0 last_DW always @ (posedge mclk) begin
}; if (mrst) datascope_run[0] <= 0;
else if (dma_cmd_start) datascope_run[0] <= 1;
*/ else if (dma_cmd_done) datascope_run[0] <= 0;
//`endif // DATASCOPE_V2
`else if (mrst || !datascope_run[0]) datascope_run[1] <= 0;
//`ifdef DATASCOPE_V1 else if (dma_dav) datascope_run[1] <= 1;
localparam DATASCOPE_CFIS_START=0;
localparam DATASCOPE_INCOMING_POST=32;
reg [ADDRESS_BITS-1:0] datascope_waddr_r=0;
reg [1:0] datascope_run;
reg datascope_link_run; if (fsnd_cfis_xmit) datascope_waddr_r <= 0;
wire dataskope_is_state_send_ready = (debug_in_link[4:0] == 16); else if (datascope_we) datascope_waddr_r <= datascope_waddr_r + 1;
wire dataskope_is_state_idle = (debug_in_link[4:0] == 22);
reg dataskope_was_state_send_ready;
reg [3:0] datascope_id;
wire datascope_incoming_start = debug_in_link[22]; // set_rcvr_wait; // start logging
wire datascope_incoming_started = debug_in_phy[21:20] == 1; // end
wire datascope_incomining_preend = debug_in_phy[21]; // d2h_type_in[1 //`endif // DATASCOPE_V2
reg [2:0] datascope_incoming_run; `else
reg [7:0] datascope_incoming_cntr; //`ifdef DATASCOPE_V1
reg datascope_receive_fis; `ifdef DATASCOPE_FIS_DATA
reg [9:0] datascope_last_jump_addr=0; datascope_timing #(
reg [1:0] datascope_new_jump = 0; .ADDRESS_BITS(10),
reg [15:0] datascope_jump_cntr = 0; .FIS_LEN(5)
) datascope_timing_i (
//last_jump_addr[9:0] .clk (mclk), // input
always @(posedge mclk) begin .rst (mrst), // input
if (mrst) datascope_new_jump[0] <= 0; .soft_write_addr (soft_write_addr), // input[9:0]
else datascope_new_jump[0] <= datascope_last_jump_addr != last_jump_addr; .soft_write_data (soft_write_data), // input[31:0]
.soft_write_en (soft_write_en), // input
.h2d_data (h2d_data), // input[31:0]
.h2d_type (h2d_type), // input[1:0]
.h2d_valid (h2d_valid), // input
.h2d_ready (h2d_ready), // input
.d2h_data (d2h_data), // input[31:0]
.d2h_type (d2h_type), // input[1:0]
.d2h_valid (d2h_valid), // input
.d2h_ready (d2h_ready), // input
.datascope_clk (datascope_clk), // output
.datascope_waddr (datascope_waddr), // output[9:0] reg
.datascope_we (datascope_we), // output
.datascope_di (datascope_di) // output[31:0] reg
);
if (mrst) datascope_new_jump[1] <= 0; `else // DATASCOPE_FIS_DATA
else datascope_new_jump[1] <= datascope_new_jump[0]; localparam DATASCOPE_CFIS_START=0;
localparam DATASCOPE_INCOMING_POST=32;
reg [ADDRESS_BITS-1:0] datascope_waddr_r=0;
reg [1:0] datascope_run;
reg datascope_link_run;
wire datascope_is_state_send_ready = (debug_in_link[4:0] == 16);
wire datascope_is_state_idle = (debug_in_link[4:0] == 22);
reg datascope_was_state_send_ready;
reg [3:0] datascope_id;
wire datascope_incoming_start = debug_in_link[22]; // set_rcvr_wait; // start logging
wire datascope_incoming_started = debug_in_phy[21:20] == 1; //
wire datascope_incomining_preend = debug_in_phy[21]; // d2h_type_in[1
reg [2:0] datascope_incoming_run;
reg [7:0] datascope_incoming_cntr;
reg datascope_receive_fis;
reg [9:0] datascope_last_jump_addr=0;
reg [1:0] datascope_new_jump = 0;
reg [15:0] datascope_jump_cntr = 0;
//last_jump_addr[9:0]
always @(posedge mclk) begin
if (mrst) datascope_new_jump[0] <= 0;
else datascope_new_jump[0] <= datascope_last_jump_addr != last_jump_addr;
if (mrst) datascope_new_jump[1] <= 0;
else datascope_new_jump[1] <= datascope_new_jump[0];
if (mrst) datascope_last_jump_addr <= 0;
if (datascope_new_jump) datascope_last_jump_addr <= last_jump_addr;
if (datascope_we) datascope_jump_cntr <= datascope_jump_cntr+1;
if (mrst) datascope_receive_fis <= 0;
else if (datascope_incoming_start) datascope_receive_fis <= 1;
else if (frcv_get_dsfis ||
frcv_get_psfis ||
frcv_get_rfis ||
frcv_get_sdbfis ||
frcv_get_ufis ||
frcv_get_data_fis ||
frcv_get_ignore) datascope_receive_fis <= 0;
if (mrst) datascope_last_jump_addr <= 0; if (mrst) datascope_incoming_run[0] <= 0;
if (datascope_new_jump) datascope_last_jump_addr <= last_jump_addr; else if (datascope_incoming_start || datascope_receive_fis) datascope_incoming_run[0] <= 1;
else if (datascope_incoming_cntr == 0) datascope_incoming_run[0] <= 0;
if (datascope_we) datascope_jump_cntr <= datascope_jump_cntr+1; if (mrst || datascope_incoming_start) datascope_incoming_run[1] <= 0;
else if (datascope_incoming_run[0] && datascope_incoming_started) datascope_incoming_run[1] <= 1;
else if (datascope_incoming_run[2]) datascope_incoming_run[1] <= 0;
if (mrst || datascope_incoming_start) datascope_incoming_run[2] <= 0;
else if (datascope_incoming_run[1] && datascope_incomining_preend) datascope_incoming_run[2] <= 1;
else if (datascope_incoming_cntr == 0) datascope_incoming_run[2] <= 0;
if (mrst || !datascope_incoming_run[2] ||
datascope_incoming_start ||
datascope_receive_fis) datascope_incoming_cntr <= DATASCOPE_INCOMING_POST;
else if (|datascope_incoming_cntr) datascope_incoming_cntr <= datascope_incoming_cntr - 1;
end
assign datascope_clk = mclk;
assign datascope_waddr = last_jump_addr;
assign datascope_we = &datascope_new_jump;
assign datascope_di = {2'h3, fsnd_pCmdToIssue, xfer_cntr_zero, 2'b0, last_jump_addr[9:0],datascope_jump_cntr};
always @(posedge mclk) begin
if (mrst) datascope_run[0] <= 0;
else if (fsnd_cfis_xmit) datascope_run[0] <= 1;
else if (h2d_valid && h2d_ready && (h2d_type == 2)) datascope_run[0] <= 0;
if (mrst) datascope_link_run <= 0;
else if (datascope_is_state_send_ready && !datascope_was_state_send_ready) datascope_link_run <= 1; // state_send_sof
else if (datascope_is_state_idle) datascope_link_run <= 0; // state_idle
datascope_was_state_send_ready <= datascope_is_state_send_ready;
datascope_run[1] <= datascope_run[0];
if (mrst) datascope_id <= 0;
else if (fsnd_cfis_xmit) datascope_id <= datascope_id + 1;
end
`endif // DATASCOPE_FIS_DATA
if (mrst) datascope_receive_fis <= 0; `endif // DATASCOPE_V1
else if (datascope_incoming_start) datascope_receive_fis <= 1;
else if (frcv_get_dsfis || `endif // USE_DATASCOPE
frcv_get_psfis || endmodule
frcv_get_rfis ||
frcv_get_sdbfis ||
frcv_get_ufis ||
frcv_get_data_fis ||
frcv_get_ignore) datascope_receive_fis <= 0;
if (mrst) datascope_incoming_run[0] <= 0; module datascope_timing #(
else if (datascope_incoming_start || datascope_receive_fis) datascope_incoming_run[0] <= 1; parameter ADDRESS_BITS = 10, // for datascope
else if (datascope_incoming_cntr == 0) datascope_incoming_run[0] <= 0; parameter FIS_LEN = 5 // Record this number of DWORDS in each FIS
)(
input clk,
input rst,
// receiving time punch command and 3-bit tag
input [ADDRESS_BITS-1:0] soft_write_addr,
input [31:0] soft_write_data,
input soft_write_en,
// outgoing FISes
input [31:0] h2d_data, // 32-bit data from the system memory to HBA (dma data)
input [ 1:0] h2d_type, // 0 - data, 1 - FIS head, 2 - FIS END (make FIS_Last?)
input h2d_valid, // output register full
input h2d_ready, // send FIFO has room for data (>= 8? dwords)
// Incoming FISes
// Data/type FIFO, device -> host
input [31:0] d2h_data, // FIFO output data
input [ 1:0] d2h_type, // 0 - data, 1 - FIS head, 2 - R_OK, 3 - R_ERR
input d2h_valid, // Data available from the transport layer in FIFO
input d2h_ready, // This module or DMA consumes DWORD
output datascope_clk,
output reg [ADDRESS_BITS-1:0] datascope_waddr,
output datascope_we,
output reg [31:0] datascope_di
);
if (mrst || datascope_incoming_start) datascope_incoming_run[1] <= 0; `include "includes/ahci_localparams.vh" // @SuppressThisWarning VEditor : Unused localparams
else if (datascope_incoming_run[0] && datascope_incoming_started) datascope_incoming_run[1] <= 1; reg [2:0] punch_tag;
else if (datascope_incoming_run[2]) datascope_incoming_run[1] <= 0; wire write_tag_w = soft_write_en && (soft_write_addr[ADDRESS_BITS-1:0] == HBA_PORT__PunchTime__TAG__ADDR);
reg pend_punch_time;
wire write_punch_time = pend_punch_time && !fis_start && !fis_run && !fis_run_d;
reg fis_run;
reg fis_run_d;
reg fis_we; // recording FIS data (until end or max len)
reg [12:0] fis_len;
reg [12:0] fis_left;
reg [31:0] fis_data;
reg [27:0] cur_time;
reg was_h2d_last;
wire fis_start = (h2d_valid && h2d_ready && (h2d_type == 1)) ||
(d2h_valid && d2h_ready && (d2h_type == 1));
wire fis_end = (d2h_valid? (d2h_valid && d2h_ready && d2h_type[1]): was_h2d_last);
// wire fis_end_we = (fis_left == 0) || fis_end;
wire pre_we_w = fis_run && (d2h_valid?(d2h_valid && d2h_ready):(h2d_valid && h2d_ready));
reg pre_we_r;
reg we_r;
assign datascope_we = we_r;
assign datascope_clk = clk;
always @ (posedge clk) begin
was_h2d_last <= h2d_type[1] && h2d_valid && h2d_ready;
if (rst) cur_time <= 0;
else cur_time <= cur_time + 1;
if (write_tag_w) punch_tag <= soft_write_data[2:0];
if (mrst || datascope_incoming_start) datascope_incoming_run[2] <= 0; if (rst) pend_punch_time <= 0;
else if (datascope_incoming_run[1] && datascope_incomining_preend) datascope_incoming_run[2] <= 1; else if (write_tag_w) pend_punch_time <= 1;
else if (datascope_incoming_cntr == 0) datascope_incoming_run[2] <= 0; else if (write_punch_time) pend_punch_time <= 0;
if (mrst || !datascope_incoming_run[2] || if (write_punch_time || fis_start) datascope_di <= {write_punch_time?{1'b1,punch_tag}:{3'b0,d2h_valid},cur_time};
datascope_incoming_start || else if (fis_we) datascope_di <= fis_data;
datascope_receive_fis) datascope_incoming_cntr <= DATASCOPE_INCOMING_POST; else if (!fis_run && fis_run_d) datascope_di <= {19'h7fff8, fis_len};
else if (|datascope_incoming_cntr) datascope_incoming_cntr <= datascope_incoming_cntr - 1;
end pre_we_r <= pre_we_w || fis_start ;
assign datascope_clk = mclk; we_r <= write_punch_time || fis_start || (fis_we ? pre_we_r : (!fis_run && fis_run_d));
`ifdef DATASCOPE_FIS_DATA
assign datascope_waddr = datascope_waddr_r;
assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || datascope_incoming_run[0] || datascope_link_run;
assign datascope_di = datascope_incoming_run[0]? {d2h_type,
debug_in_link[26], // state idle
debug_in_link[4:0], // encoded state (1 cycle later)
d2h_ready,
d2h_valid,
debug_in_phy[21:20],
datascope_incoming_start,
datascope_incoming_run[2:0],
datascope_id[3:0],
d2h_type[1:0],
frcv_busy,
1'b0,
debug_in_phy[15:8]}:
// d2h_data[8:0]}:
(datascope_run[0]? {h2d_data[31:0]} : {// will appear for fsnd_done || xmit_ok || xmit_err
debug_in_link[7:0],
debug_in_link[31],
debug_in_link[30],
debug_in_link[29], // xmit_ok,
debug_in_link[28], //xmit_err,
debug_in_link[27], // 1'b0,
debug_in_link[26],
debug_in_link[25],
debug_in_link[24], // fsnd_dx_err[1], //fsnd_dx_err[2:0],
debug_in_link[23],
datascope_id[2:0], {12-ADDRESS_BITS{1'b0}}, datascope_waddr_r});
always @(posedge mclk) begin
if (fsnd_cfis_xmit) datascope_waddr_r <= DATASCOPE_CFIS_START; // start from command FIS
/// if (mrst) datascope_waddr_r <= DATASCOPE_CFIS_START;
else if (datascope_we && !(&datascope_waddr_r)) datascope_waddr_r <= datascope_waddr_r + 1;
end
`else
assign datascope_waddr = last_jump_addr;
assign datascope_we = &datascope_new_jump;
assign datascope_di = {2'h3, fsnd_pCmdToIssue, xfer_cntr_zero, 2'b0, last_jump_addr[9:0],datascope_jump_cntr};
`endif
// assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || fsnd_done|| xmit_ok || xmit_err; /// || d2h_ready ;
// assign datascope_we = (datascope_run[0] && h2d_valid && h2d_ready) || d2h_ready || datascope_link_run;
//
// assign datascope_di = {14'h3fff,fsnd_pCmdToIssue, xfer_cntr_zero, datascope_jump_cntr};
// assign datascope_di = d2h_ready? {d2h_type,
/*
*/
/*
assign debug_out[ 4: 0] = debug_states_encoded;
assign debug_out[7: 5] = {
rcvd_dword[CODE_SYNCP],
rcvd_dword[CODE_OKP],
alignes_pair};
assign debug_out[31] = rcvd_dword[CODE_ALIGNP];
assign debug_out[30] = set_send_sof;
assign debug_out[29] = clr_send_rdy;
assign debug_out[28] = state_send_rdy;
assign debug_out[27] = state_send_sof;
assign debug_out[26] = state_idle;
assign debug_out[25] = state_send_data;
assign debug_out[24] = (state_send_sof | set_send_sof & ~alignes_pair);
assign debug_out[23] = (clr_send_sof & ~alignes_pair);
//assign debug_out[15: 5] = debug_to_first_err[14:4];
assign debug_out[22:16] = debug_rcvd_dword[6:0];
assign debug_out[15: 8] = {
debug_was_wait, // state was wait when last CODE_ERRP/CODE_OKP was received
debug_was_idle, // state was idle when last CODE_ERRP/CODE_OKP was received
debug_was_OK_ERR[1:0],
debug_was_state_wait,
debug_was_frame_done,
debug_was_got_escape,
~debug_CODE_SYNCP[1]};
assign datascope_di = d2h_ready? {d2h_type, d2h_data[29:0]}:(datascope_run[0]? {h2d_data[31:0]} : {// will appear for fsnd_done || xmit_ok || xmit_err
debug_in_link[7:0],
debug_in_link[31],
debug_in_link[30],
debug_in_link[29], // xmit_ok,
debug_in_link[28], //xmit_err,
debug_in_link[27], // 1'b0,
debug_in_link[26],
debug_in_link[25],
debug_in_link[24],//fsnd_dx_err[2:0],
debug_in_link[23], debug_in_link[25],
datascope_id[2:0], {12-ADDRESS_BITS{1'b0}}, datascope_waddr_r});
assign debug_out[27] = state_send_sof;
assign debug_out[26] = state_idle;
_out[31] = rcvd_dword[CODE_ALIGNP];
assign debug_out[ 4: 0] = debug_states_encoded;
assign debug_out[7: 5] = {
rcvd_dword[CODE_SYNCP],
rcvd_dword[CODE_OKP],
alignes_pair};
*/
/// assign datascope_we = |datascope_run;
/*
assign datascope_di = datascope_run[0]? {h2d_type, // 2 bits
dma_ct_re[0], // 1 bit
dma_ct_addr[4:0], // 5 bits
//------
dma_ct_data[7:0], //8 bits (lower)
datascope_cntr[3:0], // 4 bits
h2d_data[11:0]} : // 12 bits
{{32-ADDRESS_BITS{1'b0}},datascope_waddr_r};
*/
always @(posedge mclk) begin
if (mrst) datascope_run[0] <= 0;
else if (fsnd_cfis_xmit) datascope_run[0] <= 1;
else if (h2d_valid && h2d_ready && (h2d_type == 2)) datascope_run[0] <= 0;
if (mrst) datascope_link_run <= 0;
else if (dataskope_is_state_send_ready && !dataskope_was_state_send_ready) datascope_link_run <= 1; // state_send_sof
else if (dataskope_is_state_idle) datascope_link_run <= 0; // state_idle
dataskope_was_state_send_ready <= dataskope_is_state_send_ready; if (fis_start) fis_left <= FIS_LEN - 1;
else if (pre_we_w) fis_left <= fis_left - 1;
datascope_run[1] <= datascope_run[0]; if (rst) fis_we <= 0;
else if (fis_start) fis_we <= 1;
else if ((fis_left == 0) || fis_end) fis_we <= 0;
if (rst) fis_run <= 0;
else if (fis_start) fis_run <= 1;
else if (fis_end) fis_run <= 0;
fis_run_d <= fis_run;
if (fis_start) fis_len <= d2h_valid? 0 : 1;
else if (pre_we_w) fis_len <= fis_len + 1;
if (mrst) datascope_id <= 0; if (fis_start || pre_we_w) fis_data <= d2h_valid ? d2h_data : h2d_data;
else if (fsnd_cfis_xmit) datascope_id <= datascope_id + 1;
/// if (fsnd_cfis_xmit) datascope_cntr <= 0; if (rst) datascope_waddr <= 0;
/// else datascope_cntr <= datascope_cntr + 1; else if (we_r) datascope_waddr <= datascope_waddr + 1;
/// if (fsnd_cfis_xmit) datascope_was_busy <= ahci_fis_transmit_busy;
end end
/*
.ct_addr (dma_ct_addr), // output[4:0] reg
.ct_re (dma_ct_re), // output[1:0]
.ct_data (dma_ct_data), // input[31:0]
*/
`endif // DATASCOPE_V1
`endif // USE_DATASCOPE
endmodule endmodule
device/sata_device.v
View file @ 29d789db
...@@ -983,7 +983,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench ...@@ -983,7 +983,7 @@ task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
DEV_TITLE = "Transmission is paused"; DEV_TITLE = "Transmission is paused";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time); $display("[Device] LINK: %s @%t", DEV_TITLE, $time);
linkSendPrim("HOLD"); linkSendPrim("HOLD");
xpause = xpause - 1; // xpause = xpause - 1;
end else begin end else begin
scrambler_value = scrambleFunc({16'b0,scrambler_value[31:16]}); scrambler_value = scrambleFunc({16'b0,scrambler_value[31:16]});
linkSendData(transmit_data[cnt] ^ scrambler_value); linkSendData(transmit_data[cnt] ^ scrambler_value);
......
host/gtx_wrap.v
View file @ 29d789db
...@@ -115,7 +115,8 @@ module gtx_wrap #( ...@@ -115,7 +115,8 @@ module gtx_wrap #(
,output datascope_clk, ,output datascope_clk,
output [ADDRESS_BITS-1:0] datascope_waddr, output [ADDRESS_BITS-1:0] datascope_waddr,
output datascope_we, output datascope_we,
output reg [31:0] datascope_di, // output reg [31:0] datascope_di,
output [31:0] datascope_di,
input datascope_trig // external trigger event for the datascope input datascope_trig // external trigger event for the datascope
`endif `endif
...@@ -1363,6 +1364,47 @@ gtxe2_channel_wrapper( ...@@ -1363,6 +1364,47 @@ gtxe2_channel_wrapper(
`ifdef USE_DATASCOPE `ifdef USE_DATASCOPE
`ifdef DATASCOPE_INCOMING_RAW
datascope_incoming_raw #(
.ADDRESS_BITS (ADDRESS_BITS),
.DATASCOPE_POST_MEAS (DATASCOPE_POST_MEAS)
) datascope_incoming_i (
.clk (xclk), // input
.charisk (rxcharisk_dec_out[1:0]), // input[1:0]
.rxdata (rxdata_dec_out[15:0]), // input[15:0]
.realign (realign), // input
.comma (comma), // input
.aligned (state_aligned), // input
.not_in_table (rxnotintable_dec_out[1:0]), // input[1:0]
.disp_err (rxdisperr_dec_out[1:0]), // input[1:0]
.datascope_arm (other_control[DATASCOPE_START_BIT]), // input
.datascope_clk (datascope_clk), // output
.datascope_waddr (datascope_waddr), // output[9:0]
.datascope_we (datascope_we), // output
.datascope_di (datascope_di), // output[31:0] reg
.datascope_trig (datascope_trig) // input
);
`else // DATASCOPE_INCOMING_RAW
datascope_incoming #(
.ADDRESS_BITS (ADDRESS_BITS),
.DATASCOPE_POST_MEAS (DATASCOPE_POST_MEAS)
) datascope_incoming_i (
.clk (xclk), // input
.charisk (rxcharisk_dec_out[1:0]), // input[1:0]
.rxdata (rxdata_dec_out[15:0]), // input[15:0]
.aligned (state_aligned), // input
.not_in_table (rxnotintable_dec_out[1:0]), // input[1:0]
.disp_err (rxdisperr_dec_out[1:0]), // input[1:0]
.datascope_arm (other_control[DATASCOPE_START_BIT]), // input
.datascope_clk (datascope_clk), // output
.datascope_waddr (datascope_waddr), // output[9:0]
.datascope_we (datascope_we), // output
.datascope_di (datascope_di), // output[31:0] reg
.datascope_trig (datascope_trig) // input
);
`endif // not DATASCOPE_INCOMING_RAW
/*
reg [ADDRESS_BITS - 1:0 ] datascope_post_cntr; reg [ADDRESS_BITS - 1:0 ] datascope_post_cntr;
reg [ADDRESS_BITS - 1:0 ] datascope_waddr_r; reg [ADDRESS_BITS - 1:0 ] datascope_waddr_r;
reg [2:0] datascope_start_r; reg [2:0] datascope_start_r;
...@@ -1410,9 +1452,256 @@ gtxe2_channel_wrapper( ...@@ -1410,9 +1452,256 @@ gtxe2_channel_wrapper(
rxcharisk_dec_out[1:0], // 17:16 rxcharisk_dec_out[1:0], // 17:16
rxdata_dec_out[15:0]}; // 15: 0 rxdata_dec_out[15:0]}; // 15: 0
end end
*/
`endif `endif
always @ (posedge gtrefclk) always @ (posedge gtrefclk)
debug <= ~rxelecidle | debug; debug <= ~rxelecidle | debug;
endmodule
module datascope_incoming_raw#(
parameter ADDRESS_BITS = 10, // for datascope
parameter DATASCOPE_POST_MEAS = 16 // number of measurements to perform after event
)(
input clk, // source-synchronous clock (150MHz)
input [1:0] charisk,
input [15:0] rxdata,
input realign,
input comma,
input aligned,
input [1:0] not_in_table,
input [1:0] disp_err,
input datascope_arm,
output datascope_clk,
output [ADDRESS_BITS-1:0] datascope_waddr,
output datascope_we,
output reg [31:0] datascope_di,
input datascope_trig // external trigger event for the datascope
);
reg [ADDRESS_BITS - 1:0 ] datascope_post_cntr;
reg [ADDRESS_BITS - 1:0 ] datascope_waddr_r;
reg [2:0] datascope_start_r;
wire datascope_event;
reg datascope_event_r;
reg datascope_run;
reg datascope_post_run;
// wire datascope_start_w = other_control[DATASCOPE_START_BIT]; // datascope requires USE_DRP to be defined
wire datascope_stop = (DATASCOPE_POST_MEAS == 0) ? datascope_event: (datascope_post_cntr == 0);
reg [2:0] datascope_trig_r;
assign datascope_waddr = datascope_waddr_r;
assign datascope_we = datascope_run;
assign datascope_clk = clk;
assign datascope_event = (not_in_table) || (disp_err) || realign || (datascope_trig_r[1] && !datascope_trig_r[2]) ;
always @ (posedge clk) begin
datascope_trig_r <= {datascope_trig_r[1:0], datascope_trig};
datascope_start_r <= {datascope_start_r[1:0],datascope_arm};
datascope_event_r <=datascope_event;
if (!datascope_start_r[1]) datascope_run <= 0;
else if (!datascope_start_r[2]) datascope_run <= 1;
else if (datascope_stop) datascope_run <= 0;
if (!datascope_run) datascope_post_run <= 0;
else if (datascope_event_r) datascope_post_run <= 1;
if (!datascope_post_run) datascope_post_cntr <= DATASCOPE_POST_MEAS;
else datascope_post_cntr <= datascope_post_cntr - 1;
if (!datascope_start_r[1] && datascope_start_r[0]) datascope_waddr_r <= 0; // for simulator
else if (datascope_run) datascope_waddr_r <= datascope_waddr_r + 1;
if (datascope_start_r[1]) datascope_di <= {
6'b0,
realign, // 25
comma, // 24
1'b0, // 23
aligned, // 22
not_in_table[1:0], // 21:20
disp_err[1:0], // 19:18
charisk[1:0], // 17:16
rxdata[15:0]}; // 15: 0
end
endmodule
module datascope_incoming#(
parameter ADDRESS_BITS = 10, // for datascope
parameter DATASCOPE_POST_MEAS = 16 // number of measurements to perform after event
)(
input clk, // source-synchronous clock (150MHz)
input [1:0] charisk,
input [15:0] rxdata,
input aligned,
input [1:0] not_in_table,
input [1:0] disp_err,
input datascope_arm,
output datascope_clk,
output [ADDRESS_BITS-1:0] datascope_waddr,
output datascope_we,
output [31:0] datascope_di,
input datascope_trig // external trigger event for the datascope
);
localparam ALIGN_PRIM = 32'h7b4a4abc;
localparam CONT_PRIM = 32'h9999aa7c;
localparam DMAT_PRIM = 32'h3636b57c;
localparam EOF_PRIM = 32'hd5d5b57c;
localparam HOLD_PRIM = 32'hd5d5aa7c;
localparam HOLDA_PRIM = 32'h9595aa7c;
localparam PMACK_PRIM = 32'h9595957c;
localparam PMNAK_PRIM = 32'hf5f5957c;
localparam PMREQ_P_PRIM = 32'h1717b57c;
localparam PMREQ_S_PRIM = 32'h7575957c;
localparam R_ERR_PRIM = 32'h5656b57c;
localparam R_IP_PRIM = 32'h5555b57c;
localparam R_OK_PRIM = 32'h3535b57c;
localparam R_RDY_PRIM = 32'h4a4a957c;
localparam SOF_PRIM = 32'h3737b57c;
localparam SYNC_PRIM = 32'hb5b5957c;
localparam WTRM_PRIM = 32'h5858b57c;
localparam X_RDY_PRIM = 32'h5757b57c;
localparam NUM_NIBBLES = 6;
reg [15:0] rxdata_r;
reg [ 1:0] charisk_r;
wire is_alignp = ({rxdata, rxdata_r} == ALIGN_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_cont = ({rxdata, rxdata_r} == CONT_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_dmat = ({rxdata, rxdata_r} == DMAT_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_eof = ({rxdata, rxdata_r} == EOF_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_hold = ({rxdata, rxdata_r} == HOLD_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_holda = ({rxdata, rxdata_r} == HOLDA_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_pmack = ({rxdata, rxdata_r} == PMACK_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_pmnak = ({rxdata, rxdata_r} == PMNAK_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_pmreq_p = ({rxdata, rxdata_r} == PMREQ_P_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_pmreq_s = ({rxdata, rxdata_r} == PMREQ_S_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_r_err = ({rxdata, rxdata_r} == R_ERR_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_r_ip = ({rxdata, rxdata_r} == R_IP_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_r_ok = ({rxdata, rxdata_r} == R_OK_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_r_rdy = ({rxdata, rxdata_r} == R_RDY_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_sof = ({rxdata, rxdata_r} == SOF_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_sync = ({rxdata, rxdata_r} == SYNC_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_wrtm = ({rxdata, rxdata_r} == WTRM_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_xrdy = ({rxdata, rxdata_r} == X_RDY_PRIM) && ({charisk, charisk_r} == 4'h1);
wire is_data_w = {charisk, charisk_r} == 4'h0;
wire [17:0] is_prim_w = {is_alignp,
is_cont,
is_dmat,
is_eof,
is_hold,
is_holda,
is_pmack,
is_pmnak,
is_pmreq_p,
is_pmreq_s,
is_r_err,
is_r_ip,
is_r_ok,
is_r_rdy,
is_sof,
is_sync,
is_wrtm,
is_xrdy};
wire [ 2:0] is_err_w = {~aligned, |not_in_table, |disp_err};
reg [17:0] is_prim_r;
reg is_data_r;
reg [ 2:0] is_err_r;
reg [17:0] is_prim_r2;
reg is_data_r2;
reg [ 3:0] is_err_r2;
wire [31:0] states = {9'b0, is_err_r2[3:0], is_prim_r2[17:0], is_data_r2}; // to add more states ?
wire [ 4:0] encoded_states_w ={(|states[31:16]),
(|states[31:24]) | (|states[15:8]),
(|states[31:28]) | (|states[23:20]) | (|states[15:12]) | (|states[7:4]),
(|states[31:30]) | (|states[27:26]) | (|states[23:22]) | (|states[19:18]) | (|states[15:14]) | (|states[11:10]) | (|states[7:6]) | (|states[3:2]),
states[31] | states[29] | states[27] | states[25] | states[23] | states[21] | states[19] | states[17] |
states[15] | states[13] | states[11] | states[9] | states[7] | states[5] | states[3] | states[1]};
// wire stop = (DATASCOPE_POST_MEAS == 0) ? datascope_trig: (post_cntr == 0);
reg [5*NUM_NIBBLES-1:0] encoded_states_r3;
reg [ADDRESS_BITS - 1:0 ] post_cntr;
reg post_run;
reg [ADDRESS_BITS - 1:0 ] waddr_r;
reg [2:0] arm_r;
reg [2:0] trig_r;
reg [NUM_NIBBLES-1:0] wen;
reg run_r = 0;
wire event_w = trig_r[1] && !trig_r[2]; // re-clocked single-cycle external trigger
reg event_r;
wire stop = (DATASCOPE_POST_MEAS == 0) ? event_w: (post_cntr == 0);
reg [1:0] we_r=0;
reg msb_in_r;
reg is_aligned_r; // input aligned and got ALIGNp
assign datascope_clk = clk;
assign datascope_waddr = waddr_r;
assign datascope_we = we_r[1];
assign datascope_di = {1'b0, post_run, encoded_states_r3};
always @ (posedge clk) begin
if (!aligned) is_aligned_r <= 0;
else if (is_alignp) is_aligned_r <= 1;
if (!is_aligned_r && !is_alignp) msb_in_r <= 1;
else msb_in_r <= !msb_in_r;
rxdata_r <= rxdata;
charisk_r <= charisk;
arm_r <= {arm_r[1:0], datascope_arm};
trig_r <= {trig_r[1:0],datascope_trig};
if (!arm_r[1]) run_r <= 0;
else if (!arm_r[2]) run_r <= 1;
else if (stop) run_r <= 0;
event_r <= event_w;
if (!run_r) post_run <= 0;
else if (event_r) post_run <= 1;
if (msb_in_r) begin
is_prim_r <= is_prim_w;
is_err_r <= is_err_w;
is_data_r <= is_data_w;
is_prim_r2 <= {18{~(|is_err_r)}} & is_prim_r;
is_err_r2 <= {is_err_r[2],is_err_r[1] & ~is_err_r[2],is_err_r[0] & ~(|is_err_r[2:1]), ~(|is_prim_r) & ~is_data_r & ~(|is_err_r)}; // make errors 1-hot by priority
is_data_r2 <= is_data_r & ~(|is_err_r);
encoded_states_r3 <= {encoded_states_w, encoded_states_r3[5*NUM_NIBBLES-1:5]};
if (!run_r) wen <= 0;
else wen <= {wen[NUM_NIBBLES-2:0],~(|wen[NUM_NIBBLES-2:0])};
we_r[0] <= run_r && wen[NUM_NIBBLES-1];
end
we_r[1] <=we_r[0] && !msb_in_r;
if (!arm_r[1] && arm_r[0]) waddr_r <= 0; // for simulator
else if (we_r[1]) waddr_r <= waddr_r + 1;
if (!post_run) post_cntr <= DATASCOPE_POST_MEAS;
else if (we_r[1]) post_cntr <= post_cntr - 1;
end
endmodule endmodule
host/link.v
View file @ 29d789db
...@@ -37,7 +37,8 @@ module link #( ...@@ -37,7 +37,8 @@ module link #(
// 4 = dword. 4-bytes aligned data transfers TODO 2 = word - easy, 8 = qword - difficult // 4 = dword. 4-bytes aligned data transfers TODO 2 = word - easy, 8 = qword - difficult
parameter DATA_BYTE_WIDTH = 4, parameter DATA_BYTE_WIDTH = 4,
`ifdef SIMULATION `ifdef SIMULATION
parameter ALIGNES_PERIOD = 10 // period of sending ALIGNp pairs // parameter ALIGNES_PERIOD = 10 // period of sending ALIGNp pairs
parameter ALIGNES_PERIOD = 100 // period of sending ALIGNp pairs
`else `else
parameter ALIGNES_PERIOD = 252 // period of sending ALIGNp pairs parameter ALIGNES_PERIOD = 252 // period of sending ALIGNp pairs
`endif `endif
......
includes/ahci_defaults.vh
View file @ 29d789db
, .INIT_00 (256'h0000000000000000000000000001030100000001000000008000000000240020) , .INIT_00 (256'h0000000000000000000000000001030100000001000000008000000000240020)
, .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800) , .INIT_08 (256'h000000000024000600000000000000000000000080000C000000000080000800)
, .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000) , .INIT_09 (256'h000000000000000000000000000000000000000000000000FFFFFFFF00000000)
, .INIT_0B (256'h0000000000000000000000030000003300000000000000000000000000000000) , .INIT_0B (256'h0000000000000000000000000000003300000000000000000000000000000000)
, .INIT_0C (256'h000000000000000000000000000000000000000001010002001000000001FFFE) , .INIT_0C (256'h000000000000000000000000000000000000000001010002001000000001FFFE)
, .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000) , .INIT_0D (256'h000001000000000000000040000000000001FFFE000000008000000000000000)
, .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001) , .INIT_0E (256'h0000000000000000000000000000000000000000000000000000000040000001)
includes/ahci_localparams.vh
View file @ 29d789db
...@@ -793,5 +793,9 @@ ...@@ -793,5 +793,9 @@
// RW: Program address/data for programming AHCI state machine // RW: Program address/data for programming AHCI state machine
localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__ADDR = 'h5d; localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__ADDR = 'h5d;
localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__MASK = 'h3ffff; localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__MASK = 'h3ffff;
localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__DFLT = 'h3; localparam HBA_PORT__PGM_AHCI_SM__PGM_AD__DFLT = 'h0;
// RW: 3-bit tag to add to the recorded timestamp
localparam HBA_PORT__PunchTime__TAG__ADDR = 'h5e;
localparam HBA_PORT__PunchTime__TAG__MASK = 'h7;
localparam HBA_PORT__PunchTime__TAG__DFLT = 'h0;
includes/ahci_types.vh
View file @ 29d789db
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
, .INIT_12 (256'h0000000000555555000000000000000000000000000000000000000000000000) , .INIT_12 (256'h0000000000555555000000000000000000000000000000000000000000000000)
, .INIT_13 (256'h00000000AAAAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF002AAAAA00AA000A) , .INIT_13 (256'h00000000AAAAAAAAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF002AAAAA00AA000A)
, .INIT_14 (256'h000000000000000000000000000000000001555555555550000000000055000D) , .INIT_14 (256'h000000000000000000000000000000000001555555555550000000000055000D)
, .INIT_17 (256'h5555555555555555555555555555555500010005555555550000000000005555) , .INIT_17 (256'h5555555555555555000000000000001500010005555555550000000000005555)
, .INIT_18 (256'h00000000000055550000000000000000AA820000001000140000000000000000) , .INIT_18 (256'h00000000000055550000000000000000AA820000001000140000000000000000)
, .INIT_1B (256'h0000000000005555000000000000000000000000000000000000000000000000) , .INIT_1B (256'h0000000000005555000000000000000000000000000000000000000000000000)
, .INIT_1C (256'h0000000000000000000000000000000000000000800100050000000000000000) , .INIT_1C (256'h0000000000000000000000000000000000000000800100050000000000000000)
py393sata/create_ahci_registers.py
View file @ 29d789db
...@@ -436,9 +436,13 @@ src=[{gN:"PCI_Header", gS: PCIHEAD, gE:PCIHEAD+0x3f, gD:" PCI header emulation w ...@@ -436,9 +436,13 @@ src=[{gN:"PCI_Header", gS: PCIHEAD, gE:PCIHEAD+0x3f, gD:" PCI header emulation w
[{ fS:25, fE:31, fT:RO, fC:0, fD:"Reserved"}, [{ fS:25, fE:31, fT:RO, fC:0, fD:"Reserved"},
{fN:"AnD", fS:24, fT:RW, fC:0, fD:"Address/not data for programming AHCI state machine"}, {fN:"AnD", fS:24, fT:RW, fC:0, fD:"Address/not data for programming AHCI state machine"},
{ fS:18, fE:23, fT:RO, fC:0, fD:"Reserved"}, { fS:18, fE:23, fT:RO, fC:0, fD:"Reserved"},
{fN:"PGM_AD",fS: 0, fE:17, fT:RW, fC:3, fD:"Program address/data for programming AHCI state machine"}, {fN:"PGM_AD",fS: 0, fE:17, fT:RW, fC:0, fD:"Program address/data for programming AHCI state machine"},
]}, ]},
{rN:"PxVS", rS:0x78, rE:0x7f, rD:"Other Port x Vendor Specific", rC: {rN:"PunchTime", rS:0x78, rE:0x7b, rD:"Record current time to the datascope", rC:
[{ fS:3, fE:31, fT:RO, fC:0, fD:"Reserved"},
{fN:"TAG", fS:0, fE:2, fT:RW, fC:0, fD:"3-bit tag to add to the recorded timestamp"},
]},
{rN:"PxVS", rS:0x7c, rE:0x7f, rD:"Other Port x Vendor Specific", rC:
[{ fT:RW, fC:0, fD:"Vendor-specific data - 96 bits"} [{ fT:RW, fC:0, fD:"Vendor-specific data - 96 bits"}
]}, ]},
......
system_defines.vh
View file @ 29d789db
...@@ -5,6 +5,7 @@ ...@@ -5,6 +5,7 @@
`define ALIGN_CLOCKS `define ALIGN_CLOCKS
`define STRAIGHT_XCLK `define STRAIGHT_XCLK
`define USE_DATASCOPE `define USE_DATASCOPE
// `define DATASCOPE_INCOMING_RAW
`define PRELOAD_BRAMS `define PRELOAD_BRAMS
`define AHCI_SATA 1 `define AHCI_SATA 1
`define DEBUG_ELASTIC `define DEBUG_ELASTIC
......
tb/tb_ahci.tf
View file @ 29d789db
...@@ -1347,6 +1347,7 @@ initial begin //Host ...@@ -1347,6 +1347,7 @@ initial begin //Host
maxigp1_print (HBA_PORT__PxSERR__DIAG__X__ADDR << 2,"re-read: HBA_PORT__PxSERR"); // maxigp1_print (HBA_PORT__PxSERR__DIAG__X__ADDR << 2,"re-read: HBA_PORT__PxSERR"); //
//HBA_PORT__PxIS__DHRS__ADDR //HBA_PORT__PxIS__DHRS__ADDR
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 1); // Record current time in datascope with a 3-bit tag==1
maxigp1_print (PXSIG_OFFS32 << 2,"PXSIG_OFFS32"); maxigp1_print (PXSIG_OFFS32 << 2,"PXSIG_OFFS32");
maxigp1_print (PXTFD_OFFS32 << 2,"PXTFD_OFFS32"); maxigp1_print (PXTFD_OFFS32 << 2,"PXTFD_OFFS32");
...@@ -1365,6 +1366,15 @@ initial begin //Host ...@@ -1365,6 +1366,15 @@ initial begin //Host
maxigp1_print (HBA_PORT__PxCMD__FRE__ADDR << 2,"HBA_PORT__PxCMD__FRE__ADDR"); maxigp1_print (HBA_PORT__PxCMD__FRE__ADDR << 2,"HBA_PORT__PxCMD__FRE__ADDR");
maxigp1_print (HBA_PORT__PxSSTS__DET__ADDR << 2,"HBA_PORT__PxSSTS__DET__ADDR"); maxigp1_print (HBA_PORT__PxSSTS__DET__ADDR << 2,"HBA_PORT__PxSSTS__DET__ADDR");
drp_write ('h20b, 'hc401); // bypass, clock align, invert xclk, arm datascope1
// drp_write ('h20b, 'h8401); // bypass, clock align and invert xclk that will stop datascope1
/*
`ifdef USE_DATASCOPE
parameter DATASCOPE_START_BIT = 14, // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
parameter DATASCOPE_POST_MEAS = 256, // 16, // number of measurements to perform after event
`endif
*/
// setup_pio_read_identify_command_simple(512,1); // prdt interrupt for entry 0 // setup_pio_read_identify_command_simple(512,1); // prdt interrupt for entry 0
...@@ -1372,12 +1382,17 @@ initial begin //Host ...@@ -1372,12 +1382,17 @@ initial begin //Host
/// setup_pio_read_identify_command_shifted(1); // prdt interrupt for entry 0 /// setup_pio_read_identify_command_shifted(1); // prdt interrupt for entry 0
/// setup_pio_read_identify_command_multi4(0,27,71,83); // No prdt interrupts /// setup_pio_read_identify_command_multi4(0,27,71,83); // No prdt interrupts
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 2); // Record current time in datascope with a 3-bit tag
setup_dma_read_ext_command_multi4(0,64,64,64); // No prdt interrupts, 4 64-word chunks setup_dma_read_ext_command_multi4(0,64,64,64); // No prdt interrupts, 4 64-word chunks
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 3); // Record current time in datascope with a 3-bit tag
/// setup_pio_read_identify_command_multi4(1,27,64,83); // prdt interrupt for entry 0 /// setup_pio_read_identify_command_multi4(1,27,64,83); // prdt interrupt for entry 0
/// setup_pio_read_identify_command_multi4(1,64,63,64); // prdt interrupt for entry 0 // last used /// setup_pio_read_identify_command_multi4(1,64,63,64); // prdt interrupt for entry 0 // last used
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR"); maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
`ifdef TEST_ABORT_COMMAND `ifdef TEST_ABORT_COMMAND
TESTBENCH_TITLE = "ABORT start";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
// Abort command by clearing ST // Abort command by clearing ST
maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // Enable FR, 0-> ST maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // Enable FR, 0-> ST
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR"); maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
...@@ -1386,6 +1401,8 @@ initial begin //Host ...@@ -1386,6 +1401,8 @@ initial begin //Host
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR"); maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
// maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // Enable FR, 0-> ST // maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // Enable FR, 0-> ST
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR"); maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
TESTBENCH_TITLE = "ABORT end";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
`endif `endif
// TODO change to ifdef - this is for identify command // TODO change to ifdef - this is for identify command
...@@ -1395,8 +1412,10 @@ initial begin //Host ...@@ -1395,8 +1412,10 @@ initial begin //Host
maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // allow DHR only interrupts (PIO setup) maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // allow DHR only interrupts (PIO setup)
maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // clear that interrupt maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // clear that interrupt
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 3); // Record current time in datascope with a 3-bit tag
wait (IRQ); wait (IRQ);
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 4); // Record current time in datascope with a 3-bit tag
// TESTBENCH_TITLE = "Got Identify"; // TESTBENCH_TITLE = "Got Identify";
TESTBENCH_TITLE = "Got D2HRFIS"; TESTBENCH_TITLE = "Got D2HRFIS";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time); $display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
...@@ -1406,10 +1425,11 @@ initial begin //Host ...@@ -1406,10 +1425,11 @@ initial begin //Host
wait (~IRQ); wait (~IRQ);
// Reset command with abort_dma // Reset command with abort_dma
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 5); // Record current time in datascope with a 3-bit tag
maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // ST: 1 -> 0 maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK); // ST: 1 -> 0
repeat (50) @(posedge CLK); repeat (50) @(posedge CLK);
maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK |HBA_PORT__PxCMD__ST__MASK); // ST: 0 -> 1 maxigp1_writep (HBA_PORT__PxCMD__FRE__ADDR << 2, HBA_PORT__PxCMD__FRE__MASK |HBA_PORT__PxCMD__ST__MASK); // ST: 0 -> 1
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 6); // Record current time in datascope with a 3-bit tag
...@@ -1433,7 +1453,8 @@ initial begin //Host ...@@ -1433,7 +1453,8 @@ initial begin //Host
maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // allow only D2H Register interrupts maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__DHRE__MASK); // allow only D2H Register interrupts
maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear global interrupts for port 0 (the only one) maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear global interrupts for port 0 (the only one)
wait (~IRQ); wait (~IRQ);
TESTBENCH_TITLE = "Setting up Identify";
$display("[Testbench]: %s @%t", TESTBENCH_TITLE, $time);
setup_pio_read_identify_command_simple(512,1); // prdt interrupt for entry 0 setup_pio_read_identify_command_simple(512,1); // prdt interrupt for entry 0
maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR"); maxigp1_print (HBA_PORT__PxCI__CI__ADDR << 2,"HBA_PORT__PxCI__CI__ADDR");
maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__PSE__MASK); // allow PS only interrupts (PIO setup) maxigp1_writep (HBA_PORT__PxIE__PSE__ADDR << 2, HBA_PORT__PxIE__PSE__MASK); // allow PS only interrupts (PIO setup)
...@@ -1445,6 +1466,7 @@ initial begin //Host ...@@ -1445,6 +1466,7 @@ initial begin //Host
maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIS__PSS__MASK); // clear PS interrupt maxigp1_writep (HBA_PORT__PxIS__PSS__ADDR << 2, HBA_PORT__PxIS__PSS__MASK); // clear PS interrupt
maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear global interrupts maxigp1_writep (GHC__IS__IPS__ADDR << 2, 1); // clear global interrupts
wait (~IRQ); wait (~IRQ);
maxigp1_writep (HBA_PORT__PunchTime__TAG__ADDR << 2, 7); // Record current time in datascope with a 3-bit tag
// end of the second identify insertion // end of the second identify insertion
......
tb_ahci_01.sav
View file @ 29d789db
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Mon Mar 7 17:54:44 2016 [*] Wed Mar 9 06:40:17 2016
[*] [*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160307105210141.fst" [dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160308230522426.fst"
[dumpfile_mtime] "Mon Mar 7 17:54:09 2016" [dumpfile_mtime] "Wed Mar 9 06:07:30 2016"
[dumpfile_size] 15120516 [dumpfile_size] 14983742
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav" [savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 32540300 [timestart] 32861000
[size] 1817 609 [size] 1823 1180
[pos] 1923 0 [pos] 1920 0
*-16.022064 32722870 32476228 47988010 32736600 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-15.050610 32927500 32882854 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci. [treeopen] tb_ahci.
[treeopen] tb_ahci.axi_read_addr. [treeopen] tb_ahci.axi_read_addr.
[treeopen] tb_ahci.dev. [treeopen] tb_ahci.dev.
...@@ -33,6 +33,7 @@ ...@@ -33,6 +33,7 @@
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.scrambler.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.genblk1.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel. [treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.gtxe2_channel_wrapper.gtx_gpl.channel.
...@@ -53,6 +54,7 @@ ...@@ -53,6 +54,7 @@
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i. [treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i. [treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_write_i. [treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_write_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.
[treeopen] tb_ahci.elastic1632_fast_i. [treeopen] tb_ahci.elastic1632_fast_i.
[treeopen] tb_ahci.elastic1632_slow_i. [treeopen] tb_ahci.elastic1632_slow_i.
[treeopen] tb_ahci.read_sipo_meas. [treeopen] tb_ahci.read_sipo_meas.
...@@ -61,10 +63,10 @@ ...@@ -61,10 +63,10 @@
[treeopen] tb_ahci.simul_axi_hp_wr_i.waddr_i. [treeopen] tb_ahci.simul_axi_hp_wr_i.waddr_i.
[treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i. [treeopen] tb_ahci.simul_axi_hp_wr_i.wdata_i.
[treeopen] tb_ahci.simul_axi_read_i. [treeopen] tb_ahci.simul_axi_read_i.
[sst_width] 252 [sst_width] 259
[signals_width] 349 [signals_width] 250
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 259 [sst_vpaned_height] 687
@820 @820
tb_ahci.TESTBENCH_TITLE[639:0] tb_ahci.TESTBENCH_TITLE[639:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.oob.HOST_OOB_TITLE[639:0]
...@@ -1819,6 +1821,24 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.tfd_drq ...@@ -1819,6 +1821,24 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.tfd_drq
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.tfd_sts[7:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.tfd_sts[7:0]
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fis_first_vld tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fis_first_vld
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.ssts_det[3:0]
@200
-
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_preload
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_pre_act_w
[color] 7
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_actions
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.fsm_next
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
@800028
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
@1001200
-group_end
@c00200 @c00200
-other -other
@28 @28
...@@ -2086,9 +2106,11 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_dcount[3:0] ...@@ -2086,9 +2106,11 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.fis_dcount[3:0]
-group_end -group_end
@1401200 @1401200
-ahci_fis_receive -ahci_fis_receive
@c00200 @800200
-ahci_fis_transmit -ahci_fis_transmit
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.pcmd_st
tb_ahci.dut.sata_top.ahci_top_i.pcmd_st_cleared
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.xmit_ok tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.xmit_ok
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.xmit_err tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.xmit_err
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.todev_full_r tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.todev_full_r
...@@ -2206,7 +2228,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_pending ...@@ -2206,7 +2228,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_pending
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_GHC_GHC tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_GHC_GHC
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_GHC__IS tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_GHC__IS
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_ghc tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_ghc
@800022 @c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[6:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[6:0]
@28 @28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[6:0] (0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[6:0]
...@@ -2216,9 +2238,9 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[6:0] ...@@ -2216,9 +2238,9 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[6:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[6:0] (4)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[6:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[6:0] (5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[6:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[6:0] (6)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_first[6:0]
@1001200 @1401200
-group_end -group_end
@800022 @c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_next[6:1] tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_next[6:1]
@28 @28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_next[6:1] (0)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.update_next[6:1]
...@@ -2238,6 +2260,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.updating[6:1] ...@@ -2238,6 +2260,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.updating[6:1]
(5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.updating[6:1] (5)tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.updating[6:1]
@1001200 @1001200
-group_end -group_end
@1401200
-group_end -group_end
@200 @200
- -
...@@ -2337,7 +2360,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prd_rd ...@@ -2337,7 +2360,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.prd_rd
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_addr[31:1] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.data_addr[31:1]
@1001200 @1001200
-group_end -group_end
@1401200 @1000200
-ahci_fis_transmit -ahci_fis_transmit
@c00200 @c00200
-ahci_sata_layers -ahci_sata_layers
...@@ -3023,7 +3046,6 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.fifo_do_vld[3:0] ...@@ -3023,7 +3046,6 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.fifo_do_vld[3:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.ahci_dma_rd_stuff_i.din[31:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.ahci_dma_rd_stuff_i.din[31:0]
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.ahci_dma_rd_stuff_i.dm[1:0] tb_ahci.dut.sata_top.ahci_top_i.ahci_dma_i.ahci_dma_rd_fifo_i.ahci_dma_rd_stuff_i.dm[1:0]
tb_ahci.dut.sata_top.ahci_top_i.datascope_run[1:0]
@22 @22
tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0] tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0]
@c00022 @c00022
...@@ -4067,9 +4089,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0] ...@@ -4067,9 +4089,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.rcvd_dword[15:0]
-group_end -group_end
@28 @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.next_will_be_data tb_ahci.dut.sata_top.ahci_sata_layers_i.link.next_will_be_data
@29
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_rcvr_data tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_rcvr_data
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_data tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_data
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_rcvr_shold tb_ahci.dut.sata_top.ahci_sata_layers_i.link.set_rcvr_shold
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_shold tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_rcvr_shold
...@@ -5078,9 +5098,8 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txreset ...@@ -5078,9 +5098,8 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txreset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxreset tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.rxreset
@1401200 @1401200
-sipo_meas -sipo_meas
@800200
-gtx
@c00200 @c00200
-gtx
-elastic -elastic
@22 @22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.dbg_di[31:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.elastic1632_i.dbg_di[31:0]
...@@ -5285,9 +5304,8 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0] ...@@ -5285,9 +5304,8 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
-group_end -group_end
@1000200 @1000200
-gtx8x10enc -gtx8x10enc
@1401200
-gtx -gtx
@200
-
@800200 @800200
-device -device
@820 @820
...@@ -5304,7 +5322,7 @@ tb_ahci.dev.linkTransmitFIS.cnt ...@@ -5304,7 +5322,7 @@ tb_ahci.dev.linkTransmitFIS.cnt
tb_ahci.dev.DEV_DATA tb_ahci.dev.DEV_DATA
@1000200 @1000200
-linkTransmitFIS -linkTransmitFIS
@200 @201
- -
@820 @820
tb_ahci.dev.linkMonitorFIS.rprim[111:0] tb_ahci.dev.linkMonitorFIS.rprim[111:0]
...@@ -5357,57 +5375,27 @@ tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.TXN ...@@ -5357,57 +5375,27 @@ tb_ahci.dev.phy.gtx_wrapper.gtx_gpl.channel.tx.TXN
tb_ahci.dev.linkSendPrim.type[111:0] tb_ahci.dev.linkSendPrim.type[111:0]
@1000200 @1000200
-device -device
@c00200 @800200
-datascope -datascope
@200
-
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in0[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in1[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in2[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_in3[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_r[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.debug_rd_r
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.dma_ct_busy
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.chead_bsy
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.todev_ready
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.any_cmd_start
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.acfis_xmit_pend_r
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.cfis_acmd_left_r[4:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.cfis_acmd_left_out_r[4:0]
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.fis_data_valid tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.write_punch_time
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_stb tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.fis_start
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re_w tb_ahci.dut.sata_top.ahci_top_i.datascope_we
@c00022 @c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re_r[2:0] tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0]
@28 @28
(0)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re_r[2:0] (0)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re_r[2:0] (1)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.ct_re_r[2:0] (2)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0]
@1401200 @1401200
-group_end -group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.fsnd_cfis_xmit
@200
-
@28
tb_ahci.dut.sata_top.ahci_top_i.fsnd_done
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_busy
tb_ahci.dut.sata_top.ahci_top_i.xmit_err
tb_ahci.dut.sata_top.ahci_top_i.xmit_ok
@22
tb_ahci.dut.sata_top.ahci_top_i.h2d_data[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.h2d_ready
tb_ahci.dut.sata_top.ahci_top_i.h2d_type[1:0]
tb_ahci.dut.sata_top.ahci_top_i.h2d_valid
@22
tb_ahci.dut.sata_top.ahci_top_i.data_out_dwords[11:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.datascope_clk
@c00022 @c00022
tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0] tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
@28 @28
...@@ -5445,48 +5433,341 @@ tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0] ...@@ -5445,48 +5433,341 @@ tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0] (31)tb_ahci.dut.sata_top.ahci_top_i.datascope_di[31:0]
@1401200 @1401200
-group_end -group_end
@800022 @200
tb_ahci.dut.sata_top.ahci_top_i.datascope_run[1:0] -
@28 @28
(0)tb_ahci.dut.sata_top.ahci_top_i.datascope_run[1:0] tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.was_h2d_last
(1)tb_ahci.dut.sata_top.ahci_top_i.datascope_run[1:0] @c00022
@1001200 tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.h2d_type[1:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.h2d_type[1:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.h2d_type[1:0]
@1401200
-group_end -group_end
@22 @22
tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0] tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.h2d_data[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.h2d_valid
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.h2d_ready
@c00022 @c00022
tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr_r[9:0] tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.d2h_type[1:0]
@28 @28
(0)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr_r[9:0] (0)tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.d2h_type[1:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr_r[9:0] (1)tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.d2h_type[1:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr_r[9:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr_r[9:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr_r[9:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr_r[9:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr_r[9:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr_r[9:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr_r[9:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr_r[9:0]
@1401200 @1401200
-group_end -group_end
@22
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.d2h_data[31:0]
@28 @28
tb_ahci.dut.sata_top.ahci_top_i.datascope_we tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.d2h_valid
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.d2h_ready
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.we_r
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.punch_tag[2:0]
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.fis_start
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.pend_punch_time
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.write_tag_w
@22
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.cur_time[27:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.fis_end
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.fis_we
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.fis_run
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.fis_run_d
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.fis_start
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.pre_we_w
@22
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.fis_len[12:0]
tb_ahci.dut.sata_top.ahci_top_i.datascope_timing_i.fis_left[12:0]
@1000200
-datascope
@c00200
-datascope1
@28
(26)tb_ahci.dut.sata_top.ahci_sata_layers_i.debug_link[31:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.dbg_was_link5
tb_ahci.dut.sata_top.ahci_top_i.datascope1_clk
@c00022 @c00022
tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0] tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(10)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(11)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(12)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(13)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(14)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(15)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(16)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(17)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(18)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(19)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(20)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(21)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(22)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(23)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(24)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(25)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(26)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(27)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(28)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(29)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(30)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
(31)tb_ahci.dut.sata_top.ahci_top_i.datascope1_di[31:0]
@1401200
-group_end
@c00022
tb_ahci.dut.sata_top.ahci_top_i.datascope1_waddr[9:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.datascope1_waddr[9:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.datascope1_waddr[9:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.datascope1_waddr[9:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.datascope1_waddr[9:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.datascope1_waddr[9:0]
(5)tb_ahci.dut.sata_top.ahci_top_i.datascope1_waddr[9:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.datascope1_waddr[9:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.datascope1_waddr[9:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.datascope1_waddr[9:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.datascope1_waddr[9:0]
@1401200
-group_end
@28 @28
(0)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0] tb_ahci.dut.sata_top.ahci_top_i.datascope1_we
(1)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_trig
(2)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0] @c00022
(3)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
(4)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0] @28
(5)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0] (0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
(6)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0] (1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
(7)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0] (2)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
(8)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0] (3)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
(9)tb_ahci.dut.sata_top.ahci_top_i.datascope_waddr[9:0] (4)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.other_control[15:0]
@1401200 @1401200
-group_end -group_end
-datascope @28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_arm
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.post_run
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.msb_in_r
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.run_r
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.wen[5:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.wen[5:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.wen[5:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.wen[5:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.wen[5:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.wen[5:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.wen[5:0]
@1401200
-group_end
@c00028
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.we_r[1:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.we_r[1:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.we_r[1:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_data_w
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
(16)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
(17)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_w[17:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_data_r
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
(16)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
(17)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_prim_r[17:0]
@1401200
-group_end
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(16)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(17)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(18)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(19)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(20)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(21)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(22)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(23)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(24)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(25)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(26)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(27)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(28)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(29)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(30)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
(31)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.states[31:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.is_data_r2
@800022
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_w[4:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_w[4:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_w[4:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_w[4:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_w[4:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_w[4:0]
@1001200
-group_end
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(16)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(17)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(18)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(19)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(20)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(21)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(22)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(23)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(24)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(25)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(26)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(27)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(28)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
(29)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.encoded_states_r3[29:0]
@1401200
-group_end
@c00022
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(1)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(2)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(3)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(4)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(5)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(6)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(7)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(8)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(9)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(10)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(11)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(12)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(13)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(14)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(15)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(16)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(17)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(18)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(19)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(20)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(21)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(22)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(23)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(24)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(25)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(26)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(27)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(28)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(29)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(30)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
(31)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.datascope_di[31:0]
@1401200
-group_end
@28
(0)tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.we_r[1:0]
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.waddr_r[9:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.datascope_incoming_i.msb_in_r
@200
-
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.link.is_cont_p_w
@1401200
-datascope1
@c00200 @c00200
-frequency_meter -frequency_meter
@200 @200
......
x393_sata.bit
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