debugging read/write registers (1ccc21c0) · Commits · Elphel / x393_sata

ahci/ahci_fis_receive.v

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -336,7 +336,8 @@ localparam DATA_TYPE_ERR = 3;
	tf_err_sts <= tf_err_sts & {8'hff,clear_bsy_drq,3'h7,clear_bsy_drq,3'h7} \| {8'h0,set_bsy,3'h0,clear_bsy_set_drq,3'h0};		tf_err_sts <= tf_err_sts & {8'hff,clear_bsy_drq,3'h7,clear_bsy_drq,3'h7} \| {8'h0,set_bsy,3'h0,clear_bsy_set_drq,3'h0};
	else if (set_sts_7f \|\| set_sts_80) tf_err_sts <= {tf_err_sts[15:8],set_sts_80,{7{set_sts_7f}}} ;		else if (set_sts_7f \|\| set_sts_80) tf_err_sts <= {tf_err_sts[15:8],set_sts_80,{7{set_sts_7f}}} ;

	reg_we <= reg_we_w \|\| update_sig_r \|\| update_err_sts_r \|\| update_prdbc_r;		if (hba_rst) reg_we <= 0;
			else reg_we <= reg_we_w \|\| update_sig_r \|\| update_err_sts_r \|\| update_prdbc_r;

	if (reg_we_w) reg_addr <= reg_addr_r;		if (reg_we_w) reg_addr <= reg_addr_r;
	else if (update_err_sts_r) reg_addr <= PXTFD_OFFS32;		else if (update_err_sts_r) reg_addr <= PXTFD_OFFS32;

ahci/ahci_top.v

+31 −4

Original line number	Original line	Diff line number	Diff line
	@@ -202,16 +202,25 @@ module ahci_top#(
	wire [ADDRESS_BITS-1:0] regs_raddr;		wire [ADDRESS_BITS-1:0] regs_raddr;
	wire [31:0] regs_din_from_freceive;		wire [31:0] regs_din_from_freceive;
	wire [31:0] regs_dout;		wire [31:0] regs_dout;

			reg en_port;
			wire [1:0] regs_re = en_port ? regs_re_ftransmit : 2'b0; // [0] - re, [1] - regen
			wire regs_we = en_port ? ( regs_we_freceive \| regs_we_acs) : 1'b0;


	wire [ADDRESS_BITS-1:0] regs_addr = ({ADDRESS_BITS{regs_we_freceive}} & regs_waddr) \|		wire [ADDRESS_BITS-1:0] regs_addr = ({ADDRESS_BITS{regs_we_freceive}} & regs_waddr) \|
	({ADDRESS_BITS{regs_re_ftransmit[0]}} & regs_raddr) \|		({ADDRESS_BITS{regs_re_ftransmit[0]}} & regs_raddr) \|
	// ({ADDRESS_BITS{regs_re_fsm[0] \| regs_we_acs}} & regs_saddr);
	({ADDRESS_BITS{regs_we_acs}} & regs_saddr);		({ADDRESS_BITS{regs_we_acs}} & regs_saddr);


			/*
			wire [ADDRESS_BITS-1:0] regs_addr = ({ADDRESS_BITS{en_port & regs_we_freceive}} & regs_waddr) \|
			({ADDRESS_BITS{en_port & regs_re_ftransmit[0]}} & regs_raddr) \|
			({ADDRESS_BITS{en_port & regs_we_acs}} & regs_saddr);
			*/
	wire [31:0] regs_din = ({32{regs_we_freceive}} & regs_din_from_freceive) \|		wire [31:0] regs_din = ({32{regs_we_freceive}} & regs_din_from_freceive) \|
	({32{regs_we_acs}} & regs_din_from_acs);		({32{regs_we_acs}} & regs_din_from_acs);
	// wire [1:0] regs_re = regs_re_ftransmit \| regs_re_fsm; // [0] - re, [1] - regen		// wire [1:0] regs_re = regs_re_ftransmit \| regs_re_fsm; // [0] - re, [1] - regen
	wire [1:0] regs_re = regs_re_ftransmit; // [0] - re, [1] - regen
	wire regs_we = regs_we_freceive \| regs_we_acs;


	//---------------------		//---------------------
	@@ -423,6 +432,24 @@ module ahci_top#(
	wire pxci0_clear; // PxCI clear		wire pxci0_clear; // PxCI clear
	wire pxci0; // pxCI current value		wire pxci0; // pxCI current value

			// Async FF
			always @ (posedge mrst or posedge mclk) begin
			if (mrst) en_port <= 0;
			else en_port <= 1;
			end

			/*
			reg [1:0] port_en; //disable port signals until initialized from the hardware (currently - PLL)
			wire ports_rst = ~port_en[1];
			always @ (posedge mclk) begin
			if (port_arst_any) port_en[0] <= 0;
			else if (mrst) port_en[0] <= 1;

			if (port_arst_any) port_en[1] <= 0;
			else if (!mrst && port_en[0]) port_en[1] <= 1;

			end
			*/


	ahci_fsm// #(		ahci_fsm// #(

ahci/axi_ahci_regs.v

+2 −7

Original line number	Original line	Diff line number	Diff line
	@@ -187,13 +187,8 @@ module axi_ahci_regs#(
	reg [2:0] arst_r = ~0; // previous state of arst		reg [2:0] arst_r = ~0; // previous state of arst
	reg wait_first_access = RESET_TO_FIRST_ACCESS; // keep port reset until first access		reg wait_first_access = RESET_TO_FIRST_ACCESS; // keep port reset until first access
	wire any_access = bram_wen_r \|\| bram_ren[0];		wire any_access = bram_wen_r \|\| bram_ren[0];
	// reg bram_ren0_r;
	// wire [1:0] bram_ren_w = {bram_ren0_r, bram_ren[0] & ~write_busy_w}; // FIXED: axibram_read does not mask bram_ren and bram_regen with dev_ready !


	// assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen ? bram_waddr : pre_awaddr);
	assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);		assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);
	// assign bram_addr = bram_ren_w[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);

	assign hba_arst = hba_rst_r; // hba _reset (currently does ~ the same as port reset)		assign hba_arst = hba_rst_r; // hba _reset (currently does ~ the same as port reset)
	assign port_arst = port_rst_r; // port _reset by software		assign port_arst = port_rst_r; // port _reset by software

host/sata_phy.v

+47 −23

Original line number	Original line	Diff line number	Diff line
	@@ -214,14 +214,49 @@ end
	wire usrpll_locked;		wire usrpll_locked;

	// make tx/rxreset synchronous to gtrefclk - gather singals from different domains: async, aclk, usrclk2, gtrefclk		// make tx/rxreset synchronous to gtrefclk - gather singals from different domains: async, aclk, usrclk2, gtrefclk
			localparam [7:0] RST_TIMER_LIMIT = 8'b1000;
	reg rxreset_f;		reg rxreset_f;
	reg txreset_f;		reg txreset_f;
	reg rxreset_f_r;		reg rxreset_f_r;
	reg txreset_f_r;		reg txreset_f_r;
	reg rxreset_f_rr;		reg rxreset_f_rr;
	reg txreset_f_rr;		reg txreset_f_rr;
	always @ (posedge gtrefclk)		//reg pre_sata_reset_done;
	begin		reg sata_areset;
			reg [2:0] sata_reset_done_r;
			reg [7:0] rst_timer;
			//reg rst_r = 1;
			assign rst = !sata_reset_done_r;

			assign sata_reset_done = sata_reset_done_r[1];


			// generate internal reset after a clock is established
			// !!!ATTENTION!!!
			// async rst block
			//localparam [7:0] RST_TIMER_LIMIT = 8'b1000;
			/*
			always @ (posedge clk or posedge extrst)
			// rst_timer <= extrst \| ~cplllock \| ~usrpll_locked ? 8'h0 : sata_reset_done ? rst_timer : rst_timer + 1'b1;
			if (extrst) rst_timer <= 0;
			else if (~cplllock \| ~usrpll_locked) rst_timer <= 0;
			else if (!sata_reset_done) rst_timer <= rst_timer + 1;
			// else rst_timer <= ~cplllock \| ~usrpll_locked ? 8'h0 : sata_reset_done ? rst_timer : rst_timer + 1'b1;

			always @ (posedge clk or posedge extrst)
			if (extrst) rst_r <= 1;
			else if (~\|rst_timer) rst_r <= 0;
			else rst_r <= !sata_reset_done;
			// else rst_r <= ~\|rst_timer ? 1'b0 : sata_reset_done ? 1'b0 : 1'b1;
			///assign sata_reset_done = rst_timer == RST_TIMER_LIMIT;
			*/
			always @ (posedge clk or sata_areset) begin
			if (sata_areset) sata_reset_done_r <= 0;
			else sata_reset_done_r <= {sata_reset_done_r[1:0], 1'b1};
			end


			always @ (posedge gtrefclk) begin
	// rxreset_f <= ~cplllock \| cpllreset \| rxreset_oob & gtx_configured;		// rxreset_f <= ~cplllock \| cpllreset \| rxreset_oob & gtx_configured;
	// txreset_f <= ~cplllock \| cpllreset;		// txreset_f <= ~cplllock \| cpllreset;

	@@ -232,8 +267,13 @@ begin
	rxreset_f_r <= rxreset_f;		rxreset_f_r <= rxreset_f;
	txreset_f_rr <= txreset_f_r;		txreset_f_rr <= txreset_f_r;
	rxreset_f_rr <= rxreset_f_r;		rxreset_f_rr <= rxreset_f_r;
	end

			if (!(cplllock && usrpll_locked)) rst_timer <= RST_TIMER_LIMIT;
			else if (\|rst_timer) rst_timer <= rst_timer - 1;

			sata_areset <= !(cplllock && usrpll_locked && !(\|rst_timer));

			end
	assign rxreset = rxreset_f_rr;		assign rxreset = rxreset_f_rr;
	assign txreset = txreset_f_rr;		assign txreset = txreset_f_rr;
	assign cpllreset = extrst;		assign cpllreset = extrst;
	@@ -249,6 +289,10 @@ always @ (posedge clk or posedge extrst)
	else gtx_configured <= gtx_ready \| gtx_configured;		else gtx_configured <= gtx_ready \| gtx_configured;






	// issue partial tx reset to restore functionality after oob sequence. Let it lasts 8 clock lycles		// issue partial tx reset to restore functionality after oob sequence. Let it lasts 8 clock lycles
	reg [3:0] txpcsreset_cnt;		reg [3:0] txpcsreset_cnt;
	wire txpcsreset_stop;		wire txpcsreset_stop;
	@@ -275,26 +319,6 @@ always @ (posedge clk or posedge extrst)
	if (extrst) rxreset_oob_cnt <= 1;		if (extrst) rxreset_oob_cnt <= 1;
	else rxreset_oob_cnt <= rst \| ~rxreset_req ? 4'h0 : rxreset_oob_stop ? rxreset_oob_cnt : rxreset_oob_cnt + 1'b1;		else rxreset_oob_cnt <= rst \| ~rxreset_req ? 4'h0 : rxreset_oob_stop ? rxreset_oob_cnt : rxreset_oob_cnt + 1'b1;

	// generate internal reset after a clock is established
	// !!!ATTENTION!!!
	// async rst block
	reg [7:0] rst_timer;
	reg rst_r;
	localparam [7:0] RST_TIMER_LIMIT = 8'b1000;
	always @ (posedge clk or posedge extrst)
	// rst_timer <= extrst \| ~cplllock \| ~usrpll_locked ? 8'h0 : sata_reset_done ? rst_timer : rst_timer + 1'b1;
	if (extrst) rst_timer <= 1;
	else rst_timer <= ~cplllock \| ~usrpll_locked ? 8'h0 : sata_reset_done ? rst_timer : rst_timer + 1'b1;

	assign rst = rst_r;
	always @ (posedge clk or posedge extrst)
	if (extrst) rst_r <= 1;
	else if (~\|rst_timer) rst_r <= 0;
	else rst_r <= !sata_reset_done;

	// else rst_r <= ~\|rst_timer ? 1'b0 : sata_reset_done ? 1'b0 : 1'b1;

	assign sata_reset_done = rst_timer == RST_TIMER_LIMIT;

	/*		/*
	* USRCLKs generation. USRCLK @ 150MHz, same as TXOUTCLK; USRCLK2 @ 75Mhz -> sata_clk === sclk		* USRCLKs generation. USRCLK @ 150MHz, same as TXOUTCLK; USRCLK2 @ 75Mhz -> sata_clk === sclk

tb/tb_ahci.tf

+11 −5

Original line number	Original line	Diff line number	Diff line
	@@ -653,7 +653,7 @@ localparam MAXIGP1 = 32'h80000000; // Start of the MAXIGP1 address range (use ah
	end		end
	endtask		endtask

	//localparam CLB_OFFS32 = 'h200; // # In the second half of the register space (0x800..0xbff - 1KB)		localparam CLB_OFFS32 = 'h200; // # In the second half of the register space (0x800..0xbff - 1KB)
	localparam HBA_OFFS32 = 0;		localparam HBA_OFFS32 = 0;
	localparam HBA_PORT0_OFFS32 = 'h40;		localparam HBA_PORT0_OFFS32 = 'h40;
	localparam PXSIG_OFFS32 = HBA_OFFS32 + HBA_PORT0_OFFS32 + 'h9;		localparam PXSIG_OFFS32 = HBA_OFFS32 + HBA_PORT0_OFFS32 + 'h9;
	@@ -672,10 +672,16 @@ initial begin //Host

	maxigp1_writep (PXSIG_OFFS32 << 2, 'h12345678); //		maxigp1_writep (PXSIG_OFFS32 << 2, 'h12345678); //
	maxigp1_writep (PXTFD_OFFS32 << 2, 'h87654321); //		maxigp1_writep (PXTFD_OFFS32 << 2, 'h87654321); //
			maxigp1_writep (CLB_OFFS32 << 2, 'h12345678); //
			maxigp1_writep ((CLB_OFFS32+1) << 2, 'h87654321); //


			maxigp1_print (PXSIG_OFFS32 << 2); // OK to read wrong - it is RO with default 'hffffffff
			maxigp1_print (PXTFD_OFFS32 << 2); // OK to read wrong - it is RO with default 0
			maxigp1_print (CLB_OFFS32 << 2); //
			maxigp1_print ((CLB_OFFS32+1) << 2); //


	maxigp1_print (PXSIG_OFFS32 << 2);
	maxigp1_print (PXTFD_OFFS32 << 2);


	maxigp1_print (PCI_Header__CAP__CAP__ADDR << 2);		maxigp1_print (PCI_Header__CAP__CAP__ADDR << 2);

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