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x393_sata
Commit 1ccc21c0 authored by Andrey Filippov's avatar Andrey Filippov
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debugging read/write registers

parent 4f64364b
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Showing with 195 additions and 65 deletions
ahci/ahci_fis_receive.v
View file @ 1ccc21c0
......@@ -336,7 +336,8 @@ localparam DATA_TYPE_ERR = 3;
tf_err_sts <= tf_err_sts & {8'hff,clear_bsy_drq,3'h7,clear_bsy_drq,3'h7} | {8'h0,set_bsy,3'h0,clear_bsy_set_drq,3'h0};
else if (set_sts_7f || set_sts_80) tf_err_sts <= {tf_err_sts[15:8],set_sts_80,{7{set_sts_7f}}} ;
reg_we <= reg_we_w || update_sig_r || update_err_sts_r || update_prdbc_r;
if (hba_rst) reg_we <= 0;
else reg_we <= reg_we_w || update_sig_r || update_err_sts_r || update_prdbc_r;
if (reg_we_w) reg_addr <= reg_addr_r;
else if (update_err_sts_r) reg_addr <= PXTFD_OFFS32;
......
ahci/ahci_top.v
View file @ 1ccc21c0
......@@ -202,16 +202,25 @@ module ahci_top#(
wire [ADDRESS_BITS-1:0] regs_raddr;
wire [31:0] regs_din_from_freceive;
wire [31:0] regs_dout;
reg en_port;
wire [1:0] regs_re = en_port ? regs_re_ftransmit : 2'b0; // [0] - re, [1] - regen
wire regs_we = en_port ? ( regs_we_freceive | regs_we_acs) : 1'b0;
wire [ADDRESS_BITS-1:0] regs_addr = ({ADDRESS_BITS{regs_we_freceive}} & regs_waddr) |
({ADDRESS_BITS{regs_re_ftransmit[0]}} & regs_raddr) |
// ({ADDRESS_BITS{regs_re_fsm[0] | regs_we_acs}} & regs_saddr);
({ADDRESS_BITS{regs_we_acs}} & regs_saddr);
/*
wire [ADDRESS_BITS-1:0] regs_addr = ({ADDRESS_BITS{en_port & regs_we_freceive}} & regs_waddr) |
({ADDRESS_BITS{en_port & regs_re_ftransmit[0]}} & regs_raddr) |
({ADDRESS_BITS{en_port & regs_we_acs}} & regs_saddr);
*/
wire [31:0] regs_din = ({32{regs_we_freceive}} & regs_din_from_freceive) |
({32{regs_we_acs}} & regs_din_from_acs);
// wire [1:0] regs_re = regs_re_ftransmit | regs_re_fsm; // [0] - re, [1] - regen
wire [1:0] regs_re = regs_re_ftransmit; // [0] - re, [1] - regen
wire regs_we = regs_we_freceive | regs_we_acs;
//---------------------
......@@ -422,7 +431,25 @@ module ahci_top#(
wire pxci0_clear; // PxCI clear
wire pxci0; // pxCI current value
// Async FF
always @ (posedge mrst or posedge mclk) begin
if (mrst) en_port <= 0;
else en_port <= 1;
end
/*
reg [1:0] port_en; //disable port signals until initialized from the hardware (currently - PLL)
wire ports_rst = ~port_en[1];
always @ (posedge mclk) begin
if (port_arst_any) port_en[0] <= 0;
else if (mrst) port_en[0] <= 1;
if (port_arst_any) port_en[1] <= 0;
else if (!mrst && port_en[0]) port_en[1] <= 1;
end
*/
ahci_fsm// #(
......
ahci/axi_ahci_regs.v
View file @ 1ccc21c0
......@@ -187,13 +187,8 @@ module axi_ahci_regs#(
reg [2:0] arst_r = ~0; // previous state of arst
reg wait_first_access = RESET_TO_FIRST_ACCESS; // keep port reset until first access
wire any_access = bram_wen_r || bram_ren[0];
// reg bram_ren0_r;
// wire [1:0] bram_ren_w = {bram_ren0_r, bram_ren[0] & ~write_busy_w}; // FIXED: axibram_read does not mask bram_ren and bram_regen with dev_ready !
// assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen ? bram_waddr : pre_awaddr);
assign bram_addr = bram_ren[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);
// assign bram_addr = bram_ren_w[0] ? bram_raddr : (bram_wen_r ? bram_waddr_r : bram_waddr);
assign hba_arst = hba_rst_r; // hba _reset (currently does ~ the same as port reset)
assign port_arst = port_rst_r; // port _reset by software
......@@ -212,7 +207,7 @@ module axi_ahci_regs#(
if (bram_wen) bram_wdata_r <= bram_wdata;
/// if (bram_ren_w[1]) bram_rdata_r <= bram_rdata;
if (bram_ren[1]) bram_rdata_r <= bram_rdata;
if (bram_ren[1]) bram_rdata_r <= bram_rdata;
bram_wstb_r <= {4{bram_wen}} & bram_wstb;
......
host/sata_phy.v
View file @ 1ccc21c0
......@@ -214,14 +214,49 @@ end
wire usrpll_locked;
// make tx/rxreset synchronous to gtrefclk - gather singals from different domains: async, aclk, usrclk2, gtrefclk
localparam [7:0] RST_TIMER_LIMIT = 8'b1000;
reg rxreset_f;
reg txreset_f;
reg rxreset_f_r;
reg txreset_f_r;
reg rxreset_f_rr;
reg txreset_f_rr;
always @ (posedge gtrefclk)
begin
//reg pre_sata_reset_done;
reg sata_areset;
reg [2:0] sata_reset_done_r;
reg [7:0] rst_timer;
//reg rst_r = 1;
assign rst = !sata_reset_done_r;
assign sata_reset_done = sata_reset_done_r[1];
// generate internal reset after a clock is established
// !!!ATTENTION!!!
// async rst block
//localparam [7:0] RST_TIMER_LIMIT = 8'b1000;
/*
always @ (posedge clk or posedge extrst)
// rst_timer <= extrst | ~cplllock | ~usrpll_locked ? 8'h0 : sata_reset_done ? rst_timer : rst_timer + 1'b1;
if (extrst) rst_timer <= 0;
else if (~cplllock | ~usrpll_locked) rst_timer <= 0;
else if (!sata_reset_done) rst_timer <= rst_timer + 1;
// else rst_timer <= ~cplllock | ~usrpll_locked ? 8'h0 : sata_reset_done ? rst_timer : rst_timer + 1'b1;
always @ (posedge clk or posedge extrst)
if (extrst) rst_r <= 1;
else if (~|rst_timer) rst_r <= 0;
else rst_r <= !sata_reset_done;
// else rst_r <= ~|rst_timer ? 1'b0 : sata_reset_done ? 1'b0 : 1'b1;
///assign sata_reset_done = rst_timer == RST_TIMER_LIMIT;
*/
always @ (posedge clk or sata_areset) begin
if (sata_areset) sata_reset_done_r <= 0;
else sata_reset_done_r <= {sata_reset_done_r[1:0], 1'b1};
end
always @ (posedge gtrefclk) begin
// rxreset_f <= ~cplllock | cpllreset | rxreset_oob & gtx_configured;
// txreset_f <= ~cplllock | cpllreset;
......@@ -232,8 +267,13 @@ begin
rxreset_f_r <= rxreset_f;
txreset_f_rr <= txreset_f_r;
rxreset_f_rr <= rxreset_f_r;
if (!(cplllock && usrpll_locked)) rst_timer <= RST_TIMER_LIMIT;
else if (|rst_timer) rst_timer <= rst_timer - 1;
sata_areset <= !(cplllock && usrpll_locked && !(|rst_timer));
end
assign rxreset = rxreset_f_rr;
assign txreset = txreset_f_rr;
assign cpllreset = extrst;
......@@ -249,6 +289,10 @@ always @ (posedge clk or posedge extrst)
else gtx_configured <= gtx_ready | gtx_configured;
// issue partial tx reset to restore functionality after oob sequence. Let it lasts 8 clock lycles
reg [3:0] txpcsreset_cnt;
wire txpcsreset_stop;
......@@ -275,26 +319,6 @@ always @ (posedge clk or posedge extrst)
if (extrst) rxreset_oob_cnt <= 1;
else rxreset_oob_cnt <= rst | ~rxreset_req ? 4'h0 : rxreset_oob_stop ? rxreset_oob_cnt : rxreset_oob_cnt + 1'b1;
// generate internal reset after a clock is established
// !!!ATTENTION!!!
// async rst block
reg [7:0] rst_timer;
reg rst_r;
localparam [7:0] RST_TIMER_LIMIT = 8'b1000;
always @ (posedge clk or posedge extrst)
// rst_timer <= extrst | ~cplllock | ~usrpll_locked ? 8'h0 : sata_reset_done ? rst_timer : rst_timer + 1'b1;
if (extrst) rst_timer <= 1;
else rst_timer <= ~cplllock | ~usrpll_locked ? 8'h0 : sata_reset_done ? rst_timer : rst_timer + 1'b1;
assign rst = rst_r;
always @ (posedge clk or posedge extrst)
if (extrst) rst_r <= 1;
else if (~|rst_timer) rst_r <= 0;
else rst_r <= !sata_reset_done;
// else rst_r <= ~|rst_timer ? 1'b0 : sata_reset_done ? 1'b0 : 1'b1;
assign sata_reset_done = rst_timer == RST_TIMER_LIMIT;
/*
* USRCLKs generation. USRCLK @ 150MHz, same as TXOUTCLK; USRCLK2 @ 75Mhz -> sata_clk === sclk
......
tb/tb_ahci.tf
View file @ 1ccc21c0
......@@ -653,7 +653,7 @@ localparam MAXIGP1 = 32'h80000000; // Start of the MAXIGP1 address range (use ah
end
endtask
//localparam CLB_OFFS32 = 'h200; // # In the second half of the register space (0x800..0xbff - 1KB)
localparam CLB_OFFS32 = 'h200; // # In the second half of the register space (0x800..0xbff - 1KB)
localparam HBA_OFFS32 = 0;
localparam HBA_PORT0_OFFS32 = 'h40;
localparam PXSIG_OFFS32 = HBA_OFFS32 + HBA_PORT0_OFFS32 + 'h9;
......@@ -670,12 +670,18 @@ initial begin //Host
axi_set_rd_lag(0);
axi_set_b_lag(0);
maxigp1_writep (PXSIG_OFFS32 << 2, 'h12345678); //
maxigp1_writep (PXTFD_OFFS32 << 2, 'h87654321); //
maxigp1_writep (PXSIG_OFFS32 << 2, 'h12345678); //
maxigp1_writep (PXTFD_OFFS32 << 2, 'h87654321); //
maxigp1_writep (CLB_OFFS32 << 2, 'h12345678); //
maxigp1_writep ((CLB_OFFS32+1) << 2, 'h87654321); //
maxigp1_print (PXSIG_OFFS32 << 2); // OK to read wrong - it is RO with default 'hffffffff
maxigp1_print (PXTFD_OFFS32 << 2); // OK to read wrong - it is RO with default 0
maxigp1_print (CLB_OFFS32 << 2); //
maxigp1_print ((CLB_OFFS32+1) << 2); //
maxigp1_print (PXSIG_OFFS32 << 2);
maxigp1_print (PXTFD_OFFS32 << 2);
maxigp1_print (PCI_Header__CAP__CAP__ADDR << 2);
......
tb_ahci_01.sav
View file @ 1ccc21c0
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sun Jan 24 22:37:59 2016
[*] Mon Jan 25 02:04:39 2016
[*]
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160124150955061.fst"
[dumpfile_mtime] "Sun Jan 24 22:10:48 2016"
[dumpfile_size] 6331897
[dumpfile] "/home/andrey/git/x393_sata/simulation/tb_ahci-20160124173705418.fst"
[dumpfile_mtime] "Mon Jan 25 00:37:59 2016"
[dumpfile_size] 6252216
[savefile] "/home/andrey/git/x393_sata/tb_ahci_01.sav"
[timestart] 15550100
[timestart] 213500
[size] 1823 1173
[pos] 1951 0
*-16.936193 15738800 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-15.936193 418000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb_ahci.
[treeopen] tb_ahci.dev.
[treeopen] tb_ahci.dev.phy.
......@@ -17,8 +17,6 @@
[treeopen] tb_ahci.dut.axi_hp_clk_i.
[treeopen] tb_ahci.dut.sata_top.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.link.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.
[treeopen] tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.
......@@ -28,6 +26,7 @@
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_read_i.
[treeopen] tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_write_i.
[sst_width] 275
[signals_width] 254
[sst_expanded] 1
......@@ -66,7 +65,13 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_rdata_r[31:0]
@200
-
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.high_sel
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_write_i.dev_ready
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_write_i.dev_ready_r
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.axibram_write_i.start_write_burst_w
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.pre_bram_wen
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.write_start_burst
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.write_busy_r
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wen
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wen_r
@22
......@@ -76,6 +81,9 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wstb[3:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_addr[9:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wdata[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wdata_r[31:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_di[31:0]
@23
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.wmask[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.en_a
@c00022
......@@ -87,16 +95,19 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.we_a4[3:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.we_a4[3:0]
@1401200
-group_end
@800022
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wstb_r[3:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.en_b
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.we_b4[3:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.data_in32_a[31:0]
@c00022
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wstb_r[3:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wstb_r[3:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wstb_r[3:0]
(2)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wstb_r[3:0]
(3)tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.bram_wstb_r[3:0]
@1001200
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.write_busy_w
......@@ -124,7 +135,6 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_addr[9:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_we
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_addr[9:0]
@23
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_din[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_re[1:0]
......@@ -170,8 +180,74 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_dout[31:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.high_sel
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.write_start_burst
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_arst
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.hba_addr[9:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.port_arst_any_r
@c00200
-up
@28
tb_ahci.dut.sata_top.ahci_top_i.regs_we_freceive
@c00028
tb_ahci.dut.sata_top.ahci_top_i.regs_re_ftransmit[1:0]
@28
(0)tb_ahci.dut.sata_top.ahci_top_i.regs_re_ftransmit[1:0]
(1)tb_ahci.dut.sata_top.ahci_top_i.regs_re_ftransmit[1:0]
@1401200
-group_end
@28
tb_ahci.dut.sata_top.ahci_top_i.hba_arst
tb_ahci.dut.sata_top.ahci_top_i.mrst
tb_ahci.dut.sata_top.ahci_top_i.port_arst_any
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.hba_rst
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.hba_rst
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.reg_re[1:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_transmit_i.reg_re_r[2:0]
tb_ahci.dut.sata_top.ahci_top_i.en_port
tb_ahci.dut.sata_top.ahci_top_i.regs_we
tb_ahci.dut.sata_top.ahci_top_i.regs_we_acs
@800200
-phy
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.extrst
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rst
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rst_timer[7:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.sata_areset
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.sata_reset_done
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.cplllock
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.usrpll_locked
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.clk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtrefclk
@1000200
-phy
@200
-
@1401200
-up
@800200
-ahci_regs_i
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.addr_a[9:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.en_a
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.we_a[3:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.we_a4[3:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.data_in32_a[31:0]
@200
-
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.addr_b[9:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.en_b
@22
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.we_b[3:0]
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.ahci_regs_i.we_b4[3:0]
@1000200
-ahci_regs_i
@c00200
-axibram_read
@22
......@@ -238,7 +314,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.fifo_d2h_control_i.mem_regen
-fifo_d2h_control
@1401200
-ahci_sata_layers
@800200
@c00200
-ahci_top
@22
tb_ahci.dut.sata_top.ahci_top_i.regs_waddr[9:0]
......@@ -351,8 +427,9 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tf_err_sts[15:0]
tb_ahci.dut.sata_top.ahci_top_i.ahci_fis_receive_i.tfd_err[7:0]
@1000200
-ahci_fis_receive
@1401200
-ahci_top
@800200
@c00200
-ahci_ctrl_stat
@22
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.regs_addr[9:0]
......@@ -648,7 +725,6 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen2
tb_ahci.dut.sata_top.ahci_top_i.ahci_ctrl_stat_i.ssts_spd_gen3
@1401200
-ssts
@1000200
-ahci_ctrl_stat
@c00200
-axi_ahci_regs
......@@ -663,7 +739,7 @@ tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.any_access
tb_ahci.dut.sata_top.ahci_top_i.axi_ahci_regs_i.set_port_rst
@1401200
-axi_ahci_regs
@800200
@c00200
-ahci_fsm
@c00022
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.pgm_addr[9:0]
......@@ -752,7 +828,7 @@ tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_pend_r[1:0]
@28
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_ackn
tb_ahci.dut.sata_top.ahci_top_i.ahci_fsm_i.async_from_st
@1000200
@1401200
-ahci_fsm
@c00200
-link
......@@ -797,7 +873,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.link.state_wait
-states
@1401200
-link
@800200
@c00200
-phy
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.comreset_send
......@@ -822,7 +898,6 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxeyereset_cnt[6:0]
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rxeyereset_done
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.clk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.rst_r
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.sata_reset_done
@200
-
......@@ -846,9 +921,9 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.ll_charisk_out[3:0]
-
@22
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.txdata[31:0]
@1000200
@1401200
-phy
@800200
@c00200
-oob_ctrl
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.gtx_ready
......@@ -860,8 +935,9 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.oob_ctrl.gtx_ready
-
@1000200
-oob
@1401200
-oob_ctrl
@800200
@c00200
-gtx
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.cpllreset
......@@ -869,7 +945,7 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.cplllock
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.cplllockdetclk
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txelecidle
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txelecidle_gtx
@800200
@c00200
-gtx8x10enc
@28
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.wrap_txreset_
......@@ -882,10 +958,10 @@ tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txcharisk_enc_in[1:0]
tb_ahci.dut.sata_top.ahci_sata_layers_i.phy.gtx_wrap.txdata_enc_out[19:0]
@200
-
@1000200
@1401200
-gtx8x10enc
-gtx
@800200
@c00200
-device
@28
tb_ahci.dev.phy_ready
......@@ -904,6 +980,7 @@ tb_ahci.dev.phy.ll_charisk_in[3:0]
-
@1000200
-dev_phy
@1401200
-device
[pattern_trace] 1
[pattern_trace] 0
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