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Commit 0f01238e authored by Andrey Filippov's avatar Andrey Filippov
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Finished top modules of AHCI, started connecting them with existing link and phy layers

parent f4dc8593
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ahci/ahci_ctrl_stat.v
View file @ 0f01238e
...@@ -54,10 +54,9 @@ module ahci_ctrl_stat #( ...@@ -54,10 +54,9 @@ module ahci_ctrl_stat #(
input update_pcmd, input update_pcmd,
input update_pci, input update_pci,
// Next - obsolete? /// output reg st01_pending, // software turned PxCMD.ST from 0 to 1
output reg st01_pending, // software turned PxCMD.ST from 0 to 1 /// output reg st10_pending, // software turned PxCMD.ST from 1 to 0
output reg st10_pending, // software turned PxCMD.ST from 1 to 0 /// input st_pending_reset,// reset both st01_pending and st10_pending
input st_pending_reset,// reset both st01_pending and st10_pending
// PxCMD // PxCMD
input pcmd_clear_icc, // clear PxCMD.ICC field input pcmd_clear_icc, // clear PxCMD.ICC field
...@@ -505,7 +504,7 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000; ...@@ -505,7 +504,7 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000;
else updating[5:1] <= updating[5:1] & ~ update_next[5:1]; else updating[5:1] <= updating[5:1] & ~ update_next[5:1];
// detect software setting for PxCMD.ST 0->1 and 1->0 // detect software setting for PxCMD.ST 0->1 and 1->0
/*
if (mrst) st01_pending <= 0; if (mrst) st01_pending <= 0;
else if (swr_HBA_PORT__PxCMD && (HBA_PORT__PxCMD__ST__MASK & soft_write_data & ~PxCMD_r)) st01_pending <= 1; else if (swr_HBA_PORT__PxCMD && (HBA_PORT__PxCMD__ST__MASK & soft_write_data & ~PxCMD_r)) st01_pending <= 1;
if (st_pending_reset) st01_pending <= 0; if (st_pending_reset) st01_pending <= 0;
...@@ -513,7 +512,7 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000; ...@@ -513,7 +512,7 @@ localparam PxCMD_MASK = HBA_PORT__PxCMD__ICC__MASK | // 'hf0000000;
if (mrst) st10_pending <= 0; if (mrst) st10_pending <= 0;
else if (swr_HBA_PORT__PxCMD && (HBA_PORT__PxCMD__ST__MASK & ~soft_write_data & PxCMD_r)) st10_pending <= 1; else if (swr_HBA_PORT__PxCMD && (HBA_PORT__PxCMD__ST__MASK & ~soft_write_data & PxCMD_r)) st10_pending <= 1;
if (st_pending_reset) st10_pending <= 0; if (st_pending_reset) st10_pending <= 0;
*/
end end
endmodule endmodule
......
ahci/ahci_fsm.v
View file @ 0f01238e
...@@ -42,7 +42,7 @@ module ahci_fsm ...@@ -42,7 +42,7 @@ module ahci_fsm
// direct communication with transposrt, link and phy layers // direct communication with transposrt, link and phy layers
input phy_ready, // goes up after comreset,cominit, align, ... input [1:0] phy_ready, // goes up after comreset,cominit, align, ..., showing speed
output syncesc_send, // Send sync escape output syncesc_send, // Send sync escape
input syncesc_send_done, // "SYNC escape until the interface is quiescent..." input syncesc_send_done, // "SYNC escape until the interface is quiescent..."
output comreset_send, // Not possible yet? output comreset_send, // Not possible yet?
...@@ -59,29 +59,31 @@ module ahci_fsm ...@@ -59,29 +59,31 @@ module ahci_fsm
output pfsm_started, // H: FSM doene, P: FSM started (enable sensing pcmd_st_cleared) output pfsm_started, // H: FSM doene, P: FSM started (enable sensing pcmd_st_cleared)
// update register inputs (will write to register memory current value of the corresponding register) // update register inputs (will write to register memory current value of the corresponding register)
// Removing - such updates are always done when startimng new state // Removing - such updates are always done when startimng new state
input update_pending, /// input update_pending,
output update_all, output update_all, // =fsm_jump[0]
input update_busy, // valid same cycle as update_all input update_busy, // valid same cycle as update_all
output update_gis, // these following individual may be unneeded - just use universal update_all // output update_gis, // these following individual may be unneeded - just use universal update_all
output update_pis, // output update_pis,
output update_ssts, // output update_ssts,
output update_serr, // output update_serr,
output update_pcmd, // output update_pcmd,
output update_pci, // output update_pci,
input st01_pending, // software turned PxCMD.ST from 0 to 1 /// input st01_pending, // software turned PxCMD.ST from 0 to 1 - detected in the loop
input st10_pending, // software turned PxCMD.ST from 1 to 0 /// input st10_pending, // software turned PxCMD.ST from 1 to 0 - generates port reset
output st_pending_reset,// reset both st01_pending and st10_pending /// output st_pending_reset,// reset both st01_pending and st10_pending
// PxCMD // PxCMD
output pcmd_clear_icc, // clear PxCMD.ICC field /// output pcmd_clear_icc, // clear PxCMD.ICC field
output pcmd_esp, // external SATA port (just forward value) /// output pcmd_esp, // external SATA port (just forward value)
input pcmd_cr, // command list run - current /// input pcmd_cr, // command list run - current
output pcmd_cr_set, // command list run set output pcmd_cr_set, // command list run set
output pcmd_cr_reset, // command list run reset output pcmd_cr_reset, // command list run reset
output pcmd_fr, // ahci_fis_receive:get_fis_busy // output pcmd_fr, // ahci_fis_receive:get_fis_busy
output pcmd_clear_bsy_drq, // == ahci_fis_receive:clear_bsy_drq /// output pcmd_clear_bsy_drq, // == ahci_fis_receive:clear_bsy_drq
// Command List override, not yet implemented (optional), keeping @SuppressWarnings VEditor
input pcmd_clo, //RW1, causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit input pcmd_clo, //RW1, causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit
output pcmd_clear_st, // RW clear ST (start) bit /// output pcmd_clear_st, // RW clear ST (start) bit Seems it is software controlled only
input pcmd_st, // current value input pcmd_st, // current value
input pcmd_st_cleared,// ST bit cleared by software; input pcmd_st_cleared,// ST bit cleared by software;
...@@ -102,20 +104,7 @@ module ahci_fsm ...@@ -102,20 +104,7 @@ module ahci_fsm
// SCR1:SError (only inputs that are not available in sirq_* ones // SCR1:SError (only inputs that are not available in sirq_* ones
//sirq_PC, //sirq_PC,
//sirq_UF //sirq_UF
output serr_DT, // RWC: Transport state transition error // 5.3.2.3 P:NotRunning.8 - can not be implemented now, keeping @SuppressWarnings VEditor
output serr_DS, // RWC: Link sequence error
output serr_DH, // RWC: Handshake Error (i.e. Device got CRC error)
output serr_DC, // RWC: CRC error in Link layer
output serr_DB, // RWC: 10B to 8B decode error
output serr_DW, // RWC: COMMWAKE signal was detected
output serr_DI, // RWC: PHY Internal Error
// sirq_PRC,
// sirq_IF || // sirq_INF
output serr_EP, // RWC: Protocol Error - a violation of SATA protocol detected
output serr_EC, // RWC: Persistent Communication or Data Integrity Error
output serr_ET, // RWC: Transient Data Integrity Error (error not recovered by the interface)
output serr_EM, // RWC: Communication between the device and host was lost but re-established
output serr_EI, // RWC: Recovered Data integrity Error
input serr_diag_X, // value of PxSERR.DIAG.X input serr_diag_X, // value of PxSERR.DIAG.X
...@@ -273,7 +262,7 @@ module ahci_fsm ...@@ -273,7 +262,7 @@ module ahci_fsm
// wire [7:0] precond_w = pgm_data[17:10]; // select what to use - cond_met_w valis after precond_w, same time as conditions // wire [7:0] precond_w = pgm_data[17:10]; // select what to use - cond_met_w valis after precond_w, same time as conditions
// reg [7:0] conditions; // reg [7:0] conditions;
wire pre_jump_w = (|async_pend_r) ? async_ackn : (cond_met_w & fsm_transitions[1]); wire pre_jump_w = (|async_pend_r) ? async_ackn : (cond_met_w & fsm_transitions[1]);
wire fsm_act_done = get_fis_done || xmit_done; wire fsm_act_done = get_fis_done || xmit_done || (syncesc_send_pend && syncesc_send_done);
wire fsm_wait_act_w = pgm_data[16]; // this action requires waiting for done wire fsm_wait_act_w = pgm_data[16]; // this action requires waiting for done
wire fsm_last_act_w = pgm_data[17]; wire fsm_last_act_w = pgm_data[17];
...@@ -284,9 +273,33 @@ module ahci_fsm ...@@ -284,9 +273,33 @@ module ahci_fsm
wire asynq_rq = cominit_got || pcmd_st_cleared; wire asynq_rq = cominit_got || pcmd_st_cleared;
wire async_ackn = !fsm_preload && async_pend_r[0] && ((fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]); // OK to process async jump wire async_ackn = !fsm_preload && async_pend_r[0] && ((fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]); // OK to process async jump
reg x_rdy_collision_pend; reg x_rdy_collision_pend;
reg syncesc_send_pend; // waiting for 'syncesc_send' confiramtion 'syncesc_send_done'
reg [1:0] phy_ready_prev; // previous state of phy_ready / speed
reg phy_ready_chng_r; // pulse when phy_ready changes
wire phy_ready_chng_w = !hba_rst && !was_rst && (phy_ready != phy_ready_prev);
assign fsm_next = (fsm_preload || (fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]) && !async_pend_r[0]; // quiet if received cominit is pending assign fsm_next = (fsm_preload || (fsm_actions && !update_busy && !fsm_act_busy) || fsm_transitions[0]) && !async_pend_r[0]; // quiet if received cominit is pending
assign update_all = fsm_jump[0];
assign ssts_ipm_dnp = phy_ready_chng_r && (phy_ready_prev == 0); // device not present or communication not established
assign ssts_ipm_active = phy_ready_chng_r && (phy_ready_prev != 0); // device in active state
assign ssts_ipm_part = 0; // device in partial state
assign ssts_ipm_slumb = 0; // device in slumber state
assign ssts_ipm_devsleep = 0; // device in DevSleep state
assign ssts_spd_dnp = phy_ready_chng_r && (phy_ready_prev == 0); // device not present or communication not established
assign ssts_spd_gen1 = phy_ready_chng_r && (phy_ready_prev == 1); // Gen 1 rate negotiated
assign ssts_spd_gen2 = phy_ready_chng_r && (phy_ready_prev == 2); // Gen 2 rate negotiated
assign ssts_spd_gen3 = phy_ready_chng_r && (phy_ready_prev == 3); // Gen 3 rate negotiated
assign ssts_det_ndnp = phy_ready_chng_r && (phy_ready_prev == 0); // no device detected, phy communication not established
assign ssts_det_dnp = 0; // device detected, but phy communication not established
assign ssts_det_dp = phy_ready_chng_r && (phy_ready_prev != 0); // device detected, phy communication established
assign sirq_OF = 0; // RWC: Overflow Status (buffer overrun - should not happen, add?)
assign sirq_PRC = phy_ready_chng_r; // RO: PhyRdy changed Status
// Writing to the FSM program memory // Writing to the FSM program memory
always @ (posedge aclk) begin always @ (posedge aclk) begin
...@@ -343,6 +356,13 @@ module ahci_fsm ...@@ -343,6 +356,13 @@ module ahci_fsm
if (hba_rst || pcmd_cr_set) x_rdy_collision_pend <= 0; if (hba_rst || pcmd_cr_set) x_rdy_collision_pend <= 0;
else if (x_rdy_collision) x_rdy_collision_pend <= 1; else if (x_rdy_collision) x_rdy_collision_pend <= 1;
if (hba_rst || syncesc_send_done) syncesc_send_pend <= 0;
else if (syncesc_send) syncesc_send_pend <= 1;
if (was_rst && !hba_rst && !was_hba_rst && !was_port_rst) phy_ready_prev <= 0;
else if (phy_ready_chng_w) phy_ready_prev <= phy_ready;
phy_ready_chng_r <= phy_ready_chng_w;
end end
...@@ -374,6 +394,7 @@ module ahci_fsm ...@@ -374,6 +394,7 @@ module ahci_fsm
.SIRQ_DP (sirq_DP), // output reg .SIRQ_DP (sirq_DP), // output reg
.SIRQ_DS (sirq_DS), // output reg .SIRQ_DS (sirq_DS), // output reg
.SIRQ_IF (sirq_IF), // output reg .SIRQ_IF (sirq_IF), // output reg
.SIRQ_INF (sirq_INF), // output reg
.SIRQ_PS (sirq_PS), // output reg .SIRQ_PS (sirq_PS), // output reg
.SIRQ_SDB (sirq_SDB), // output reg .SIRQ_SDB (sirq_SDB), // output reg
.SIRQ_TFE (sirq_TFE), // output reg .SIRQ_TFE (sirq_TFE), // output reg
......
ahci/ahci_sata_layers.v 0 → 100644
View file @ 0f01238e
/*******************************************************************************
* Module: ahci_sata_layers
* Date:2016-01-19
* Author: andrey
* Description: Link and PHY SATA layers
*
* Copyright (c) 2016 Elphel, Inc .
* ahci_sata_layers.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ahci_sata_layers.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module ahci_sata_layers(
input exrst, // master reset that resets PLL and GTX
output rst, // PHY-generated reset after PLL lock
output clk, // PHY-generated clock, 75MHz for SATA2
// Data/type FIFO, host -> device
// Data System memory or FIS -> device
input [31:0] h2d_data, // 32-bit data from the system memory to HBA (dma data)
input [ 1:0] h2d_type, // 0 - data, 1 - FIS head, 2 - FIS LAST
input h2d_valid, // input register full
output h2d_ready, // send FIFO has room for data (>= 8? dwords)
// Data/type FIFO, device -> host
output [31:0] d2h_data, // FIFO input data
output [ 1:0] d2h_type, // 0 - data, 1 - FIS head, 2 - R_OK, 3 - R_ERR (last two - after data, so ignore data with R_OK/R_ERR)
output d2h_valid, // Data available from the transport layer in FIFO
output d2h_many, // Multiple DWORDs available from the transport layer in FIFO
input d2h_ready, // This module or DMA consumes DWORD
// communication with link/phys layers
output [ 1:0] phy_ready, // 0 - not ready, 1..3 - negotiated speed
output syncesc_recv, // These two **puts interrupt transmit
output xmit_err, // Error during sending of a FIS
input syncesc_send, // Send sync escape
output syncesc_send_done, // "SYNC escape until the interface is quiescent..."
input comreset_send, // Not possible yet?
output cominit_got,
input set_offline, // electrically idle
output x_rdy_collision, // X_RDY/X_RDY collision on interface
input send_R_OK, // Should it be originated in this layer SM?
input send_R_ERR,
// additional errors from SATA layers (single-clock pulses):
output serr_DT, // RWC: Transport state transition error
output serr_DS, // RWC: Link sequence error
output serr_DH, // RWC: Handshake Error (i.e. Device got CRC error)
output serr_DC, // RWC: CRC error in Link layer
output serr_DB, // RWC: 10B to 8B decode error
output serr_DW, // RWC: COMMWAKE signal was detected
output serr_DI, // RWC: PHY Internal Error
// sirq_PRC,
// sirq_IF || // sirq_INF
output serr_EP, // RWC: Protocol Error - a violation of SATA protocol detected
output serr_EC, // RWC: Persistent Communication or Data Integrity Error
output serr_ET, // RWC: Transient Data Integrity Error (error not recovered by the interface)
output serr_EM, // RWC: Communication between the device and host was lost but re-established
output serr_EI, // RWC: Recovered Data integrity Error
// additional control signals for SATA layers
input [3:0] sctl_ipm, // Interface power management transitions allowed
input [3:0] sctl_spd // Interface maximal speed
);
link #(
.DATA_BYTE_WIDTH(4)
) link_i (
.rst (), // input wire
.clk (), // input wire
// data inputs from transport layer
.data_in (), // input[31:0] wire // input data stream (if any data during OOB setting => ignored)
// in case of strange data aligments and size (1st mentioned @ doc, p.310, odd number of words case)
// Actually, only last data bundle shall be masked, others are always valid.
// Mask could be encoded into 3 bits instead of 4 for qword, but encoding+decoding aren't worth the bit
// TODO, for now not supported, all mask bits are assumed to be set
.data_mask_in (), // input[1:0] wire
.data_strobe_out (), // output wire // buffer read strobe
.data_last_in (), // input wire // transaction's last data budle pulse
.data_val_in (), // input wire // read data is valid (if 0 while last pulse wasn't received => need to hold the line)
.data_out (), // output[31:0] wire // read data, same as related inputs
.data_mask_out (), // output[1:0] wire // same thing - all 1s for now. TODO
.data_val_out (), // output wire // count every data bundle read by transport layer, even if busy flag is set // let the transport layer handle oveflows by himself
.data_busy_in (), // input wire // transport layer tells if its inner buffer is almost full
.data_last_out (), // output wire
.frame_req (), // input wire // request for a new frame transition
.frame_busy (), // output wire // a little bit of overkill with the cound of response signals, think of throwing out 1 of them // LL tells back if it cant handle the request for now
.frame_ack (), // output wire // LL tells if the request is transmitting
.frame_rej (), // output wire // or if it was cancelled because of simultanious incoming transmission
.frame_done_good (), // output wire // TL tell if the outcoming transaction is done and how it was done
.frame_done_bad (), // output wire
.incom_start (), // output wire // if started an incoming transaction
.incom_done (), // output wire // if incoming transition was completed
.incom_invalidate (), // output wire // if incoming transition had errors
.incom_ack_good (), // input wire // transport layer responds on a completion of a FIS
.incom_ack_bad (), // input wire // oob sequence is reinitiated and link now is not established or rxelecidle
.link_reset (), // input wire // oob sequence is reinitiated and link now is not established or rxelecidle
.sync_escape_req (), // input wire // TL demands to brutally cancel current transaction
.sync_escape_ack (), // output wire // acknowlegement of a successful reception?
.incom_stop_req (), // input wire // TL demands to stop current recieving session
// inputs from phy
.phy_ready (), // input wire // phy is ready - link is established
// data-primitives stream from phy
.phy_data_in (), // input[31:0] wire // phy_data_in
.phy_isk_in (), // input[3:0] wire // charisk
.phy_err_in (), // input[3:0] wire // disperr | notintable
// to phy
.phy_data_out (), // output[31:0] wire
.phy_isk_out () // output[3:0] wire // charisk
);
reg [8:0] h2d_raddr;
reg [8:0] h2d_waddr;
reg [8:0] d2h_raddr;
reg [8:0] d2h_waddr;
wire [1:0] dummy1;
sata_phy #(
.DATA_BYTE_WIDTH(4)
) sata_phy_i (
.extrst (), // input wire
.clk (), // output wire
.rst (), // output wire
.reliable_clk (), // input wire
.phy_ready (), // output wire
.gtx_ready (), // output wire
.debug_cnt (), // output[11:0] wire
.extclk_p (), // input wire
.extclk_n (), // input wire
.txp_out (), // output wire
.txn_out (), // output wire
.rxp_in (), // input wire
.rxn_in (), // input wire
.ll_data_out (), // output[31:0] wire
.ll_charisk_out (), // output[3:0] wire
.ll_err_out (), // output[3:0] wire
.ll_data_in (), // input[31:0] wire
.ll_charisk_in () // input[3:0] wire
);
ram18p_var_w_var_r #(
.REGISTERS (1),
.LOG2WIDTH_WR (5),
.LOG2WIDTH_RD (5)
) fifo_h2d_i (
.rclk (clk), // input
.raddr (h2d_raddr), // input[8:0]
.ren (), // input
.regen (), // input
.data_out (), // output[35:0]
.wclk (clk), // input
.waddr (h2d_waddr), // input[8:0]
.we (), // input
.web (4'hf), // input[3:0]
.data_in ({2'b0,h2d_type,h2d_data}) // input[35:0]
);
ram18p_var_w_var_r #(
.REGISTERS (1),
.LOG2WIDTH_WR (5),
.LOG2WIDTH_RD (5)
) fifo_d2h_i (
.rclk (clk), // input
.raddr (d2h_raddr), // input[8:0]
.ren (), // input
.regen (), // input
.data_out ({dummy1,d2h_type,d2h_data}), // output[35:0]
.wclk (clk), // input
.waddr (d2h_waddr), // input[8:0]
.we (), // input
.web (4'hf), // input[3:0]
.data_in () // input[35:0]
);
endmodule
ahci/ahci_top.v
View file @ 0f01238e
...@@ -30,7 +30,7 @@ module ahci_top#( ...@@ -30,7 +30,7 @@ module ahci_top#(
input arst, // @aclk sync reset, active high input arst, // @aclk sync reset, active high
input mclk, // SATA system clock (current 75MHz for SATA2) input mclk, // SATA system clock (current 75MHz for SATA2)
input mrst, // reset in mclk clock domain (after SATA PLL is on) input mrst, // reset in mclk clock domain (after SATA PLL is on)
// async reset for SATA (mrst will be responce to it) // async reset for SATA (mrst will be response to it)
output hba_arst, // hba async reset (currently does ~ the same as port reset) output hba_arst, // hba async reset (currently does ~ the same as port reset)
output port_arst, // port0 async reset by software output port_arst, // port0 async reset by software
...@@ -52,7 +52,7 @@ module ahci_top#( ...@@ -52,7 +52,7 @@ module ahci_top#(
input [11:0] wid, // WID[11:0], input input [11:0] wid, // WID[11:0], input
input wlast, // WLAST, input input wlast, // WLAST, input
input [ 3:0] wstb, // WSTRB[3:0], input input [ 3:0] wstb, // WSTRB[3:0], input
// AXI PS Master GP0: Write Responce // AXI PS Master GP0: Write response
output bvalid, // BVALID, output output bvalid, // BVALID, output
input bready, // BREADY, input input bready, // BREADY, input
output [11:0] bid, // BID[11:0], output output [11:0] bid, // BID[11:0], output
...@@ -141,8 +141,8 @@ module ahci_top#( ...@@ -141,8 +141,8 @@ module ahci_top#(
output d2h_ready, // This module or DMA consumes DWORD output d2h_ready, // This module or DMA consumes DWORD
// communication with transport/link/phys layers // communication with transport/link/phys layers
// input phy_rst, // frome phy, as a responce to hba_arst || port_arst. It is deasserted when clock is stable // input phy_rst, // frome phy, as a response to hba_arst || port_arst. It is deasserted when clock is stable
input phy_ready, input [ 1:0] phy_ready, // 0 - not ready, 1..3 - negotiated speed
input syncesc_recv, // These two inputs interrupt transmit input syncesc_recv, // These two inputs interrupt transmit
input xmit_err, // Error during sending of a FIS input xmit_err, // Error during sending of a FIS
output syncesc_send, // Send sync escape output syncesc_send, // Send sync escape
...@@ -154,6 +154,27 @@ module ahci_top#( ...@@ -154,6 +154,27 @@ module ahci_top#(
output send_R_OK, // Should it be originated in this layer SM? output send_R_OK, // Should it be originated in this layer SM?
output send_R_ERR, output send_R_ERR,
// additional errors from SATA layers (single-clock pulses):
input serr_DT, // RWC: Transport state transition error
input serr_DS, // RWC: Link sequence error
input serr_DH, // RWC: Handshake Error (i.e. Device got CRC error)
input serr_DC, // RWC: CRC error in Link layer
input serr_DB, // RWC: 10B to 8B decode error
input serr_DW, // RWC: COMMWAKE signal was detected
input serr_DI, // RWC: PHY Internal Error
// sirq_PRC,
// sirq_IF || // sirq_INF
input serr_EP, // RWC: Protocol Error - a violation of SATA protocol detected
input serr_EC, // RWC: Persistent Communication or Data Integrity Error
input serr_ET, // RWC: Transient Data Integrity Error (error not recovered by the interface)
input serr_EM, // RWC: Communication between the device and host was lost but re-established
input serr_EI, // RWC: Recovered Data integrity Error
// additional control signals for SATA layers
output [3:0] sctl_ipm, // Interface power management transitions allowed
output [3:0] sctl_spd, // Interface maximal speed
output irq // CPU interrupt request output irq // CPU interrupt request
...@@ -214,10 +235,10 @@ module ahci_top#( ...@@ -214,10 +235,10 @@ module ahci_top#(
wire [ 4:0] dma_ct_addr; // input[4:0] wire [ 4:0] dma_ct_addr; // input[4:0]
wire [ 1:0] dma_ct_re; // input wire [ 1:0] dma_ct_re; // input
wire [31:0] dma_ct_data; // output[31:0] reg wire [31:0] dma_ct_data; // output[31:0] reg
wire dma_prd_done; // output (finished next prd) /// wire dma_prd_done; // output (finished next prd)
wire dma_prd_irq_clear; // reset pending prd_irq wire dma_prd_irq_clear; // reset pending prd_irq
wire dma_prd_irq_pend; // prd interrupt pending. This is just a condition for irq - actual will be generated after FIS OK wire dma_prd_irq_pend; // prd interrupt pending. This is just a condition for irq - actual will be generated after FIS OK
wire dma_cmd_busy; // output reg (DMA engine is processing PRDs) /// wire dma_cmd_busy; // output reg (DMA engine is processing PRDs)
wire dma_cmd_done; // output (last PRD is over) wire dma_cmd_done; // output (last PRD is over)
wire [31:0] dma_dout; // output[31:0] wire [31:0] dma_dout; // output[31:0]
wire dma_dav; // output wire dma_dav; // output
...@@ -266,30 +287,30 @@ module ahci_top#( ...@@ -266,30 +287,30 @@ module ahci_top#(
wire frcv_extra; // DMA all transferred, but some data is still in left. . Does not deny frcv_ok wire frcv_extra; // DMA all transferred, but some data is still in left. . Does not deny frcv_ok
wire frcv_set_update_sig; // when set, enables get_sig (and resets itself) wire frcv_set_update_sig; // when set, enables get_sig (and resets itself)
wire frcv_pUpdateSig; // state variable /// wire frcv_pUpdateSig; // state variable
wire frcv_sig_available; // signature data available /// wire frcv_sig_available; // signature data available
wire frcv_update_sig; // update signature wire frcv_update_sig; // update signature
// fsm <- state variables that are maintained inside 'ahc_fis_receive' // fsm <- state variables that are maintained inside 'ahc_fis_receive'
wire [7:0] tfd_sts; // Current PxTFD status field (updated after regFIS and SDB - certain fields) wire [7:0] tfd_sts; // Current PxTFD status field (updated after regFIS and SDB - certain fields)
// tfd_sts[7] - BSY, tfd_sts[4] - DRQ, tfd_sts[0] - ERR // tfd_sts[7] - BSY, tfd_sts[4] - DRQ, tfd_sts[0] - ERR
wire [7:0] tfd_err; // Current PxTFD error field (updated after regFIS and SDB) // wire [7:0] tfd_err; // Current PxTFD error field (updated after regFIS and SDB)
wire fis_i; // value of "I" field in received regsD2H or SDB FIS wire fis_i; // value of "I" field in received regsD2H or SDB FIS
wire sdb_n; // value of "N" field in received SDB FIS /// wire sdb_n; // value of "N" field in received SDB FIS
wire dma_a; // value of "A" field in received DMA Setup FIS wire dma_a; // value of "A" field in received DMA Setup FIS
wire dma_d; // value of "D" field in received DMA Setup FIS /// wire dma_d; // value of "D" field in received DMA Setup FIS
wire pio_i; // value of "I" field in received PIO Setup FIS wire pio_i; // value of "I" field in received PIO Setup FIS
wire pio_d; // value of "D" field in received PIO Setup FIS wire pio_d; // value of "D" field in received PIO Setup FIS
wire [7:0] pio_es; // value of PIO E_Status /// wire [7:0] pio_es; // value of PIO E_Status
wire pPioXfer; wire pPioXfer;
wire sactive0; // bit 0 of sActive DWORD received in SDB FIS /// wire sactive0; // bit 0 of sActive DWORD received in SDB FIS
// Using even word count (will be rounded up), partial DWORD (last) will be handled by PRD length if needed // Using even word count (will be rounded up), partial DWORD (last) will be handled by PRD length if needed
wire [31:0] xfer_cntr; wire [31:0] xfer_cntr;
wire xfer_cntr_zero; wire xfer_cntr_zero;
wire [11:0] data_in_dwords; // number of DWORDs received in data FIS (can be updated internally). Is it needed? /// wire [11:0] data_in_dwords; // number of DWORDs received in data FIS (can be updated internally). Is it needed?
// fsm <-> ahc_fis_transmit // fsm <-> ahc_fis_transmit
// Command pulses to execute states fsm -> ahc_fis_transmit // Command pulses to execute states fsm -> ahc_fis_transmit
...@@ -301,7 +322,7 @@ module ahci_top#( ...@@ -301,7 +322,7 @@ module ahci_top#(
wire fsnd_atapi_xmit; // tarsmit ATAPI command FIS wire fsnd_atapi_xmit; // tarsmit ATAPI command FIS
// responses fsm <- ahc_fis_transmit // responses fsm <- ahc_fis_transmit
wire fsnd_done; wire fsnd_done;
wire fsnd_busy; /// wire fsnd_busy;
// Short action pulses fsm -> ahc_fis_transmit // Short action pulses fsm -> ahc_fis_transmit
wire fsnd_clearCmdToIssue; // From CFIS:SUCCESS wire fsnd_clearCmdToIssue; // From CFIS:SUCCESS
// State variables fsm <- ahc_fis_transmit // State variables fsm <- ahc_fis_transmit
...@@ -313,7 +334,7 @@ module ahci_top#( ...@@ -313,7 +334,7 @@ module ahci_top#(
wire fsnd_ch_p; // prefetchable - only used with non-zero PRDTL or ATAPI bit set wire fsnd_ch_p; // prefetchable - only used with non-zero PRDTL or ATAPI bit set
wire fsnd_ch_w; // Write: system memory -> device wire fsnd_ch_w; // Write: system memory -> device
wire fsnd_ch_a; // ATAPI: 1 means device should send PIO setup FIS for ATAPI command wire fsnd_ch_a; // ATAPI: 1 means device should send PIO setup FIS for ATAPI command
wire [4:0] fsnd_ch_cfl; // length of the command FIS in DW, 0 means none. 0 and 1 - illegal, ... Maybe not needed outside ahc_fis_transmit /// wire [4:0] fsnd_ch_cfl; // length of the command FIS in DW, 0 means none. 0 and 1 - illegal, ... Maybe not needed outside ahc_fis_transmit
wire [11:0] data_out_dwords; // number of DWORDs sent in data FIS wire [11:0] data_out_dwords; // number of DWORDs sent in data FIS
...@@ -321,34 +342,34 @@ module ahci_top#( ...@@ -321,34 +342,34 @@ module ahci_top#(
wire was_port_rst; wire was_port_rst;
// signals between ahci_fsm and ahci_ctrl_stat // signals between ahci_fsm and ahci_ctrl_stat
wire update_regs_pending; /// wire update_regs_pending;
wire update_all_regs; wire update_all_regs;
wire update_regs_busy; // valid same cycle as update_all_regs wire update_regs_busy; // valid same cycle as update_all_regs
wire st01_pending; // software turned PxCMD.ST from 0 to 1 /// wire st01_pending; // software turned PxCMD.ST from 0 to 1
wire st10_pending; // software turned PxCMD.ST from 1 to 0 /// wire st10_pending; // software turned PxCMD.ST from 1 to 0
wire st_pending_reset;// reset both st01_pending and st10_pending /// wire st_pending_reset;// reset both st01_pending and st10_pending
// these following individual signals may be unneded - use update_all_regs -> update_regs_busy // these following individual signals may be unneded - use update_all_regs -> update_regs_busy
wire update_GHC__IS; // wire update_GHC__IS;
wire update_HBA_PORT__PxIS; // wire update_HBA_PORT__PxIS;
wire update_HBA_PORT__PxSSTS; // wire update_HBA_PORT__PxSSTS;
wire update_HBA_PORT__PxSERR; // wire update_HBA_PORT__PxSERR;
wire update_HBA_PORT__PxCMD; // wire update_HBA_PORT__PxCMD;
wire update_HBA_PORT__PxCI; // wire update_HBA_PORT__PxCI;
// PxCMD // PxCMD
wire pcmd_clear_icc; // clear PxCMD.ICC field // wire pcmd_clear_icc; // clear PxCMD.ICC field
wire pcmd_esp; // external SATA port (just forward value) wire pcmd_esp = 1'b0; // external SATA port (just forward value)
wire pcmd_cr; // command list run - current /// wire pcmd_cr; // command list run - current - read only by software (set by HBA)
wire pcmd_cr_set; // command list run set wire pcmd_cr_set; // command list run set
wire pcmd_cr_reset; // command list run reset wire pcmd_cr_reset; // command list run reset
wire pcmd_fr; // ahci_fis_receive:get_fis_busy // wire pcmd_fr; // ahci_fis_receive:get_fis_busy - use frcv_busy
wire pcmd_fre; // FIS enable copy to memory wire pcmd_fre; // FIS enable copy to memory
wire pcmd_clear_bsy_drq; // == ahci_fis_receive:clear_bsy_drq // wire pcmd_clear_bsy_drq; // == ahci_fis_receive:clear_bsy_drq
wire pcmd_clo; //RW1, causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit wire pcmd_clo; // RW1, causes ahci_fis_receive:clear_bsy_drq, that in turn resets this bit
wire pcmd_clear_st; // RW clear ST (start) bit // wire pcmd_clear_st; // RW clear ST (start) bit
wire pcmd_st; // current value wire pcmd_st; // current value
wire pfsm_started; // H: FSM done, P: FSM started (enable sensing pcmd_st_cleared) wire pfsm_started; // H: FSM done, P: FSM started (enable sensing pcmd_st_cleared)
wire pcmd_st_cleared; // bit was cleared by software wire pcmd_st_cleared; // bit was cleared by software
...@@ -369,20 +390,6 @@ module ahci_top#( ...@@ -369,20 +390,6 @@ module ahci_top#(
// SCR1:SError (only inputs that are not available in sirq_* ones // SCR1:SError (only inputs that are not available in sirq_* ones
//sirq_PC; //sirq_PC;
//sirq_UF //sirq_UF
wire serr_DT; // RWC: Transport state transition error
wire serr_DS; // RWC: Link sequence error
wire serr_DH; // RWC: Handshake Error (i.e. Device got CRC error)
wire serr_DC; // RWC: CRC error in Link layer
wire serr_DB; // RWC: 10B to 8B decode error
wire serr_DW; // RWC: COMMWAKE signal was detected
wire serr_DI; // RWC: PHY Internal Error
// sirq_PRC;
// sirq_IF || // sirq_INF
wire serr_EP; // RWC: Protocol Error - a violation of SATA protocol detected
wire serr_EC; // RWC: Persistent Communication or Data Integrity Error
wire serr_ET; // RWC: Transient Data Integrity Error (error not recovered by the interface)
wire serr_EM; // RWC: Communication between the device and host was lost but re-established
wire serr_EI; // RWC: Recovered Data integrity Error
wire serr_diag_X; // value of PxSERR.DIAG.X wire serr_diag_X; // value of PxSERR.DIAG.X
...@@ -406,8 +413,6 @@ module ahci_top#( ...@@ -406,8 +413,6 @@ module ahci_top#(
wire [3:0] ssts_det; // current value of PxSSTS.DET wire [3:0] ssts_det; // current value of PxSSTS.DET
// SCR2:SControl (written by software only) // SCR2:SControl (written by software only)
wire [3:0] sctl_ipm; // Interface power management transitions allowed
wire [3:0] sctl_spd; // Interface maximal speed
wire [3:0] sctl_det; // Device detection initialization requested wire [3:0] sctl_det; // Device detection initialization requested
wire sctl_det_changed; // Software had written new value to sctl_det wire sctl_det_changed; // Software had written new value to sctl_det
wire sctl_det_reset; // clear sctl_det_changed wire sctl_det_reset; // clear sctl_det_changed
...@@ -444,27 +449,27 @@ module ahci_top#( ...@@ -444,27 +449,27 @@ module ahci_top#(
.send_R_OK (send_R_OK), // output .send_R_OK (send_R_OK), // output
.send_R_ERR (send_R_ERR), // output .send_R_ERR (send_R_ERR), // output
.update_pending (update_regs_pending),// input /// .update_pending (update_regs_pending),// input
.update_all (update_all_regs), // output .update_all (update_all_regs), // output
.update_busy (update_regs_busy), // input .update_busy (update_regs_busy), // input
.update_gis (update_GHC__IS), // output /// .update_gis (update_GHC__IS), // output
.update_pis (update_HBA_PORT__PxIS), // output /// .update_pis (update_HBA_PORT__PxIS), // output
.update_ssts (update_HBA_PORT__PxSSTS), // output /// .update_ssts (update_HBA_PORT__PxSSTS), // output
.update_serr (update_HBA_PORT__PxSERR), // output /// .update_serr (update_HBA_PORT__PxSERR), // output
.update_pcmd (update_HBA_PORT__PxCMD), // output /// .update_pcmd (update_HBA_PORT__PxCMD), // output
.update_pci (update_HBA_PORT__PxCI), // output /// .update_pci (update_HBA_PORT__PxCI), // output
.st01_pending (st01_pending), // input /// .st01_pending (st01_pending), // input
.st10_pending (st10_pending), // input /// .st10_pending (st10_pending), // input
.st_pending_reset (st_pending_reset), // output /// .st_pending_reset (st_pending_reset), // output
.pcmd_clear_icc (pcmd_clear_icc), // output // .pcmd_clear_icc (pcmd_clear_icc), // output
.pcmd_esp (pcmd_esp), // output // .pcmd_esp (pcmd_esp), // output
.pcmd_cr (pcmd_cr), // input // .pcmd_cr (pcmd_cr), // input
.pcmd_cr_set (pcmd_cr_set), // output .pcmd_cr_set (pcmd_cr_set), // output
.pcmd_cr_reset (pcmd_cr_reset), // output .pcmd_cr_reset (pcmd_cr_reset), // output
.pcmd_fr (pcmd_fr), // output // .pcmd_fr (pcmd_fr), // output
.pcmd_clear_bsy_drq (pcmd_clear_bsy_drq),// output // .pcmd_clear_bsy_drq (pcmd_clear_bsy_drq),// output
.pcmd_clo (pcmd_clo), // input .pcmd_clo (pcmd_clo), // input
.pcmd_clear_st (pcmd_clear_st), // output // .pcmd_clear_st (pcmd_clear_st), // output
.pcmd_st (pcmd_st), // input .pcmd_st (pcmd_st), // input
.pfsm_started (pfsm_started), // output .pfsm_started (pfsm_started), // output
.pcmd_st_cleared (pcmd_st_cleared), // input .pcmd_st_cleared (pcmd_st_cleared), // input
...@@ -480,18 +485,6 @@ module ahci_top#( ...@@ -480,18 +485,6 @@ module ahci_top#(
.sirq_DS (sirq_DS), // output .sirq_DS (sirq_DS), // output
.sirq_PS (sirq_PS), // output .sirq_PS (sirq_PS), // output
.sirq_DHR (sirq_DHR), // output .sirq_DHR (sirq_DHR), // output
.serr_DT (serr_DT), // output
.serr_DS (serr_DS), // output
.serr_DH (serr_DH), // output
.serr_DC (serr_DC), // output
.serr_DB (serr_DB), // output
.serr_DW (serr_DW), // output
.serr_DI (serr_DI), // output
.serr_EP (serr_EP), // output
.serr_EC (serr_EC), // output
.serr_ET (serr_ET), // output
.serr_EM (serr_EM), // output
.serr_EI (serr_EI), // output
.serr_diag_X (serr_diag_X), // input .serr_diag_X (serr_diag_X), // input
.ssts_ipm_dnp (ssts_ipm_dnp), // output .ssts_ipm_dnp (ssts_ipm_dnp), // output
.ssts_ipm_active (ssts_ipm_active), // output .ssts_ipm_active (ssts_ipm_active), // output
...@@ -507,20 +500,20 @@ module ahci_top#( ...@@ -507,20 +500,20 @@ module ahci_top#(
.ssts_det_dp (ssts_det_dp), // output .ssts_det_dp (ssts_det_dp), // output
.ssts_det_offline (ssts_det_offline), // output .ssts_det_offline (ssts_det_offline), // output
.ssts_det (ssts_det), // input[3:0] .ssts_det (ssts_det), // input[3:0]
.sctl_ipm (sctl_ipm), // input[3:0] /// .sctl_ipm (sctl_ipm), // input[3:0]
.sctl_spd (sctl_spd), // input[3:0] /// .sctl_spd (sctl_spd), // input[3:0]
.sctl_det (sctl_det), // input[3:0] .sctl_det (sctl_det), // input[3:0]
.sctl_det_changed (sctl_det_changed), // input .sctl_det_changed (sctl_det_changed), // input
.sctl_det_reset (sctl_det_reset), // output .sctl_det_reset (sctl_det_reset), // output
.pxci0_clear (pxci0_clear), // output .pxci0_clear (pxci0_clear), // output
.pxci0 (pxci0), // input .pxci0 (pxci0), // input
.dma_prd_done (dma_prd_done), // input /// .dma_prd_done (dma_prd_done), // input
.dma_prd_irq_clear (dma_prd_irq_clear), // output .dma_prd_irq_clear (dma_prd_irq_clear), // output
.dma_prd_irq_pend (dma_prd_irq_pend), // input .dma_prd_irq_pend (dma_prd_irq_pend), // input
.dma_cmd_busy (dma_cmd_busy), // input /// .dma_cmd_busy (dma_cmd_busy), // input
.dma_cmd_done (dma_cmd_done), // input /// .dma_cmd_done (dma_cmd_done), // input
.dma_cmd_abort (dma_cmd_abort_fsm), // output .dma_cmd_abort (dma_cmd_abort_fsm), // output
.fis_first_invalid (frcv_first_invalid),// input .fis_first_invalid (frcv_first_invalid),// input
...@@ -537,7 +530,7 @@ module ahci_top#( ...@@ -537,7 +530,7 @@ module ahci_top#(
.get_ufis (frcv_get_ufis), // output .get_ufis (frcv_get_ufis), // output
.get_data_fis (frcv_get_data_fis), // output .get_data_fis (frcv_get_data_fis), // output
.get_ignore (frcv_get_ignore), // output .get_ignore (frcv_get_ignore), // output
.get_fis_busy (frcv_busy), // input /// .get_fis_busy (frcv_busy), // input
.get_fis_done (frcv_done), // input .get_fis_done (frcv_done), // input
.fis_ok (frcv_ok), // input .fis_ok (frcv_ok), // input
.fis_err (frcv_err), // input .fis_err (frcv_err), // input
...@@ -545,8 +538,8 @@ module ahci_top#( ...@@ -545,8 +538,8 @@ module ahci_top#(
.fis_extra (frcv_extra || dma_extra_din), // input // more data got from FIS than DMA can accept. Does not deny fis_ok. May have latency .fis_extra (frcv_extra || dma_extra_din), // input // more data got from FIS than DMA can accept. Does not deny fis_ok. May have latency
.set_update_sig (frcv_set_update_sig),// output .set_update_sig (frcv_set_update_sig),// output
.pUpdateSig (frcv_pUpdateSig), // input /// .pUpdateSig (frcv_pUpdateSig), // input
.sig_available (frcv_sig_available), // input /// .sig_available (frcv_sig_available), // input
.update_sig (frcv_update_sig), // output .update_sig (frcv_update_sig), // output
.update_err_sts (frcv_update_err_sts),// output .update_err_sts (frcv_update_err_sts),// output
...@@ -565,16 +558,16 @@ module ahci_top#( ...@@ -565,16 +558,16 @@ module ahci_top#(
.pPioXfer (pPioXfer), // input .pPioXfer (pPioXfer), // input
.tfd_sts (tfd_sts), // input[7:0] .tfd_sts (tfd_sts), // input[7:0]
.tfd_err (tfd_err), // input[7:0] /// .tfd_err (tfd_err), // input[7:0]
.fis_i (fis_i), // input .fis_i (fis_i), // input
.sdb_n (sdb_n), // input /// .sdb_n (sdb_n), // input
.dma_a (dma_a), // input .dma_a (dma_a), // input
.dma_d (dma_d), // input /// .dma_d (dma_d), // input
.pio_i (pio_i), // input .pio_i (pio_i), // input
.pio_d (pio_d), // input .pio_d (pio_d), // input
.sactive0 (sactive0), // input /// .sactive0 (sactive0), // input
.pio_es (pio_es), // input[7:0] /// .pio_es (pio_es), // input[7:0]
.xfer_cntr (xfer_cntr[31:2]), // input[31:2] /// .xfer_cntr (xfer_cntr[31:2]), // input[31:2]
.xfer_cntr_zero (xfer_cntr_zero), // input .xfer_cntr_zero (xfer_cntr_zero), // input
.fetch_cmd (fsnd_fetch_cmd), // output .fetch_cmd (fsnd_fetch_cmd), // output
...@@ -582,19 +575,19 @@ module ahci_top#( ...@@ -582,19 +575,19 @@ module ahci_top#(
.dx_transmit (fsnd_dx_transmit), // output .dx_transmit (fsnd_dx_transmit), // output
.atapi_xmit (fsnd_atapi_xmit), // output .atapi_xmit (fsnd_atapi_xmit), // output
.xmit_done (fsnd_done), // input .xmit_done (fsnd_done), // input
.xmit_busy (fsnd_busy), // input /// .xmit_busy (fsnd_busy), // input
.clearCmdToIssue (fsnd_clearCmdToIssue),// output // From CFIS:SUCCESS .clearCmdToIssue (fsnd_clearCmdToIssue),// output // From CFIS:SUCCESS
.pCmdToIssue (fsnd_pCmdToIssue), // input .pCmdToIssue (fsnd_pCmdToIssue), // input
.dx_err (fsnd_dx_err), // input[1:0] .dx_err (fsnd_dx_err), // input[1:0]
.ch_prdtl (prdtl), // input[15:0] /// .ch_prdtl (prdtl), // input[15:0]
.ch_c (fsnd_ch_c), // input .ch_c (fsnd_ch_c), // input
.ch_b (fsnd_ch_b), // input .ch_b (fsnd_ch_b), // input
.ch_r (fsnd_ch_r), // input .ch_r (fsnd_ch_r), // input
.ch_p (fsnd_ch_p), // input .ch_p (fsnd_ch_p), // input
.ch_w (fsnd_ch_w), // input .ch_w (fsnd_ch_w), // input
.ch_a (fsnd_ch_a), // input .ch_a (fsnd_ch_a) // input
.ch_cfl (fsnd_ch_cfl), // input[4:0] /// .ch_cfl (fsnd_ch_cfl), // input[4:0]
.dwords_sent (data_out_dwords) // input[11:0] ???? /// .dwords_sent (data_out_dwords) // input[11:0] ????
); );
...@@ -671,29 +664,30 @@ module ahci_top#( ...@@ -671,29 +664,30 @@ module ahci_top#(
.regs_addr (regs_saddr), // output[9:0] reg .regs_addr (regs_saddr), // output[9:0] reg
.regs_we (regs_we_acs), // output reg .regs_we (regs_we_acs), // output reg
.regs_din (regs_din_from_acs), // output[31:0] reg .regs_din (regs_din_from_acs), // output[31:0] reg
.update_pending (update_regs_pending), // output .update_pending (), /// update_regs_pending), // output
.update_all (update_all_regs), // input .update_all (update_all_regs), // input
.update_busy (update_regs_busy), // output .update_busy (update_regs_busy), // output
.st01_pending (st01_pending), // output reg /// .st01_pending (st01_pending), // output reg
.st10_pending (st10_pending), // output reg /// .st10_pending (st10_pending), // output reg
.st_pending_reset (st_pending_reset), // input /// .st_pending_reset (st_pending_reset), // input
.update_gis (1'b0), // update_GHC__IS), // input
.update_pis (1'b0), // update_HBA_PORT__PxIS), // input
.update_ssts (1'b0), // update_HBA_PORT__PxSSTS), // input
.update_serr (1'b0), // update_HBA_PORT__PxSERR), // input
.update_pcmd (1'b0), // update_HBA_PORT__PxCMD), // input
.update_pci (1'b0), // update_HBA_PORT__PxCI), // input
.update_gis (update_GHC__IS), // input .pcmd_clear_icc (1'b0), // pcmd_clear_icc), // input
.update_pis (update_HBA_PORT__PxIS), // input
.update_ssts (update_HBA_PORT__PxSSTS), // input
.update_serr (update_HBA_PORT__PxSERR), // input
.update_pcmd (update_HBA_PORT__PxCMD), // input
.update_pci (update_HBA_PORT__PxCI), // input
.pcmd_clear_icc (pcmd_clear_icc), // input
.pcmd_esp (pcmd_esp), // input .pcmd_esp (pcmd_esp), // input
.pcmd_cr (pcmd_cr), // output .pcmd_cr (), //pcmd_cr), // output
.pcmd_cr_set (pcmd_cr_set), // input .pcmd_cr_set (pcmd_cr_set), // input
.pcmd_cr_reset (pcmd_cr_reset), // input .pcmd_cr_reset (pcmd_cr_reset), // input
.pcmd_fr (pcmd_fr), // input .pcmd_fr (frcv_busy), // input
.pcmd_fre (pcmd_fre), // output .pcmd_fre (pcmd_fre), // output
.pcmd_clear_bsy_drq (pcmd_clear_bsy_drq), // input .pcmd_clear_bsy_drq (frcv_clear_bsy_drq), // input
.pcmd_clo (pcmd_clo), // output .pcmd_clo (pcmd_clo), // output
.pcmd_clear_st (pcmd_clear_st), // input .pcmd_clear_st (1'b0), // pcmd_clear_st), // input
.pcmd_st (pcmd_st), // output .pcmd_st (pcmd_st), // output
.pfsm_started (pfsm_started), // input .pfsm_started (pfsm_started), // input
.pcmd_st_cleared (pcmd_st_cleared), // output reg .pcmd_st_cleared (pcmd_st_cleared), // output reg
...@@ -766,12 +760,12 @@ module ahci_top#( ...@@ -766,12 +760,12 @@ module ahci_top#(
.ct_addr (dma_ct_addr), // input[4:0] .ct_addr (dma_ct_addr), // input[4:0]
.ct_re (dma_ct_re[0]), // input .ct_re (dma_ct_re[0]), // input
.ct_data (dma_ct_data), // output[31:0] reg .ct_data (dma_ct_data), // output[31:0] reg
.prd_done (dma_prd_done), // output .prd_done (), /// dma_prd_done), // output
.prd_irq_clear (dma_prd_irq_clear),// input .prd_irq_clear (dma_prd_irq_clear),// input
.prd_irq_pend (dma_prd_irq_pend), // output reg .prd_irq_pend (dma_prd_irq_pend), // output reg
.cmd_busy (dma_cmd_busy), // output reg .cmd_busy (), // dma_cmd_busy), // output reg
.cmd_done (dma_cmd_done), // output .cmd_done (dma_cmd_done), // output
.sys_out (dma_dout), // output[31:0] .sys_out (dma_dout), // output[31:0]
.sys_dav (dma_dav), // output .sys_dav (dma_dav), // output
...@@ -854,8 +848,8 @@ module ahci_top#( ...@@ -854,8 +848,8 @@ module ahci_top#(
.fis_extra (frcv_extra), // output .fis_extra (frcv_extra), // output
.set_update_sig (frcv_set_update_sig), // input .set_update_sig (frcv_set_update_sig), // input
.pUpdateSig (frcv_pUpdateSig), // output .pUpdateSig (), /// frcv_pUpdateSig), // output
.sig_available (frcv_sig_available), // output reg .sig_available (), ///frcv_sig_available), // output reg
.update_sig (frcv_update_sig), // input .update_sig (frcv_update_sig), // input
.update_err_sts (frcv_update_err_sts), // input .update_err_sts (frcv_update_err_sts), // input
...@@ -876,18 +870,18 @@ module ahci_top#( ...@@ -876,18 +870,18 @@ module ahci_top#(
.pPioXfer (pPioXfer), // output reg .pPioXfer (pPioXfer), // output reg
.tfd_sts (tfd_sts), // output[7:0] .tfd_sts (tfd_sts), // output[7:0]
.tfd_err (tfd_err), // output[7:0] .tfd_err (), /// tfd_err), // output[7:0]
.fis_i (fis_i), // output reg .fis_i (fis_i), // output reg
.sdb_n (sdb_n), // output reg .sdb_n (), /// sdb_n), // output reg
.dma_a (dma_a), // output reg .dma_a (dma_a), // output reg
.dma_d (dma_d), // output reg .dma_d (), /// dma_d), // output reg
.pio_i (pio_i), // output reg .pio_i (pio_i), // output reg
.pio_d (pio_d), // output reg .pio_d (pio_d), // output reg
.pio_es (pio_es), // output[7:0] reg .pio_es (), /// pio_es), // output[7:0] reg
.sactive0 (sactive0), // output reg .sactive0 (), /// sactive0), // output reg
.xfer_cntr (xfer_cntr[31:2]), // output[31:2] .xfer_cntr (xfer_cntr[31:2]), // output[31:2]
.xfer_cntr_zero (xfer_cntr_zero), // output reg .xfer_cntr_zero (xfer_cntr_zero), // output reg
.data_in_dwords (data_in_dwords), // output[11:0] .data_in_dwords (), /// data_in_dwords), // output[11:0]
.reg_addr (regs_waddr), // output[9:0] reg .reg_addr (regs_waddr), // output[9:0] reg
.reg_we (regs_we_freceive), // output reg .reg_we (regs_we_freceive), // output reg
...@@ -916,7 +910,7 @@ module ahci_top#( ...@@ -916,7 +910,7 @@ module ahci_top#(
.atapi_xmit (fsnd_atapi_xmit), // input .atapi_xmit (fsnd_atapi_xmit), // input
.done (fsnd_done), // output reg .done (fsnd_done), // output reg
.busy (fsnd_busy), // output reg .busy (), /// fsnd_busy), // output reg
.clearCmdToIssue (fsnd_clearCmdToIssue), // input .clearCmdToIssue (fsnd_clearCmdToIssue), // input
.pCmdToIssue (fsnd_pCmdToIssue), // output .pCmdToIssue (fsnd_pCmdToIssue), // output
.syncesc_recv (syncesc_recv), // input .syncesc_recv (syncesc_recv), // input
...@@ -929,7 +923,7 @@ module ahci_top#( ...@@ -929,7 +923,7 @@ module ahci_top#(
.ch_p (fsnd_ch_p), // output .ch_p (fsnd_ch_p), // output
.ch_w (fsnd_ch_w), // output .ch_w (fsnd_ch_w), // output
.ch_a (fsnd_ch_a), // output .ch_a (fsnd_ch_a), // output
.ch_cfl (fsnd_ch_cfl), // output[4:0] .ch_cfl (), /// fsnd_ch_cfl), // output[4:0]
.dwords_sent (data_out_dwords), // output[11:0] reg .dwords_sent (data_out_dwords), // output[11:0] reg
.reg_addr (regs_raddr), // output[9:0] reg .reg_addr (regs_raddr), // output[9:0] reg
......
ahci/axi_ahci_regs.v
View file @ 0f01238e
...@@ -60,7 +60,7 @@ module axi_ahci_regs#( ...@@ -60,7 +60,7 @@ module axi_ahci_regs#(
input [11:0] wid, // WID[11:0], input input [11:0] wid, // WID[11:0], input
input wlast, // WLAST, input input wlast, // WLAST, input
input [ 3:0] wstb, // WSTRB[3:0], input input [ 3:0] wstb, // WSTRB[3:0], input
// AXI PS Master GP0: Write Responce // AXI PS Master GP0: Write response
output bvalid, // BVALID, output output bvalid, // BVALID, output
input bready, // BREADY, input input bready, // BREADY, input
output [11:0] bid, // BID[11:0], output output [11:0] bid, // BID[11:0], output
......
device/oob_dev.v
View file @ 0f01238e
...@@ -48,7 +48,7 @@ module oob_dev #( ...@@ -48,7 +48,7 @@ module oob_dev #(
input wire rst, input wire rst,
input wire gtx_ready, input wire gtx_ready,
// oob responces // oob responses
input wire rxcominitdet_in, input wire rxcominitdet_in,
input wire rxcomwakedet_in, input wire rxcomwakedet_in,
input wire rxelecidle_in, input wire rxelecidle_in,
......
device/sata_phy_dev.v
View file @ 0f01238e
...@@ -112,7 +112,7 @@ oob_dev oob_dev( ...@@ -112,7 +112,7 @@ oob_dev oob_dev(
.rst (rst), .rst (rst),
// gtx is ready = all resets are done // gtx is ready = all resets are done
.gtx_ready (gtx_ready), .gtx_ready (gtx_ready),
// oob responces // oob responses
.rxcominitdet_in (rxcominitdet), .rxcominitdet_in (rxcominitdet),
.rxcomwakedet_in (rxcomwakedet), .rxcomwakedet_in (rxcomwakedet),
.rxelecidle_in (rxelecidle), .rxelecidle_in (rxelecidle),
......
dma/axi_regs.v
View file @ 0f01238e
...@@ -66,7 +66,7 @@ module axi_regs( ...@@ -66,7 +66,7 @@ module axi_regs(
input wire [11:0] WID, // AXI PS Master GP1 WID[11:0], output input wire [11:0] WID, // AXI PS Master GP1 WID[11:0], output
input wire WLAST, // AXI PS Master GP1 WLAST, output input wire WLAST, // AXI PS Master GP1 WLAST, output
input wire [3:0] WSTRB, // AXI PS Master GP1 WSTRB[3:0], output input wire [3:0] WSTRB, // AXI PS Master GP1 WSTRB[3:0], output
// AXI PS Master GP1: Write Responce // AXI PS Master GP1: Write response
output wire BVALID, // AXI PS Master GP1 BVALID, input output wire BVALID, // AXI PS Master GP1 BVALID, input
input wire BREADY, // AXI PS Master GP1 BREADY, output input wire BREADY, // AXI PS Master GP1 BREADY, output
output wire [11:0] BID, // AXI PS Master GP1 BID[11:0], input output wire [11:0] BID, // AXI PS Master GP1 BID[11:0], input
......
dma/sata_top.v
View file @ 0f01238e
...@@ -86,7 +86,7 @@ ...@@ -86,7 +86,7 @@
input wire [11:0] WID, // AXI PS Master GP1 WID[11:0], output input wire [11:0] WID, // AXI PS Master GP1 WID[11:0], output
input wire WLAST, // AXI PS Master GP1 WLAST, output input wire WLAST, // AXI PS Master GP1 WLAST, output
input wire [3:0] WSTRB, // AXI PS Master GP1 WSTRB[3:0], output input wire [3:0] WSTRB, // AXI PS Master GP1 WSTRB[3:0], output
// AXI PS Master GP1: Write Responce // AXI PS Master GP1: Write response
output wire BVALID, // AXI PS Master GP1 BVALID, input output wire BVALID, // AXI PS Master GP1 BVALID, input
input wire BREADY, // AXI PS Master GP1 BREADY, output input wire BREADY, // AXI PS Master GP1 BREADY, output
output wire [11:0] BID, // AXI PS Master GP1 BID[11:0], input output wire [11:0] BID, // AXI PS Master GP1 BID[11:0], input
......
dma/top.v
View file @ 0f01238e
...@@ -202,7 +202,7 @@ sata_top sata_top( ...@@ -202,7 +202,7 @@ sata_top sata_top(
.WID (maxi1_wid), .WID (maxi1_wid),
.WLAST (maxi1_wlast), .WLAST (maxi1_wlast),
.WSTRB (maxi1_wstb), .WSTRB (maxi1_wstb),
// AXI PS Master GP1: Write Responce // AXI PS Master GP1: Write response
.BVALID (maxi1_bvalid), .BVALID (maxi1_bvalid),
.BREADY (maxi1_bready), .BREADY (maxi1_bready),
.BID (maxi1_bid), .BID (maxi1_bid),
...@@ -306,7 +306,7 @@ PS7 ps7_i ( ...@@ -306,7 +306,7 @@ PS7 ps7_i (
.EMIOENET0SOFRX(), // GMII 0 Rx Start of Frame, output .EMIOENET0SOFRX(), // GMII 0 Rx Start of Frame, output
.EMIOENET0PTPDELAYREQRX(), // GMII 0 Rx PTP delay req frame detected .EMIOENET0PTPDELAYREQRX(), // GMII 0 Rx PTP delay req frame detected
.EMIOENET0PTPPDELAYREQRX(), // GMII 0 Rx PTP peer delay frame detected, output .EMIOENET0PTPPDELAYREQRX(), // GMII 0 Rx PTP peer delay frame detected, output
.EMIOENET0PTPPDELAYRESPRX(), // GMII 0 Rx PTP peer delay responce frame detected, output .EMIOENET0PTPPDELAYRESPRX(), // GMII 0 Rx PTP peer delay response frame detected, output
.EMIOENET0PTPSYNCFRAMERX(), // GMII 0 Rx PTP sync frame detected, output .EMIOENET0PTPSYNCFRAMERX(), // GMII 0 Rx PTP sync frame detected, output
// MDIO 0 // MDIO 0
.EMIOENET0MDIOMDC(), // MDIO 0 MD clock output, output .EMIOENET0MDIOMDC(), // MDIO 0 MD clock output, output
...@@ -338,7 +338,7 @@ PS7 ps7_i ( ...@@ -338,7 +338,7 @@ PS7 ps7_i (
.EMIOENET1SOFRX(), // GMII 1 Rx Start of Frame, output .EMIOENET1SOFRX(), // GMII 1 Rx Start of Frame, output
.EMIOENET1PTPDELAYREQRX(), // GMII 1 Rx PTP delay req frame detected .EMIOENET1PTPDELAYREQRX(), // GMII 1 Rx PTP delay req frame detected
.EMIOENET1PTPPDELAYREQRX(), // GMII 1 Rx PTP peer delay frame detected, output .EMIOENET1PTPPDELAYREQRX(), // GMII 1 Rx PTP peer delay frame detected, output
.EMIOENET1PTPPDELAYRESPRX(), // GMII 1 Rx PTP peer delay responce frame detected, output .EMIOENET1PTPPDELAYRESPRX(), // GMII 1 Rx PTP peer delay response frame detected, output
.EMIOENET1PTPSYNCFRAMERX(), // GMII 1 Rx PTP sync frame detected, output .EMIOENET1PTPSYNCFRAMERX(), // GMII 1 Rx PTP sync frame detected, output
// MDIO 1 // MDIO 1
.EMIOENET1MDIOMDC(), // MDIO 1 MD clock output, output .EMIOENET1MDIOMDC(), // MDIO 1 MD clock output, output
...@@ -578,7 +578,7 @@ PS7 ps7_i ( ...@@ -578,7 +578,7 @@ PS7 ps7_i (
.MAXIGP0WID (/*axi_wid[11:0]*/), // AXI PS Master GP0 WID[11:0], output .MAXIGP0WID (/*axi_wid[11:0]*/), // AXI PS Master GP0 WID[11:0], output
.MAXIGP0WLAST (/*axi_wlast*/), // AXI PS Master GP0 WLAST, output .MAXIGP0WLAST (/*axi_wlast*/), // AXI PS Master GP0 WLAST, output
.MAXIGP0WSTRB (/*axi_wstb[3:0]*/), // AXI PS Master GP0 WSTRB[3:0], output .MAXIGP0WSTRB (/*axi_wstb[3:0]*/), // AXI PS Master GP0 WSTRB[3:0], output
// AXI PS Master GP0: Write Responce // AXI PS Master GP0: Write response
.MAXIGP0BVALID (/*axi_bvalid*/), // AXI PS Master GP0 BVALID, input .MAXIGP0BVALID (/*axi_bvalid*/), // AXI PS Master GP0 BVALID, input
.MAXIGP0BREADY (/*axi_bready*/), // AXI PS Master GP0 BREADY, output .MAXIGP0BREADY (/*axi_bready*/), // AXI PS Master GP0 BREADY, output
.MAXIGP0BID (/*axi_bid[11:0]*/), // AXI PS Master GP0 BID[11:0], input .MAXIGP0BID (/*axi_bid[11:0]*/), // AXI PS Master GP0 BID[11:0], input
...@@ -626,7 +626,7 @@ PS7 ps7_i ( ...@@ -626,7 +626,7 @@ PS7 ps7_i (
.MAXIGP1WID (maxi1_wid), // AXI PS Master GP1 WID[11:0], output .MAXIGP1WID (maxi1_wid), // AXI PS Master GP1 WID[11:0], output
.MAXIGP1WLAST (maxi1_wlast), // AXI PS Master GP1 WLAST, output .MAXIGP1WLAST (maxi1_wlast), // AXI PS Master GP1 WLAST, output
.MAXIGP1WSTRB (maxi1_wstb), // AXI PS Master GP1 maxi1_wstb[3:0], output .MAXIGP1WSTRB (maxi1_wstb), // AXI PS Master GP1 maxi1_wstb[3:0], output
// AXI PS Master GP1: Write Responce // AXI PS Master GP1: Write response
.MAXIGP1BVALID (maxi1_bvalid), // AXI PS Master GP1 BVALID, input .MAXIGP1BVALID (maxi1_bvalid), // AXI PS Master GP1 BVALID, input
.MAXIGP1BREADY (maxi1_bready), // AXI PS Master GP1 BREADY, output .MAXIGP1BREADY (maxi1_bready), // AXI PS Master GP1 BREADY, output
.MAXIGP1BID (maxi1_bid), // AXI PS Master GP1 BID[11:0], input .MAXIGP1BID (maxi1_bid), // AXI PS Master GP1 BID[11:0], input
...@@ -674,7 +674,7 @@ PS7 ps7_i ( ...@@ -674,7 +674,7 @@ PS7 ps7_i (
.SAXIGP0WID(), // AXI PS Slave GP0 WID[5:0], input .SAXIGP0WID(), // AXI PS Slave GP0 WID[5:0], input
.SAXIGP0WLAST(), // AXI PS Slave GP0 WLAST, input .SAXIGP0WLAST(), // AXI PS Slave GP0 WLAST, input
.SAXIGP0WSTRB(), // AXI PS Slave GP0 WSTRB[3:0], input .SAXIGP0WSTRB(), // AXI PS Slave GP0 WSTRB[3:0], input
// AXI PS Slave GP0: Write Responce // AXI PS Slave GP0: Write response
.SAXIGP0BVALID(), // AXI PS Slave GP0 BVALID, output .SAXIGP0BVALID(), // AXI PS Slave GP0 BVALID, output
.SAXIGP0BREADY(), // AXI PS Slave GP0 BREADY, input .SAXIGP0BREADY(), // AXI PS Slave GP0 BREADY, input
.SAXIGP0BID(), // AXI PS Slave GP0 BID[5:0], output //TODO: Update range !!! .SAXIGP0BID(), // AXI PS Slave GP0 BID[5:0], output //TODO: Update range !!!
...@@ -722,7 +722,7 @@ PS7 ps7_i ( ...@@ -722,7 +722,7 @@ PS7 ps7_i (
.SAXIGP1WID(), // AXI PS Slave GP1 WID[5:0], input .SAXIGP1WID(), // AXI PS Slave GP1 WID[5:0], input
.SAXIGP1WLAST(), // AXI PS Slave GP1 WLAST, input .SAXIGP1WLAST(), // AXI PS Slave GP1 WLAST, input
.SAXIGP1WSTRB(), // AXI PS Slave GP1 WSTRB[3:0], input .SAXIGP1WSTRB(), // AXI PS Slave GP1 WSTRB[3:0], input
// AXI PS Slave GP1: Write Responce // AXI PS Slave GP1: Write response
.SAXIGP1BVALID(), // AXI PS Slave GP1 BVALID, output .SAXIGP1BVALID(), // AXI PS Slave GP1 BVALID, output
.SAXIGP1BREADY(), // AXI PS Slave GP1 BREADY, input .SAXIGP1BREADY(), // AXI PS Slave GP1 BREADY, input
.SAXIGP1BID(), // AXI PS Slave GP1 BID[5:0], output .SAXIGP1BID(), // AXI PS Slave GP1 BID[5:0], output
...@@ -776,7 +776,7 @@ PS7 ps7_i ( ...@@ -776,7 +776,7 @@ PS7 ps7_i (
.SAXIHP0WCOUNT(), // AXI PS Slave HP0 WCOUNT[7:0], output .SAXIHP0WCOUNT(), // AXI PS Slave HP0 WCOUNT[7:0], output
.SAXIHP0WACOUNT(), // AXI PS Slave HP0 WACOUNT[5:0], output .SAXIHP0WACOUNT(), // AXI PS Slave HP0 WACOUNT[5:0], output
.SAXIHP0WRISSUECAP1EN(), // AXI PS Slave HP0 WRISSUECAP1EN, input .SAXIHP0WRISSUECAP1EN(), // AXI PS Slave HP0 WRISSUECAP1EN, input
// AXI PS Slave HP0: Write Responce // AXI PS Slave HP0: Write response
.SAXIHP0BVALID(), // AXI PS Slave HP0 BVALID, output .SAXIHP0BVALID(), // AXI PS Slave HP0 BVALID, output
.SAXIHP0BREADY(), // AXI PS Slave HP0 BREADY, input .SAXIHP0BREADY(), // AXI PS Slave HP0 BREADY, input
.SAXIHP0BID(), // AXI PS Slave HP0 BID[5:0], output .SAXIHP0BID(), // AXI PS Slave HP0 BID[5:0], output
...@@ -830,7 +830,7 @@ PS7 ps7_i ( ...@@ -830,7 +830,7 @@ PS7 ps7_i (
.SAXIHP1WCOUNT(), // AXI PS Slave HP1 WCOUNT[7:0], output .SAXIHP1WCOUNT(), // AXI PS Slave HP1 WCOUNT[7:0], output
.SAXIHP1WACOUNT(), // AXI PS Slave HP1 WACOUNT[5:0], output .SAXIHP1WACOUNT(), // AXI PS Slave HP1 WACOUNT[5:0], output
.SAXIHP1WRISSUECAP1EN(), // AXI PS Slave HP1 WRISSUECAP1EN, input .SAXIHP1WRISSUECAP1EN(), // AXI PS Slave HP1 WRISSUECAP1EN, input
// AXI PS Slave HP1: Write Responce // AXI PS Slave HP1: Write response
.SAXIHP1BVALID(), // AXI PS Slave HP1 BVALID, output .SAXIHP1BVALID(), // AXI PS Slave HP1 BVALID, output
.SAXIHP1BREADY(), // AXI PS Slave HP1 BREADY, input .SAXIHP1BREADY(), // AXI PS Slave HP1 BREADY, input
.SAXIHP1BID(), // AXI PS Slave HP1 BID[5:0], output .SAXIHP1BID(), // AXI PS Slave HP1 BID[5:0], output
...@@ -884,7 +884,7 @@ PS7 ps7_i ( ...@@ -884,7 +884,7 @@ PS7 ps7_i (
.SAXIHP2WCOUNT(), // AXI PS Slave HP2 WCOUNT[7:0], output .SAXIHP2WCOUNT(), // AXI PS Slave HP2 WCOUNT[7:0], output
.SAXIHP2WACOUNT(), // AXI PS Slave HP2 WACOUNT[5:0], output .SAXIHP2WACOUNT(), // AXI PS Slave HP2 WACOUNT[5:0], output
.SAXIHP2WRISSUECAP1EN(), // AXI PS Slave HP2 WRISSUECAP1EN, input .SAXIHP2WRISSUECAP1EN(), // AXI PS Slave HP2 WRISSUECAP1EN, input
// AXI PS Slave HP2: Write Responce // AXI PS Slave HP2: Write response
.SAXIHP2BVALID(), // AXI PS Slave HP2 BVALID, output .SAXIHP2BVALID(), // AXI PS Slave HP2 BVALID, output
.SAXIHP2BREADY(), // AXI PS Slave HP2 BREADY, input .SAXIHP2BREADY(), // AXI PS Slave HP2 BREADY, input
.SAXIHP2BID(), // AXI PS Slave HP2 BID[5:0], output .SAXIHP2BID(), // AXI PS Slave HP2 BID[5:0], output
...@@ -938,7 +938,7 @@ PS7 ps7_i ( ...@@ -938,7 +938,7 @@ PS7 ps7_i (
.SAXIHP3WCOUNT (afi3_wcount), // AXI PS Slave HP3 WCOUNT[7:0], output .SAXIHP3WCOUNT (afi3_wcount), // AXI PS Slave HP3 WCOUNT[7:0], output
.SAXIHP3WACOUNT (afi3_wacount), // AXI PS Slave HP3 WACOUNT[5:0], output .SAXIHP3WACOUNT (afi3_wacount), // AXI PS Slave HP3 WACOUNT[5:0], output
.SAXIHP3WRISSUECAP1EN (afi3_wrissuecap1en), // AXI PS Slave HP3 WRISSUECAP1EN, input .SAXIHP3WRISSUECAP1EN (afi3_wrissuecap1en), // AXI PS Slave HP3 WRISSUECAP1EN, input
// AXI PS Slave HP3: Write Responce // AXI PS Slave HP3: Write response
.SAXIHP3BVALID (afi3_bvalid), // AXI PS Slave HP3 BVALID, output .SAXIHP3BVALID (afi3_bvalid), // AXI PS Slave HP3 BVALID, output
.SAXIHP3BREADY (afi3_bready), // AXI PS Slave HP3 BREADY, input .SAXIHP3BREADY (afi3_bready), // AXI PS Slave HP3 BREADY, input
.SAXIHP3BID (afi3_bid), // AXI PS Slave HP3 BID[5:0], output .SAXIHP3BID (afi3_bid), // AXI PS Slave HP3 BID[5:0], output
...@@ -989,7 +989,7 @@ PS7 ps7_i ( ...@@ -989,7 +989,7 @@ PS7 ps7_i (
.SAXIACPWID(), // AXI PS Slave ACP WID[2:0], input .SAXIACPWID(), // AXI PS Slave ACP WID[2:0], input
.SAXIACPWLAST(), // AXI PS Slave ACP WLAST, input .SAXIACPWLAST(), // AXI PS Slave ACP WLAST, input
.SAXIACPWSTRB(), // AXI PS Slave ACP WSTRB[7:0], input .SAXIACPWSTRB(), // AXI PS Slave ACP WSTRB[7:0], input
// AXI PS Slave ACP: Write Responce // AXI PS Slave ACP: Write response
.SAXIACPBVALID(), // AXI PS Slave ACP BVALID, output .SAXIACPBVALID(), // AXI PS Slave ACP BVALID, output
.SAXIACPBREADY(), // AXI PS Slave ACP BREADY, input .SAXIACPBREADY(), // AXI PS Slave ACP BREADY, input
.SAXIACPBID(), // AXI PS Slave ACP BID[2:0], output .SAXIACPBID(), // AXI PS Slave ACP BID[2:0], output
......
generated/action_decoder.v
View file @ 0f01238e
...@@ -16,6 +16,7 @@ module action_decoder ( ...@@ -16,6 +16,7 @@ module action_decoder (
output reg SIRQ_DP, output reg SIRQ_DP,
output reg SIRQ_DS, output reg SIRQ_DS,
output reg SIRQ_IF, output reg SIRQ_IF,
output reg SIRQ_INF,
output reg SIRQ_PS, output reg SIRQ_PS,
output reg SIRQ_SDB, output reg SIRQ_SDB,
output reg SIRQ_TFE, output reg SIRQ_TFE,
...@@ -66,48 +67,49 @@ module action_decoder ( ...@@ -66,48 +67,49 @@ module action_decoder (
SIRQ_DP <= enable && data[ 3] && data[ 0]; SIRQ_DP <= enable && data[ 3] && data[ 0];
SIRQ_DS <= enable && data[ 4] && data[ 0]; SIRQ_DS <= enable && data[ 4] && data[ 0];
SIRQ_IF <= enable && data[ 5] && data[ 0]; SIRQ_IF <= enable && data[ 5] && data[ 0];
SIRQ_PS <= enable && data[ 6] && data[ 0]; SIRQ_INF <= enable && data[ 6] && data[ 0];
SIRQ_SDB <= enable && data[ 7] && data[ 0]; SIRQ_PS <= enable && data[ 7] && data[ 0];
SIRQ_TFE <= enable && data[ 8] && data[ 0]; SIRQ_SDB <= enable && data[ 8] && data[ 0];
SIRQ_UF <= enable && data[ 9] && data[ 0]; SIRQ_TFE <= enable && data[ 9] && data[ 0];
PFSM_STARTED <= enable && data[10] && data[ 0]; SIRQ_UF <= enable && data[10] && data[ 0];
PCMD_CR_CLEAR <= enable && data[ 2] && data[ 1]; PFSM_STARTED <= enable && data[ 2] && data[ 1];
PCMD_CR_SET <= enable && data[ 3] && data[ 1]; PCMD_CR_CLEAR <= enable && data[ 3] && data[ 1];
PXCI0_CLEAR <= enable && data[ 4] && data[ 1]; PCMD_CR_SET <= enable && data[ 4] && data[ 1];
PXSSTS_DET_1 <= enable && data[ 5] && data[ 1]; PXCI0_CLEAR <= enable && data[ 5] && data[ 1];
SSTS_DET_OFFLINE <= enable && data[ 6] && data[ 1]; PXSSTS_DET_1 <= enable && data[ 6] && data[ 1];
SCTL_DET_CLEAR <= enable && data[ 7] && data[ 1]; SSTS_DET_OFFLINE <= enable && data[ 7] && data[ 1];
SET_UPDATE_SIG <= enable && data[ 8] && data[ 1]; SCTL_DET_CLEAR <= enable && data[ 8] && data[ 1];
UPDATE_SIG <= enable && data[ 9] && data[ 1]; SET_UPDATE_SIG <= enable && data[ 9] && data[ 1];
UPDATE_ERR_STS <= enable && data[10] && data[ 1]; UPDATE_SIG <= enable && data[10] && data[ 1];
UPDATE_PIO <= enable && data[ 3] && data[ 2]; UPDATE_ERR_STS <= enable && data[ 3] && data[ 2];
UPDATE_PRDBC <= enable && data[ 4] && data[ 2]; UPDATE_PIO <= enable && data[ 4] && data[ 2];
CLEAR_BSY_DRQ <= enable && data[ 5] && data[ 2]; UPDATE_PRDBC <= enable && data[ 5] && data[ 2];
CLEAR_BSY_SET_DRQ <= enable && data[ 6] && data[ 2]; CLEAR_BSY_DRQ <= enable && data[ 6] && data[ 2];
SET_BSY <= enable && data[ 7] && data[ 2]; CLEAR_BSY_SET_DRQ <= enable && data[ 7] && data[ 2];
SET_STS_7F <= enable && data[ 8] && data[ 2]; SET_BSY <= enable && data[ 8] && data[ 2];
SET_STS_80 <= enable && data[ 9] && data[ 2]; SET_STS_7F <= enable && data[ 9] && data[ 2];
XFER_CNTR_CLEAR <= enable && data[10] && data[ 2]; SET_STS_80 <= enable && data[10] && data[ 2];
DECR_DWC <= enable && data[ 4] && data[ 3]; XFER_CNTR_CLEAR <= enable && data[ 4] && data[ 3];
FIS_FIRST_FLUSH <= enable && data[ 5] && data[ 3]; DECR_DWC <= enable && data[ 5] && data[ 3];
CLEAR_CMD_TO_ISSUE <= enable && data[ 6] && data[ 3]; FIS_FIRST_FLUSH <= enable && data[ 6] && data[ 3];
DMA_ABORT <= enable && data[ 7] && data[ 3]; CLEAR_CMD_TO_ISSUE <= enable && data[ 7] && data[ 3];
DMA_PRD_IRQ_CLEAR <= enable && data[ 8] && data[ 3]; DMA_ABORT <= enable && data[ 8] && data[ 3];
XMIT_COMRESET <= enable && data[ 9] && data[ 3]; DMA_PRD_IRQ_CLEAR <= enable && data[ 9] && data[ 3];
SEND_SYNC_ESC <= enable && data[10] && data[ 3]; XMIT_COMRESET <= enable && data[10] && data[ 3];
SET_OFFLINE <= enable && data[ 5] && data[ 4]; SEND_SYNC_ESC <= enable && data[ 5] && data[ 4];
R_OK <= enable && data[ 6] && data[ 4]; SET_OFFLINE <= enable && data[ 6] && data[ 4];
R_ERR <= enable && data[ 7] && data[ 4]; R_OK <= enable && data[ 7] && data[ 4];
FETCH_CMD <= enable && data[ 8] && data[ 4]; R_ERR <= enable && data[ 8] && data[ 4];
ATAPI_XMIT <= enable && data[ 9] && data[ 4]; FETCH_CMD <= enable && data[ 9] && data[ 4];
CFIS_XMIT <= enable && data[10] && data[ 4]; ATAPI_XMIT <= enable && data[10] && data[ 4];
DX_XMIT <= enable && data[ 6] && data[ 5]; CFIS_XMIT <= enable && data[ 6] && data[ 5];
GET_DATA_FIS <= enable && data[ 7] && data[ 5]; DX_XMIT <= enable && data[ 7] && data[ 5];
GET_DSFIS <= enable && data[ 8] && data[ 5]; GET_DATA_FIS <= enable && data[ 8] && data[ 5];
GET_IGNORE <= enable && data[ 9] && data[ 5]; GET_DSFIS <= enable && data[ 9] && data[ 5];
GET_PSFIS <= enable && data[10] && data[ 5]; GET_IGNORE <= enable && data[10] && data[ 5];
GET_RFIS <= enable && data[ 7] && data[ 6]; GET_PSFIS <= enable && data[ 7] && data[ 6];
GET_SDBFIS <= enable && data[ 8] && data[ 6]; GET_RFIS <= enable && data[ 8] && data[ 6];
GET_UFIS <= enable && data[ 9] && data[ 6]; GET_SDBFIS <= enable && data[ 9] && data[ 6];
GET_UFIS <= enable && data[10] && data[ 6];
end end
endmodule endmodule
helpers/ahci_fsm_sequence.py
View file @ 0f01238e
...@@ -45,7 +45,7 @@ code_rom_path= '../includes/ahxi_fsm_code.vh' ...@@ -45,7 +45,7 @@ code_rom_path= '../includes/ahxi_fsm_code.vh'
#Set actions, conditions to empty string to rebuild list. Then edit order and put here #Set actions, conditions to empty string to rebuild list. Then edit order and put here
actions = ['NOP', actions = ['NOP',
# CTRL_STAT # CTRL_STAT
'PXSERR_DIAG_X', 'SIRQ_DHR', 'SIRQ_DP', 'SIRQ_DS', 'SIRQ_IF', 'SIRQ_PS', 'SIRQ_SDB', 'SIRQ_TFE', 'SIRQ_UF', 'PXSERR_DIAG_X', 'SIRQ_DHR', 'SIRQ_DP', 'SIRQ_DS', 'SIRQ_IF', 'SIRQ_INF', 'SIRQ_PS', 'SIRQ_SDB', 'SIRQ_TFE', 'SIRQ_UF',
'PFSM_STARTED', 'PCMD_CR_CLEAR', 'PCMD_CR_SET', 'PXCI0_CLEAR', 'PXSSTS_DET_1', 'SSTS_DET_OFFLINE', 'SCTL_DET_CLEAR', 'PFSM_STARTED', 'PCMD_CR_CLEAR', 'PCMD_CR_SET', 'PXCI0_CLEAR', 'PXSSTS_DET_1', 'SSTS_DET_OFFLINE', 'SCTL_DET_CLEAR',
# FIS RECEIVE # FIS RECEIVE
'SET_UPDATE_SIG', 'UPDATE_SIG', 'UPDATE_ERR_STS', 'UPDATE_PIO', 'UPDATE_PRDBC', 'CLEAR_BSY_DRQ', 'SET_UPDATE_SIG', 'UPDATE_SIG', 'UPDATE_ERR_STS', 'UPDATE_PIO', 'UPDATE_PRDBC', 'CLEAR_BSY_DRQ',
...@@ -55,7 +55,7 @@ actions = ['NOP', ...@@ -55,7 +55,7 @@ actions = ['NOP',
# DMA # DMA
'DMA_ABORT', 'DMA_PRD_IRQ_CLEAR', 'DMA_ABORT', 'DMA_PRD_IRQ_CLEAR',
# SATA TRANSPORT/LINK/PHY # SATA TRANSPORT/LINK/PHY
'XMIT_COMRESET', 'SEND_SYNC_ESC', 'SET_OFFLINE', 'R_OK', 'R_ERR', 'XMIT_COMRESET', 'SEND_SYNC_ESC*', 'SET_OFFLINE', 'R_OK', 'R_ERR',
# FIS TRANSMIT/WAIT DONE # FIS TRANSMIT/WAIT DONE
'FETCH_CMD*', 'ATAPI_XMIT*', 'CFIS_XMIT*', 'DX_XMIT*', 'FETCH_CMD*', 'ATAPI_XMIT*', 'CFIS_XMIT*', 'DX_XMIT*',
#FIS RECEIVE/WAIT DONE #FIS RECEIVE/WAIT DONE
...@@ -227,7 +227,7 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -227,7 +227,7 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{IF:'PIO_SETUP', GOTO:'PIO:Entry' }, # 12 FIS == FIS_PIO_SETUP {IF:'PIO_SETUP', GOTO:'PIO:Entry' }, # 12 FIS == FIS_PIO_SETUP
{ GOTO:'UFIS:Entry' }, # 13 Unknown FIS (else) { GOTO:'UFIS:Entry' }, # 13 Unknown FIS (else)
#5.3.6. Command Transfer State #5.3.6. Command Transfer State
{LBL:'CFIS:SyncEscape', ACT: 'SEND_SYNC_ESC'}, # syncesc_send, should wait (for syncesc_send_done) {LBL:'CFIS:SyncEscape', ACT: 'SEND_SYNC_ESC*'}, # syncesc_send, should wait (for syncesc_send_done)
{ ACT: 'SET_UPDATE_SIG'}, # set_update_sig { ACT: 'SET_UPDATE_SIG'}, # set_update_sig
{ GOTO:'CFIS:Xmit' }, # 1 { GOTO:'CFIS:Xmit' }, # 1
...@@ -438,6 +438,7 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP}, ...@@ -438,6 +438,7 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{ GOTO:'ERR:WaitForClear' }, # Loop until PxCMD.ST is cleared by software { GOTO:'ERR:WaitForClear' }, # Loop until PxCMD.ST is cleared by software
{LBL:'ERR:Non-Fatal', ACT: 'NOP'}, # Do anything else here? {LBL:'ERR:Non-Fatal', ACT: 'NOP'}, # Do anything else here?
{ ACT: 'SIRQ_INF'}, # sirq_INF
{ GOTO:'P:Idle'}, # { GOTO:'P:Idle'}, #
] ]
def get_cnk (start,end,level): def get_cnk (start,end,level):
......
host/oob.v
View file @ 0f01238e
...@@ -47,7 +47,7 @@ module oob #( ...@@ -47,7 +47,7 @@ module oob #(
input wire clk, input wire clk,
// reset oob // reset oob
input wire rst, input wire rst,
// oob responces // oob responses
input wire rxcominitdet_in, input wire rxcominitdet_in,
input wire rxcomwakedet_in, input wire rxcomwakedet_in,
input wire rxelecidle_in, input wire rxelecidle_in,
......
host/oob_ctrl.v
View file @ 0f01238e
...@@ -44,7 +44,7 @@ module oob_ctrl #( ...@@ -44,7 +44,7 @@ module oob_ctrl #(
// gtx is ready = all resets are done // gtx is ready = all resets are done
input wire gtx_ready, input wire gtx_ready,
output wire [11:0] debug, output wire [11:0] debug,
// oob responces // oob responses
input wire rxcominitdet_in, input wire rxcominitdet_in,
input wire rxcomwakedet_in, input wire rxcomwakedet_in,
input wire rxelecidle_in, input wire rxelecidle_in,
...@@ -137,7 +137,7 @@ oob ...@@ -137,7 +137,7 @@ oob
.clk (clk), .clk (clk),
// reset oob // reset oob
.rst (rst), .rst (rst),
// oob responces // oob responses
.rxcominitdet_in (rxcominitdet_in), .rxcominitdet_in (rxcominitdet_in),
.rxcomwakedet_in (rxcomwakedet_in), .rxcomwakedet_in (rxcomwakedet_in),
.rxelecidle_in (rxelecidle_in), .rxelecidle_in (rxelecidle_in),
......
host/sata_phy.v
View file @ 0f01238e
...@@ -120,7 +120,7 @@ oob_ctrl oob_ctrl( ...@@ -120,7 +120,7 @@ oob_ctrl oob_ctrl(
// gtx is ready = all resets are done // gtx is ready = all resets are done
.gtx_ready (gtx_ready), .gtx_ready (gtx_ready),
.debug ({dummy,debug_cnt[10:0]}), .debug ({dummy,debug_cnt[10:0]}),
// oob responces // oob responses
.rxcominitdet_in (rxcominitdet), .rxcominitdet_in (rxcominitdet),
.rxcomwakedet_in (rxcomwakedet), .rxcomwakedet_in (rxcomwakedet),
.rxelecidle_in (rxelecidle), .rxelecidle_in (rxelecidle),
......
includes/ahxi_fsm_code.vh 0 → 100644
View file @ 0f01238e
, .INIT_00 (256'h00100000000E0000000C00000030000000200000000A0000000A0000000A0000)
, .INIT_01 (256'h0019444F1C369443542D44170000001900480019040802020204008400220006)
, .INIT_02 (256'h0019010200500019000C04020090002924F824FF014000190003004204040000)
, .INIT_03 (256'h021000368C68844F84BB44344C652C3F14190012003600480018000A01080022)
, .INIT_04 (256'h00000036000000190090003600900019144301020408020202040036B07A7077)
, .INIT_05 (256'h98A458D4387F64510C2504550000004B24F824FF0420004924F824FF04200059)
, .INIT_06 (256'h30ED008800FFA46E50F590360060010400680202003000DFA89068ED18E618C8)
, .INIT_07 (256'h01400099D0F80410003600000036B07A0000004D004400220036B07A70773074)
, .INIT_08 (256'h004D0402008E0005008EC88C00220024008E288828FB000C0090008324F824FF)
, .INIT_09 (256'h00220024003648A2289E28FB00140036487C0CAA28FB0090009424F824FF00C0)
, .INIT_0A (256'h50F500A000AE88360899020800AA009000A824F824FF0420004D0081004D48A2)
, .INIT_0B (256'h24F824F8012000BD020800368899020800090036889950B70024002800B2D0F8)
, .INIT_0C (256'h001100D1C8CF009000CC24F824FF02200036889950B700240028009000C2C4FF)
, .INIT_0D (256'h0440004D0101004DC8DD28FB000C009000D824F824FF0240003634CF000000D1)
, .INIT_0E (256'h24F824FF042000F30082009000EA24F824FF042000360401009000E324F824FF)
, .INIT_0F (256'h000000FD000000FD020100FD0021011000FD0021004400F3000000F3009000F1)
, .INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000360041)
, .INITP_00 (256'hC3208802605C240900789C9C8888A000C250620020809C802018880022222222)
, .INITP_01 (256'h088820889C827209C828270882271A009C86068072E227218168AA2722081A09)
, .INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000002)
includes/fis_types.vh 0 → 100644
View file @ 0f01238e
// FIS types (low byte of the first DWORD)
localparam FIS_H2DR = 'h27;
localparam FIS_D2HR = 'h34;
localparam FIS_DMAA = 'h39;
localparam FIS_DMAS = 'h41;
localparam FIS_DATA = 'h46;
localparam FIS_BIST = 'h58;
localparam FIS_PIOS = 'h5f;
localparam FIS_SDB = 'ha1;
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