Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
X
x393_sata
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
Elphel
x393_sata
Commits
f4dc8593
Commit
f4dc8593
authored
Jan 19, 2016
by
Andrey Filippov
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Connected generated decoder+multiplexer to AHCI state machine
parent
3e169400
Changes
4
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
200 additions
and
166 deletions
+200
-166
ahci_fsm.v
ahci/ahci_fsm.v
+145
-120
ahci_top.v
ahci/ahci_top.v
+10
-5
action_decoder.v
generated/action_decoder.v
+34
-32
ahci_fsm_sequence.py
helpers/ahci_fsm_sequence.py
+11
-9
No files found.
ahci/ahci_fsm.v
View file @
f4dc8593
This diff is collapsed.
Click to expand it.
ahci/ahci_top.v
View file @
f4dc8593
...
...
@@ -147,6 +147,7 @@ module ahci_top#(
input
xmit_err
,
// Error during sending of a FIS
output
syncesc_send
,
// Send sync escape
input
syncesc_send_done
,
// "SYNC escape until the interface is quiescent..."
output
comreset_send
,
// Not possible yet?
input
cominit_got
,
output
set_offline
,
// electrically idle
input
x_rdy_collision
,
// X_RDY/X_RDY collision on interface
...
...
@@ -197,7 +198,9 @@ module ahci_top#(
wire
dev_wr
;
// input
wire
dma_cmd_start
;
// input
wire
dma_prd_start
;
// input
wire
dma_cmd_abort
;
// input
wire
dma_cmd_abort_xmit
;
// input
wire
dma_cmd_abort_fsm
;
// abort from FSM (also from ahci_fis_transmit)
// Use some of the custom registers in the address space?
wire
[
17
:
0
]
fsm_pgm_ad
;
// @aclk, address/data to program the AHCI FSM
wire
fsm_pgm_wa
;
// @aclk, address strobe to program the AHCI FSM
...
...
@@ -432,6 +435,7 @@ module ahci_top#(
.
phy_ready
(
phy_ready
)
,
// input
.
syncesc_send
(
syncesc_send
)
,
// output
.
comreset_send
(
comreset_send
)
,
// output
.
syncesc_send_done
(
syncesc_send_done
)
,
// input
.
cominit_got
(
cominit_got
)
,
// input
.
set_offline
(
set_offline
)
,
// output
...
...
@@ -515,8 +519,9 @@ module ahci_top#(
.
dma_prd_irq_clear
(
dma_prd_irq_clear
)
,
// output
.
dma_prd_irq_pend
(
dma_prd_irq_pend
)
,
// input
.
dma_cmd_busy
(
dma_cmd_busy
)
,
// input
.
dma_cmd_done
(
dma_cmd_done
)
,
// input
.
dma_cmd_busy
(
dma_cmd_busy
)
,
// input
.
dma_cmd_done
(
dma_cmd_done
)
,
// input
.
dma_cmd_abort
(
dma_cmd_abort_fsm
)
,
// output
.
fis_first_invalid
(
frcv_first_invalid
)
,
// input
.
fis_first_flush
(
frcv_first_flush
)
,
// output
...
...
@@ -752,7 +757,7 @@ module ahci_top#(
.
dev_wr
(
dev_wr
)
,
// input
.
cmd_start
(
dma_cmd_start
)
,
// input
.
prd_start
(
dma_prd_start
)
,
// input
.
cmd_abort
(
dma_cmd_abort
)
,
// input
.
cmd_abort
(
dma_cmd_abort
_xmit
||
dma_cmd_abort_fsm
)
,
// input
.
axi_wr_cache_mode
(
axi_wr_cache_mode
)
,
// input[3:0]
.
axi_rd_cache_mode
(
axi_rd_cache_mode
)
,
// input[3:0]
.
set_axi_wr_cache_mode
(
set_axi_cache_mode
)
,
// input
...
...
@@ -936,7 +941,7 @@ module ahci_top#(
.
dma_dev_wr
(
dev_wr
)
,
// output
.
dma_ct_busy
(
dma_ct_busy
)
,
// input
.
dma_prd_start
(
dma_prd_start
)
,
// output reg
.
dma_cmd_abort
(
dma_cmd_abort
)
,
// output reg
.
dma_cmd_abort
(
dma_cmd_abort
_xmit
)
,
// output reg
.
ct_addr
(
dma_ct_addr
)
,
// output[4:0] reg
.
ct_re
(
dma_ct_re
)
,
// output[1:0]
.
ct_data
(
dma_ct_data
)
,
// input[31:0]
...
...
generated/action_decoder.v
View file @
f4dc8593
...
...
@@ -26,6 +26,7 @@ module action_decoder (
output
reg
PXCI0_CLEAR
,
output
reg
PXSSTS_DET_1
,
output
reg
SSTS_DET_OFFLINE
,
output
reg
SCTL_DET_CLEAR
,
output
reg
SET_UPDATE_SIG
,
output
reg
UPDATE_SIG
,
output
reg
UPDATE_ERR_STS
,
...
...
@@ -75,37 +76,38 @@ module action_decoder (
PXCI0_CLEAR
<=
enable
&&
data
[
4
]
&&
data
[
1
]
;
PXSSTS_DET_1
<=
enable
&&
data
[
5
]
&&
data
[
1
]
;
SSTS_DET_OFFLINE
<=
enable
&&
data
[
6
]
&&
data
[
1
]
;
SET_UPDATE_SIG
<=
enable
&&
data
[
7
]
&&
data
[
1
]
;
UPDATE_SIG
<=
enable
&&
data
[
8
]
&&
data
[
1
]
;
UPDATE_ERR_STS
<=
enable
&&
data
[
9
]
&&
data
[
1
]
;
UPDATE_PIO
<=
enable
&&
data
[
10
]
&&
data
[
1
]
;
UPDATE_PRDBC
<=
enable
&&
data
[
3
]
&&
data
[
2
]
;
CLEAR_BSY_DRQ
<=
enable
&&
data
[
4
]
&&
data
[
2
]
;
CLEAR_BSY_SET_DRQ
<=
enable
&&
data
[
5
]
&&
data
[
2
]
;
SET_BSY
<=
enable
&&
data
[
6
]
&&
data
[
2
]
;
SET_STS_7F
<=
enable
&&
data
[
7
]
&&
data
[
2
]
;
SET_STS_80
<=
enable
&&
data
[
8
]
&&
data
[
2
]
;
XFER_CNTR_CLEAR
<=
enable
&&
data
[
9
]
&&
data
[
2
]
;
DECR_DWC
<=
enable
&&
data
[
10
]
&&
data
[
2
]
;
FIS_FIRST_FLUSH
<=
enable
&&
data
[
4
]
&&
data
[
3
]
;
CLEAR_CMD_TO_ISSUE
<=
enable
&&
data
[
5
]
&&
data
[
3
]
;
DMA_ABORT
<=
enable
&&
data
[
6
]
&&
data
[
3
]
;
DMA_PRD_IRQ_CLEAR
<=
enable
&&
data
[
7
]
&&
data
[
3
]
;
XMIT_COMRESET
<=
enable
&&
data
[
8
]
&&
data
[
3
]
;
SEND_SYNC_ESC
<=
enable
&&
data
[
9
]
&&
data
[
3
]
;
SET_OFFLINE
<=
enable
&&
data
[
10
]
&&
data
[
3
]
;
R_OK
<=
enable
&&
data
[
5
]
&&
data
[
4
]
;
R_ERR
<=
enable
&&
data
[
6
]
&&
data
[
4
]
;
FETCH_CMD
<=
enable
&&
data
[
7
]
&&
data
[
4
]
;
ATAPI_XMIT
<=
enable
&&
data
[
8
]
&&
data
[
4
]
;
CFIS_XMIT
<=
enable
&&
data
[
9
]
&&
data
[
4
]
;
DX_XMIT
<=
enable
&&
data
[
10
]
&&
data
[
4
]
;
GET_DATA_FIS
<=
enable
&&
data
[
6
]
&&
data
[
5
]
;
GET_DSFIS
<=
enable
&&
data
[
7
]
&&
data
[
5
]
;
GET_IGNORE
<=
enable
&&
data
[
8
]
&&
data
[
5
]
;
GET_PSFIS
<=
enable
&&
data
[
9
]
&&
data
[
5
]
;
GET_RFIS
<=
enable
&&
data
[
10
]
&&
data
[
5
]
;
GET_SDBFIS
<=
enable
&&
data
[
7
]
&&
data
[
6
]
;
GET_UFIS
<=
enable
&&
data
[
8
]
&&
data
[
6
]
;
SCTL_DET_CLEAR
<=
enable
&&
data
[
7
]
&&
data
[
1
]
;
SET_UPDATE_SIG
<=
enable
&&
data
[
8
]
&&
data
[
1
]
;
UPDATE_SIG
<=
enable
&&
data
[
9
]
&&
data
[
1
]
;
UPDATE_ERR_STS
<=
enable
&&
data
[
10
]
&&
data
[
1
]
;
UPDATE_PIO
<=
enable
&&
data
[
3
]
&&
data
[
2
]
;
UPDATE_PRDBC
<=
enable
&&
data
[
4
]
&&
data
[
2
]
;
CLEAR_BSY_DRQ
<=
enable
&&
data
[
5
]
&&
data
[
2
]
;
CLEAR_BSY_SET_DRQ
<=
enable
&&
data
[
6
]
&&
data
[
2
]
;
SET_BSY
<=
enable
&&
data
[
7
]
&&
data
[
2
]
;
SET_STS_7F
<=
enable
&&
data
[
8
]
&&
data
[
2
]
;
SET_STS_80
<=
enable
&&
data
[
9
]
&&
data
[
2
]
;
XFER_CNTR_CLEAR
<=
enable
&&
data
[
10
]
&&
data
[
2
]
;
DECR_DWC
<=
enable
&&
data
[
4
]
&&
data
[
3
]
;
FIS_FIRST_FLUSH
<=
enable
&&
data
[
5
]
&&
data
[
3
]
;
CLEAR_CMD_TO_ISSUE
<=
enable
&&
data
[
6
]
&&
data
[
3
]
;
DMA_ABORT
<=
enable
&&
data
[
7
]
&&
data
[
3
]
;
DMA_PRD_IRQ_CLEAR
<=
enable
&&
data
[
8
]
&&
data
[
3
]
;
XMIT_COMRESET
<=
enable
&&
data
[
9
]
&&
data
[
3
]
;
SEND_SYNC_ESC
<=
enable
&&
data
[
10
]
&&
data
[
3
]
;
SET_OFFLINE
<=
enable
&&
data
[
5
]
&&
data
[
4
]
;
R_OK
<=
enable
&&
data
[
6
]
&&
data
[
4
]
;
R_ERR
<=
enable
&&
data
[
7
]
&&
data
[
4
]
;
FETCH_CMD
<=
enable
&&
data
[
8
]
&&
data
[
4
]
;
ATAPI_XMIT
<=
enable
&&
data
[
9
]
&&
data
[
4
]
;
CFIS_XMIT
<=
enable
&&
data
[
10
]
&&
data
[
4
]
;
DX_XMIT
<=
enable
&&
data
[
6
]
&&
data
[
5
]
;
GET_DATA_FIS
<=
enable
&&
data
[
7
]
&&
data
[
5
]
;
GET_DSFIS
<=
enable
&&
data
[
8
]
&&
data
[
5
]
;
GET_IGNORE
<=
enable
&&
data
[
9
]
&&
data
[
5
]
;
GET_PSFIS
<=
enable
&&
data
[
10
]
&&
data
[
5
]
;
GET_RFIS
<=
enable
&&
data
[
7
]
&&
data
[
6
]
;
GET_SDBFIS
<=
enable
&&
data
[
8
]
&&
data
[
6
]
;
GET_UFIS
<=
enable
&&
data
[
9
]
&&
data
[
6
]
;
end
endmodule
helpers/ahci_fsm_sequence.py
View file @
f4dc8593
...
...
@@ -46,7 +46,7 @@ code_rom_path= '../includes/ahxi_fsm_code.vh'
actions
=
[
'NOP'
,
# CTRL_STAT
'PXSERR_DIAG_X'
,
'SIRQ_DHR'
,
'SIRQ_DP'
,
'SIRQ_DS'
,
'SIRQ_IF'
,
'SIRQ_PS'
,
'SIRQ_SDB'
,
'SIRQ_TFE'
,
'SIRQ_UF'
,
'PFSM_STARTED'
,
'PCMD_CR_CLEAR'
,
'PCMD_CR_SET'
,
'PXCI0_CLEAR'
,
'PXSSTS_DET_1'
,
'SSTS_DET_OFFLINE'
,
'PFSM_STARTED'
,
'PCMD_CR_CLEAR'
,
'PCMD_CR_SET'
,
'PXCI0_CLEAR'
,
'PXSSTS_DET_1'
,
'SSTS_DET_OFFLINE'
,
'SCTL_DET_CLEAR'
,
# FIS RECEIVE
'SET_UPDATE_SIG'
,
'UPDATE_SIG'
,
'UPDATE_ERR_STS'
,
'UPDATE_PIO'
,
'UPDATE_PRDBC'
,
'CLEAR_BSY_DRQ'
,
'CLEAR_BSY_SET_DRQ'
,
'SET_BSY'
,
'SET_STS_7F'
,
'SET_STS_80'
,
'XFER_CNTR_CLEAR'
,
'DECR_DWC'
,
'FIS_FIRST_FLUSH'
,
...
...
@@ -109,7 +109,7 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{
ACT
:
'CLEAR_BSY_SET_DRQ'
},
# clear_bsy_set_drq
{
ACT
:
'SET_STS_7F'
},
# set_sts_7f
{
ACT
:
'SET_UPDATE_SIG'
},
# set_update_sig
{
ACT
:
'XMIT_COMRESET'
},
# Now does it on reset. See if it is possible to transmit COMRESET w/o reset
{
ACT
:
'XMIT_COMRESET'
},
#
comreset_send (not yet implemented)
Now does it on reset. See if it is possible to transmit COMRESET w/o reset
{
GOTO
:
'P:NotRunning'
},
{
LBL
:
'P:NotRunningGarbage'
,
ACT
:
'FIS_FIRST_FLUSH'
},
# fis_first_flush (FIFO output has data, but not FIS head
...
...
@@ -123,12 +123,12 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
# Transition 8. PxCMD.FRE written to ‘1’ from a ‘0’ and previously processed Register FIS is in receive FIFO and PxSERR.DIAG.X = ‘0’
# can not be implemented - it is too late, FIS is already gone. So as we do not move FIS receive area, there is no sense to disable FIS,
# and for the signature we'll always assume FRE is on
{
IF
:
'ST_NB_ND'
,
GOTO
:
'P:Idle'
},
#12 : PxCMD.ST & !PxT
BD.STS.BSY & !PxTB
D.STS.DRQ
{
IF
:
'ST_NB_ND'
,
GOTO
:
'P:Idle'
},
#12 : PxCMD.ST & !PxT
FD.STS.BSY & !PxTF
D.STS.DRQ
{
IF
:
'FR_D2HR'
,
GOTO
:
'NDR:Entry'
},
#13 fis_first_vld & fis_type == 0x34 (D2H Register)
{
GOTO
:
'P:NotRunning'
},
#14
{
LBL
:
'P:Cominit'
,
ACT
:
'NOP'
},
# got here asynchronously from COMINIT label
{
ACT
:
'SET_STS_80'
},
#
frcv_
set_sts_80 (Not clear 0xff or 0x80 should be here?)
{
ACT
:
'SET_STS_80'
},
# set_sts_80 (Not clear 0xff or 0x80 should be here?)
{
ACT
:
'PXSSTS_DET_1'
},
# ssts_det_dnp, // device detected, but phy communication not established
{
ACT
:
'PXSERR_DIAG_X'
},
# sirq_PC, // RO: Port Connect Change Status (pulse to set)
# {IF:'PXIE_PCE', GOTO:'P:CominitSetIS'}, # Not needed, interrupt
...
...
@@ -144,12 +144,13 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{
ACT
:
'UPDATE_ERR_STS'
},
# update_err_sts
{
GOTO
:
'P:NotRunning'
},
# {IF: 'PCMD_FRE', GOTO:'P:RegFisPostToMem'}, # pcmd_fre hardware always copies signature FIS to 'memory' if expected
# {IF: 'PCMD_FRE', GOTO:'P:RegFisPostToMem'}, # p
x
cmd_fre hardware always copies signature FIS to 'memory' if expected
# {LBL:'P:RegFisPostToMem', ACT: 'NOP'}, # Probably not needed, handled at lower level
# { GOTO:'P:NotRunning'},
{
LBL
:
'P:Offline'
,
ACT
:
'SET_OFFLINE'
},
# set_offline
{
ACT
:
'SCTL_DET_CLEAR'
},
# sctl_det_reset
{
GOTO
:
'P:NotRunning'
},
{
LBL
:
'P:StartBitCleared'
,
ACT
:
'PXCI0_CLEAR'
},
# pxci0_clear
...
...
@@ -180,6 +181,7 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{
LBL
:
'P:StartComm'
,
ACT
:
'SET_STS_7F'
},
# frcv_set_sts_7f
{
ACT
:
'SET_UPDATE_SIG'
},
# #frcv_set_update_sig
{
ACT
:
'XMIT_COMRESET'
},
# Now does it on reset. See if it is possible to transmit COMRESET w/o reset
{
ACT
:
'SCTL_DET_CLEAR'
},
# sctl_det_reset
{
IF
:
'PXSSTS_DET_EQ_1'
,
GOTO
:
'P:StartComm'
},
{
GOTO
:
'P:NotRunning'
},
#New states, because FIS needs to be read in befor R_OK
...
...
@@ -213,15 +215,15 @@ sequence = [{LBL:'POR', ADDR: 0x0, ACT: NOP},
{
LBL
:
'NDR:Accept'
,
ACT
:
'NOP'
},
# ******** # send R_OK after reading in FIS: ACT: 'R_OK'}, # send_R_OK to device
{
IF
:
'NB_ND_D2HR_PIO'
,
GOTO
:
'NDR:IgnoreIdle'
},
# 2 :((FIS == FIS_D2HR) || (FIS == FIS_PIO)) && !PxT
BD.STS.BSY & !PxTB
D.STS.DRQ
{
IF
:
'NB_ND_D2HR_PIO'
,
GOTO
:
'NDR:IgnoreIdle'
},
# 2 :((FIS == FIS_D2HR) || (FIS == FIS_PIO)) && !PxT
FD.STS.BSY & !PxTF
D.STS.DRQ
{
IF
:
'NST_D2HR'
,
GOTO
:
'P:RegFisUpdate'
},
# 3 :!ST && (FIS == FIS_D2HR) TODO: does it mean either BSY or DRQ are 1?
{
IF
:
'NPCMD_FRE'
,
GOTO
:
'NDR:IgnoreNR'
},
# 4 !pcmd_fre (docs: goto P:NotRunning, but we need to clear FIFO)
{
IF
:
'NPCMD_FRE'
,
GOTO
:
'NDR:IgnoreNR'
},
# 4 !p
x
cmd_fre (docs: goto P:NotRunning, but we need to clear FIFO)
{
IF
:
'D2HR'
,
GOTO
:
'RegFIS:Entry'
},
# 5 FIS == FIS_D2HR
{
IF
:
'SDB'
,
GOTO
:
'SDB:Entry'
},
# 7 (# 6 skipped)
{
IF
:
'DMA_ACT'
,
GOTO
:
'DX:EntryIgnore'
},
# 8 FIS == FIS_DMA_ACT
{
IF
:
'DMA_SETUP'
,
GOTO
:
'DmaSet:Entry'
},
# 9 FIS == FIS_DMA_SETUP
{
IF
:
'BIST_ACT_FE'
,
GOTO
:
'BIST:FarEndLoopback'
},
#
10 FIS == FIS_BIST_ACT && |bist_bits TODO:get_ignore to read in FIS
{
IF
:
'BIST_ACT'
,
GOTO
:
'BIST:TestOngoing'
},
# 11 FIS == FIS_BIST_ACT
&& |bist_bits TODO:get_ignore to read in FIS
{
IF
:
'BIST_ACT_FE'
,
GOTO
:
'BIST:FarEndLoopback'
},
#
10 FIS == FIS_BIST_ACT && |bist_bits
{
IF
:
'BIST_ACT'
,
GOTO
:
'BIST:TestOngoing'
},
# 11 FIS == FIS_BIST_ACT
# && !(|bist_bits)
{
IF
:
'PIO_SETUP'
,
GOTO
:
'PIO:Entry'
},
# 12 FIS == FIS_PIO_SETUP
{
GOTO
:
'UFIS:Entry'
},
# 13 Unknown FIS (else)
#5.3.6. Command Transfer State
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment
