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Andrey Filippov authored
module to keep global (Verilog) parameters, self-modified code to include pre-defines fro PyDev to be happy)
e6b5bfc1
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.settings | Loading commit data... | |
.project | ||
.pydevproject | ||
args | ||
hargs | ||
import_verilog_parameters.py | ||
test_mcntrl.py | ||
verilog_utils.py | ||
vrlg.py | ||
x393_axi_control_status.py | ||
x393_mcntrl_adjust.py | ||
x393_mcntrl_buffers.py | ||
x393_mcntrl_tests.py | ||
x393_mcntrl_timing.py | ||
x393_mem.py | ||
x393_pio_sequences.py | ||
x393_utils.py |