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ahci_defaults.vh modified source to include new SATA code (not in the bitstream)
ahci_localparams.vh modified source to include new SATA code (not in the bitstream)
ahci_types.vh added files copied from x393_sata
ahxi_fsm_code.vh added files copied from x393_sata
coring.dat.vh continue debugging
fis_types.vh added files copied from x393_sata
focus_filt.dat.vh continue debugging
huffman.dat.vh continue debugging
linear1028rgb.dat.vh includes to pass initialization parameters to block RAM primitives
quantization_100.dat.vh changed user name to full name
ram18_declare_init.vh Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
ram18_pass_init.vh includes to pass initialization parameters to block RAM primitives
ram36_declare_init.vh Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
ram36_pass_init.vh includes to pass initialization parameters to block RAM primitives
tasks_tests_memory.vh Added interrupts to membridge module
x393_cur_params_simulation.vh renamed current simulation parameters file
x393_cur_params_target.vh fixed phase adjustment
x393_localparams.vh Modified headers to work with doxverilog2.5/doxygen1.7.0
x393_mcontr_encode_cmd.vh changed order of the function defines
x393_parameters.vh adding InertialSense IMS-5 support
x393_simulation_parameters.vh working on boson implementaion, fixed old bug in python code
x393_tasks01.vh Modified headers to work with doxverilog2.5/doxygen1.7.0
x393_tasks_afi.vh Added interrupts to membridge module
x393_tasks_mcntrl_buffers.vh Modified headers to work with doxverilog2.5/doxygen1.7.0
x393_tasks_mcntrl_en_dis_priority.vh Modified headers to work with doxverilog2.5/doxygen1.7.0
x393_tasks_mcntrl_timing.vh Loading commit data...
x393_tasks_pio_sequences.vh Loading commit data...
x393_tasks_ps_pio.vh Loading commit data...
x393_tasks_status.vh Loading commit data...