Name
Last commit
Last update
axi correcting histograms to system memory transfer
cocotb correcting histograms to system memory transfer
compressor_jp last dct branch mods
ddr3 testing and simulating, improving timing
docs Description of the memory controller clocks and programmable delays
dsp working on dtt-iv: dct-iv/dst-iv
eclipse_project_setup changed branched eclipse project name
hardware_tests eye pattern tests at 400MHz
helpers changed user name to full name
includes merged with master
input_data added more simulation images, more fixing of JPEG tail
logger modifying timestamps/triggering
memctrl last dct branch mods
py393 correcting histograms to system memory transfer
sensor correcting histograms to system memory transfer
simulation_data improving sensor_i2c
simulation_modules added more simulation images, more fixing of JPEG tail
timing correcting triggering - there was a false trigger when turning on extrenal trigger condition
unisims_extra Modified headers to work with doxverilog2.5/doxygen1.7.0
unisims_patches patch to work with Icarus Verilog simulator
util_modules disabling SoF for disabled channels
wrap working with cocotb simulation
x393_sata modified source to include new SATA code (not in the bitstream)
.editor_defines working to add cocotb simualtion
.gitignore ignore .settings
INIT_PROJECT Loading commit data...
Makefile Loading commit data...
OSERDESE1.diff Loading commit data...
README.md Loading commit data...
VERSION Loading commit data...
address_map.txt Loading commit data...
copy_x393_sata.sh Loading commit data...
dct_tests_01.sav Loading commit data...
ddrc_test01.xcf Loading commit data...
ddrc_test01.xdc Loading commit data...
ddrc_test01_testbench.sav Loading commit data...
ddrc_test01_timing.xdc Loading commit data...
fpga_version.vh Loading commit data...
glbl.v Loading commit data...
install.sh Loading commit data...
system_defines.vh Loading commit data...
x393.v Loading commit data...
x393.xcf Loading commit data...
x393_1_7_0.Doxyfile Loading commit data...
x393_1_8_2.Doxyfile Loading commit data...
x393_diagram.png Loading commit data...
x393_diagram.svg Loading commit data...
x393_global.tcl Loading commit data...
x393_hispi.bit Loading commit data...
x393_parallel.bit Loading commit data...
x393_placement.tcl Loading commit data...
x393_testbench01.sav Loading commit data...
x393_testbench01.tf Loading commit data...
x393_testbench02.sav Loading commit data...
x393_testbench02.tf Loading commit data...
x393_testbench03.sav Loading commit data...
x393_testbench03.tf Loading commit data...
x393_testbench04.gtkw Loading commit data...
x393_testbench04.sav Loading commit data...
x393_timing.tcl Loading commit data...

x393

x393 Block Diagram

FPGA code for Elphel 393 camera, created with VDT plugin. It runs on Xilinx Zynq 7030 SoC (FPGA plus dual ARM).

Documentation is generated with Doxygen-based Doxverilog.

Run ./INIT_PROJECT in the top directory to copy initial .project and .pydevproject files for Eclipse

Simulation of this project requires some files from the Xilinx proprietary unisims library (list of dependencies is in this blog post). VDT plugin README file describes steps needed after installation of Xilinx software (unisims library is not distributed separately).

Python program used on the target and during Cocotb simulation requires Python numpy module, on Ubuntu you may install it with

sudo apt-get install python-numpy