Name
Last commit
Last update
.eclipse_project_setup updated python paths
.settings re-generated bitfiles
axi moved declarations up to make simulator happy
cocotb bug fixrd in DCT and other places
compressor_jp bug fixrd in DCT and other places
ddr3 testing and simulating, improving timing
docs Description of the memory controller clocks and programmable delays
dsp code formatting
hardware_tests eye pattern tests at 400MHz
helpers changed user name to full name
includes individual camsync timestamp control
input_data changed user name to full name
logger Modified headers to work with doxverilog2.5/doxygen1.7.0
memctrl Made separate control for sesnort histograms, channel enable and bit width
py393 minor cleanup
sensor Added bayer input to histograms, separated bayer, page, en and repet control in gamma modules
simulation_data improving sensor_i2c
simulation_modules bug fixrd in DCT and other places
timing re-generated bitfiles
unisims_extra Modified headers to work with doxverilog2.5/doxygen1.7.0
unisims_patches patch to work with Icarus Verilog simulator
util_modules working with cocotb simulation
wrap working with cocotb simulation
x393_sata Modified headers to work with doxverilog2.5/doxygen1.7.0
.editor_defines working to add cocotb simualtion
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x393

x393 Block Diagram

FPGA code for Elphel 393 camera, created with VDT plugin. It runs on Xilinx Zynq 7030 SoC (FPGA plus dual ARM).

Documentation is generated with Doxygen-based Doxverilog.

Run ./INIT_PROJECT in the top directory to copy initial .project and .pydevproject files for Eclipse

Simulation of this project requires some files from the Xilinx proprietary unisims library (list of dependencies is in this blog post). VDT plugin README file describes steps needed after installation of Xilinx software (unisims library is not distributed separately).

Python program used on the target and during Cocotb simulation requires Python numpy module, on Ubuntu you may install it with

sudo apt-get install python-numpy