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cmd_deser.v working on files realted to sensor channels, added frame sequences to mcntrl_linear_rw.v and mcntrl_tiled_rw.v
dly01_16.v added 16-bit shift register
dly_16.v modifying memory controller buffer interface
fifo_1cycle.v working on synthesis with Vivado tools
fifo_2regs.v testing read memory as rectangular tiles
fifo_cross_clocks.v added configuration for ISE, timing constraints for Vivado
fifo_same_clock.v working on synthesis with Vivado tools
fifo_same_clock_fill.v simulating/debugging
index_max_16.v debugging/simulation
masked_max_reg.v debugging/simulation
mcont_common_chnbuf_reg.v re-organized top structure
mcont_from_chnbuf_reg.v more bugs fixing with simulation
mcont_to_chnbuf_reg.v more debugging by simulation, bug fixing
pri1hot16.v converting eddr3 to the x393 project
pulse_cross_clock.v Working on membridge.v - module to read/write ddr3 in scanline mode over ahi_hp
status_generate.v Fixed handling AXI write responce channel - both in work and simulation modules. Before each word, not burst was responded
status_router16.v started top module for memory controller with channle buffers, added cascaded status multiplexers
status_router2.v working on synthesis with Vivado tools
status_router4.v started top module for memory controller with channle buffers, added cascaded status multiplexers
status_router8.v started top module for memory controller with channle buffers, added cascaded status multiplexers