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.settings testing hardware, adding related code
axi Debugging hardware, added functionality to detect cache-related problems
ddr3 debugging/simulation
docs Description of the memory controller clocks and programmable delays
hardware_tests eye pattern tests at 400MHz
includes Debugging hardware, added functionality to detect cache-related problems
memctrl working on sensor channel
py393 Debugging hardware, added functionality to detect cache-related problems
sensor module to convert 16-bit data to 8 bit using piecewise-linear table conversion
simulation_modules Fixed handling AXI write responce channel - both in work and simulation modules. Before each word, not burst was responded
unisims_patches patch to work with Icarus Verilog simulator
util_modules working on files realted to sensor channels, added frame sequences to mcntrl_linear_rw.v and mcntrl_tiled_rw.v
wrap working on sensor channel
.editor_defines.vh working on synthesis with Vivado tools
.gitignore removed *py393/dbg not to update them ater each re-run
.project Debugging hardware, added functionality to detect cache-related problems
.pydevproject organized new/debug files
OSERDESE1.diff Modifications for Icarus Verilog
README.md added link to vdt-plugin in README.md
address_map.txt before adding extra register layer between channel buffers outputs and memory controller
axi_hp_clk.v Working on membridge.v - module to read/write ddr3 in scanline mode over ahi_hp
cmd_mux.v before adding extra register layer between channel buffers outputs and memory controller
cmd_readback.v working on files realted to sensor channels, added frame sequences to mcntrl_linear_rw.v and mcntrl_tiled_rw.v
ddrc_test01.xcf added configuration for ISE, timing constraints for Vivado
ddrc_test01.xdc troubleshooting lack of DONE during loading of the bitfile
ddrc_test01_testbench.sav Loading commit data...
ddrc_test01_timing.xdc Loading commit data...
glbl.v Loading commit data...
status_read.v Loading commit data...
system_defines.vh Loading commit data...
x393.v Loading commit data...
x393.xcf Loading commit data...
x393.xdc Loading commit data...
x393_testbench01.sav Loading commit data...
x393_testbench01.tf Loading commit data...
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