Name
Last commit
Last update
.eclipse_project_setup updated working set
.settings added hardwired option for x393_cur_params_target.vh
axi Modified headers to work with doxverilog2.5/doxygen1.7.0
compressor_jp minor formatting
ddr3 testing and simulating, improving timing
docs Description of the memory controller clocks and programmable delays
dsp Switched to new implementation of 8x8 DCT, generated documentation
hardware_tests eye pattern tests at 400MHz
helpers changed user name to full name
includes changed order of the function defines
input_data changed user name to full name
logger Modified headers to work with doxverilog2.5/doxygen1.7.0
memctrl Modified headers to work with doxverilog2.5/doxygen1.7.0
py393 Switched to new implementation of 8x8 DCT, generated documentation
sensor Modified headers to work with doxverilog2.5/doxygen1.7.0
simulation_data improving sensor_i2c
simulation_modules Modified headers to work with doxverilog2.5/doxygen1.7.0
timing Modified headers to work with doxverilog2.5/doxygen1.7.0
unisims_extra Modified headers to work with doxverilog2.5/doxygen1.7.0
unisims_patches patch to work with Icarus Verilog simulator
util_modules moved modules from the top directory to util_modules
wrap Modified headers to work with doxverilog2.5/doxygen1.7.0
x393_sata Modified headers to work with doxverilog2.5/doxygen1.7.0
.editor_defines copied CVC-related changes from master branch
.gitignore Switched to new implementation of 8x8 DCT, generated documentation
INIT_PROJECT Loading commit data...
OSERDESE1.diff Loading commit data...
README.md Loading commit data...
address_map.txt Loading commit data...
copy_x393_sata.sh Loading commit data...
ddrc_test01.xcf Loading commit data...
ddrc_test01.xdc Loading commit data...
ddrc_test01_testbench.sav Loading commit data...
ddrc_test01_timing.xdc Loading commit data...
fpga_version.vh Loading commit data...
glbl.v Loading commit data...
install.sh Loading commit data...
system_defines.vh Loading commit data...
x393.v Loading commit data...
x393.xcf Loading commit data...
x393_1_7_0.Doxyfile Loading commit data...
x393_global.tcl Loading commit data...
x393_hispi.bit Loading commit data...
x393_parallel.bit Loading commit data...
x393_placement.tcl Loading commit data...
x393_testbench01.sav Loading commit data...
x393_testbench01.tf Loading commit data...
x393_testbench02.sav Loading commit data...
x393_testbench02.tf Loading commit data...
x393_testbench03.sav Loading commit data...
x393_testbench03.tf Loading commit data...
x393_testbench04.gtkw Loading commit data...
x393_testbench04.sav Loading commit data...
x393_timing.tcl Loading commit data...

x393

FPGA code for Elphel 393 camera, created with VDT plugin

Documentation is generated with Doxygen-based Doxverilog. Unfortunately this program does not yet support 'generate' Verilog operators so some important dependencies are missing, like compressor393 module has generated instances of jp_channel that are not shown.

We believe it is still useful, you can get descriptions of the project files.

Run ./INIT_PROJECT in the top directory to copy initial .project and .pydevproject files for Eclipse