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phy Modified write module to support variable 'sel' input, adjustedg hardware to simulation timing
cmd_encod_4mux.v working on synthesis with Vivado tools
cmd_encod_linear_mux.v working on synthesis with Vivado tools
cmd_encod_linear_rd.v bug fixes in Verilog code
cmd_encod_linear_rw.v bug fixes in Verilog code
cmd_encod_linear_wr.v Modified write module to support variable 'sel' input, adjustedg hardware to simulation timing
cmd_encod_tiled_32_rd.v bug fixes in Verilog code
cmd_encod_tiled_32_rw.v bug fixes in Verilog code
cmd_encod_tiled_32_wr.v Modified write module to support variable 'sel' input, adjustedg hardware to simulation timing
cmd_encod_tiled_mux.v bug fixes in Verilog code
cmd_encod_tiled_rd.v bug fixes in Verilog code
cmd_encod_tiled_rw.v bug fixes in Verilog code
cmd_encod_tiled_wr.v Modified write module to support variable 'sel' input, adjustedg hardware to simulation timing
ddr_refresh.v continue on initial x393 with a memory controller
mcntrl393.v connecting new modules for membridge to top module and test fixture
mcntrl393_test01.v re-organized top structure
mcntrl_1kx32r.v debugging, more corrections, tested write levelling/buffer reading
mcntrl_1kx32w.v debugging, more corrections, tested write levelling/buffer reading
mcntrl_buf_rd.v converted channel buffers to configurable width
mcntrl_buf_wr.v converted channel buffers to configurable width
mcntrl_linear_rw.v Working on membridge.v - module to read/write ddr3 in scanline mode over ahi_hp
mcntrl_ps_pio.v converted channel buffers to configurable width
mcntrl_tiled_rw.v working on synthesis with Vivado tools
memctrl16.v creating Python program to pass Verilog parameters to Python FPGA tests
scheduler16.v working on synthesis with Vivado tools