Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
X
x393
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
Elphel
x393
Repository
445798f890d6e0b81a0777fb34a0f8d9dc472df1
Switch branch/tag
x393
includes
History
Find file
Select Archive Format
Source code
Download zip
Download tar.gz
Download tar.bz2
Download tar
ROM contents
· 83f0444a
Andrey Filippov
authored
7 years ago
83f0444a
Name
Last commit
Last update
..
ahci_defaults.vh
modified source to include new SATA code (not in the bitstream)
7 years ago
ahci_localparams.vh
modified source to include new SATA code (not in the bitstream)
7 years ago
ahci_types.vh
added files copied from x393_sata
9 years ago
ahxi_fsm_code.vh
added files copied from x393_sata
9 years ago
coring.dat.vh
continue debugging
9 years ago
fis_types.vh
added files copied from x393_sata
9 years ago
focus_filt.dat.vh
continue debugging
9 years ago
huffman.dat.vh
continue debugging
9 years ago
linear1028rgb.dat.vh
includes to pass initialization parameters to block RAM primitives
9 years ago
mclt_fold_rom.vh
ROM data and Python generator for MCLT fold data
7 years ago
mclt_rotator_rom.vh
ROM contents
7 years ago
mclt_wnd_mul.vh
MCLT window generators - with(128:1)/without(4:1) multiplier, ROM data
7 years ago
mclt_wnd_sres4.vh
MCLT window generators - with(128:1)/without(4:1) multiplier, ROM data
7 years ago
quantization_100.dat.vh
changed user name to full name
8 years ago
ram18_declare_init.vh
Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
9 years ago
ram18_pass_init.vh
includes to pass initialization parameters to block RAM primitives
9 years ago
ram36_declare_init.vh
Finished simulation/testing of a single-channel acquisition/processing/compression, fixed problems with Xilinx tools to pass sythesis/implementation
9 years ago
ram36_pass_init.vh
includes to pass initialization parameters to block RAM primitives
9 years ago
tasks_tests_memory.vh
Added interrupts to membridge module
8 years ago
x393_cur_params_simulation.vh
renamed current simulation parameters file
8 years ago
x393_cur_params_target.vh
Modified headers to work with doxverilog2.5/doxygen1.7.0
8 years ago
x393_localparams.vh
Modified headers to work with doxverilog2.5/doxygen1.7.0
8 years ago
x393_mcontr_encode_cmd.vh
changed order of the function defines
8 years ago
x393_parameters.vh
last dct branch mods
7 years ago
x393_simulation_parameters.vh
added more simulation images, more fixing of JPEG tail
8 years ago
x393_tasks01.vh
Loading commit data...
x393_tasks_afi.vh
Loading commit data...
x393_tasks_mcntrl_buffers.vh
Loading commit data...
x393_tasks_mcntrl_en_dis_priority.vh
Loading commit data...
x393_tasks_mcntrl_timing.vh
Loading commit data...
x393_tasks_pio_sequences.vh
Loading commit data...
x393_tasks_ps_pio.vh
Loading commit data...
x393_tasks_status.vh
Loading commit data...