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Andrey Filippov authored
finalized DQS input delay vs clock phase adjustment, combined all current results together as a function of the clock phase
1417d17e
finalized DQS input delay vs clock phase adjustment, combined all current results together as a function of the clock phase
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args | Loading commit data... | |
get_test_dq_dqs_data.py | Loading commit data... | |
hargs | Loading commit data... | |
import_verilog_parameters.py | Loading commit data... | |
test_mcntrl.py | Loading commit data... | |
verilog_utils.py | Loading commit data... | |
vrlg.py | Loading commit data... | |
x393_axi_control_status.py | Loading commit data... | |
x393_lma.py | Loading commit data... | |
x393_mcntrl_adjust.py | Loading commit data... | |
x393_mcntrl_buffers.py | Loading commit data... | |
x393_mcntrl_tests.py | Loading commit data... | |
x393_mcntrl_timing.py | Loading commit data... | |
x393_mem.py | Loading commit data... | |
x393_pio_sequences.py | Loading commit data... | |
x393_utils.py | Loading commit data... |