Programming languages used in this repository
-
Verilog
56.25 %
-
Python
29.11 %
-
HCL
7.27 %
-
SystemVerilog
6.82 %
-
Tcl
0.3 %
Commit statistics for fcb4d602f0787d6179f23982fd0cad094a27db6f Apr 26 - Dec 31
- Total: 791 commits
- Average per day: 0.6 commits
- Authors: 5
Commits per day of month
Commits per weekday
Commits per day hour (UTC)