Programming languages used in this repository
-
Verilog
56.25 %
-
Python
29.11 %
-
HCL
7.27 %
-
SystemVerilog
6.82 %
-
Tcl
0.3 %
Commit statistics for 86ec82ad3944e3d4b1e8e2782713e53048ec7dfa Apr 26 - Jul 20
- Total: 592 commits
- Average per day: 0.7 commits
- Authors: 5
Commits per day of month
Commits per weekday
Commits per day hour (UTC)