Programming languages used in this repository
-
Verilog
56.25 %
-
Python
29.11 %
-
HCL
7.27 %
-
SystemVerilog
6.82 %
-
Tcl
0.3 %
Commit statistics for 35cce7c8a7f7b3311a9ce1042a60bbed455b7095 Apr 26 - Aug 03
- Total: 609 commits
- Average per day: 0.7 commits
- Authors: 5
Commits per day of month
Commits per weekday
Commits per day hour (UTC)