adding measurement of DQ_ODELAY vs DQS_ODELAY (fbf5fddb) · Commits · Elphel / x393

py393/x393_lma.py

+19 −19

py393/x393_mcntrl_adjust.py

+577 −18

File changed.

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py393/x393_mcntrl_buffers.py

+3 −3

Original line number	Original line	Diff line number	Diff line
	@@ -135,9 +135,9 @@ class X393McntrlBuffers(object):
	num_words_or_data_list): # input integer num_words; # number of words to write (will be rounded up to multiple of 16)		num_words_or_data_list): # input integer num_words; # number of words to write (will be rounded up to multiple of 16)
	"""		"""
	Fill specified buffer with the pattern data		Fill specified buffer with the pattern data
	<chn> 4-bit buffer channel (0..4) to write data to		@param chn 4-bit buffer channel (0..4) to write data to
	<page> 2-bit buffer page to write to		@param page 2-bit buffer page to write to
	<num_words_or_data_list> number of 32-bit words to generate/write or a list with integer data		@param num_words_or_data_list> number of 32-bit words to generate/write or a list with integer data
	"""		"""
	print("===write_block_buf_chn() chn=0x%x, page=0x%x"%(chn,page), end=" ")		print("===write_block_buf_chn() chn=0x%x, page=0x%x"%(chn,page), end=" ")
	if isinstance (num_words_or_data_list,list):		if isinstance (num_words_or_data_list,list):

py393/x393_mcntrl_tests.py

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -283,7 +283,7 @@ class X393McntrlTests(object):
	self.x393_mcntrl_timing.axi_set_dq_odelay(dq_odelay)		self.x393_mcntrl_timing.axi_set_dq_odelay(dq_odelay)
	if (not dqs_odelay is None) and (dqs_odelay != []):		if (not dqs_odelay is None) and (dqs_odelay != []):
	self.x393_mcntrl_timing.axi_set_dqs_odelay(dqs_odelay)		self.x393_mcntrl_timing.axi_set_dqs_odelay(dqs_odelay)
	return self.x393_pio_sequences.write_block(wait_complete) # Wait for operation to complete		return self.x393_pio_sequences.write_block(0,wait_complete) # Wait for operation to complete

	def test_read_block(self,		def test_read_block(self,
	dq_idelay=None,		dq_idelay=None,

py393/x393_mcntrl_timing.py

+26 −23

Original line number	Original line	Diff line number	Diff line
	@@ -82,7 +82,7 @@ class X393McntrlTiming(object):
	<phase> 8-bit clock phase value (None will use default)		<phase> 8-bit clock phase value (None will use default)
	<wait_phase_en> compare phase shift to programmed (will not work if the program was restarted)		<wait_phase_en> compare phase shift to programmed (will not work if the program was restarted)
	<wait_seq> read and re-send status request to make sure status reflects new data (just for testing, too fast for Python)		<wait_seq> read and re-send status request to make sure status reflects new data (just for testing, too fast for Python)
	<quiet> reduce output		@param quiet reduce output
	Returns 1 if success, 0 if timeout (or no wait was performed)		Returns 1 if success, 0 if timeout (or no wait was performed)
	"""		"""
	if phase is None:		if phase is None:
	@@ -182,10 +182,10 @@ class X393McntrlTiming(object):
	quiet=1):		quiet=1):
	"""		"""
	Set all DQ input delays to the same value		Set all DQ input delays to the same value
	<delay> 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)		@param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
	Each of the two elements in the delay tuple/list may be a a common integer or a list/tuple itself		Each of the two elements in the delay tuple/list may be a a common integer or a list/tuple itself
	if delay is None will restore default values		if delay is None will restore default values
	<quiet> reduce output		@param quiet reduce output
	"""		"""
	# print("====axi_set_dq_idelay %s"%str(delay))		# print("====axi_set_dq_idelay %s"%str(delay))

	@@ -203,12 +203,15 @@ class X393McntrlTiming(object):
	self.x393_axi_tasks.write_contol_register (vrlg.DLY_SET,0);# // set all delays		self.x393_axi_tasks.write_contol_register (vrlg.DLY_SET,0);# // set all delays

	def axi_set_dq_odelay(self,		def axi_set_dq_odelay(self,
	delay=None): # input [7:0] delay;		delay=None, # input [7:0] delay;
			quiet=1):

	"""		"""
	Set all DQ OUTput delays to the same value		Set all DQ OUTput delays to the same value
	<delay> 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)		@param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
	Each of the two elements in the delay tuple/list may be a a common integer or a list/tuple itself		Each of the two elements in the delay tuple/list may be a a common integer or a list/tuple itself
	if delay is None will restore default values		if delay is None will restore default values
			@param quiet reduce output
	"""		"""
	if delay is None:		if delay is None:
	delay=[[],[]]		delay=[[],[]]
	@@ -217,7 +220,7 @@ class X393McntrlTiming(object):
	delay[1].append(vrlg.get_default_field("DLY_LANE1_ODELAY",i))		delay[1].append(vrlg.get_default_field("DLY_LANE1_ODELAY",i))
	if isinstance(delay,(int,long)):		if isinstance(delay,(int,long)):
	delay=(delay,delay)		delay=(delay,delay)
	if self.DEBUG_MODE > 1:		if quiet < 2:
	print("SET DQ ODELAY="+hexMultiple(delay)) # hexMultiple		print("SET DQ ODELAY="+hexMultiple(delay)) # hexMultiple
	self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_ODELAY, 0, 8, delay[0], "DLY_LANE0_ODELAY");		self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_ODELAY, 0, 8, delay[0], "DLY_LANE0_ODELAY");
	self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_ODELAY, 0, 8, delay[1], "DLY_LANE1_ODELAY");		self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_ODELAY, 0, 8, delay[1], "DLY_LANE1_ODELAY");
	@@ -228,9 +231,9 @@ class X393McntrlTiming(object):
	quiet=1):		quiet=1):
	"""		"""
	Set all DQs input delays to the same value		Set all DQs input delays to the same value
	<delay> 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)		@param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
	if delay is None will restore default values		if delay is None will restore default values
	<quiet> reduce output		@param quiet reduce output
	"""		"""
	if delay is None:		if delay is None:
	delay=(vrlg.get_default_field("DLY_LANE0_IDELAY",8),vrlg.get_default_field("DLY_LANE1_IDELAY",8))		delay=(vrlg.get_default_field("DLY_LANE0_IDELAY",8),vrlg.get_default_field("DLY_LANE1_IDELAY",8))
	@@ -247,9 +250,9 @@ class X393McntrlTiming(object):
	quiet=1):		quiet=1):
	"""		"""
	Set all DQs OUTput delays to the same value		Set all DQs OUTput delays to the same value
	<delay> 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)		@param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
	if delay is None will restore default values		if delay is None will restore default values
	<quiet> reduce output		@param quiet reduce output

	"""		"""
	if delay is None:		if delay is None:
	@@ -267,9 +270,9 @@ class X393McntrlTiming(object):
	quiet=1):		quiet=1):
	"""		"""
	Set all DM output delays to the same value		Set all DM output delays to the same value
	<delay> 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)		@param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
	if delay is None will restore default values		if delay is None will restore default values
	<quiet> reduce output		@param quiet reduce output
	"""		"""
	if delay is None:		if delay is None:
	delay=(vrlg.get_default_field("DLY_LANE0_ODELAY",9),vrlg.get_default_field("DLY_LANE1_ODELAY",9))		delay=(vrlg.get_default_field("DLY_LANE0_ODELAY",9),vrlg.get_default_field("DLY_LANE1_ODELAY",9))
	@@ -287,11 +290,11 @@ class X393McntrlTiming(object):
	quiet=1):		quiet=1):
	"""		"""
	Set all command/address output delays to the same value (or a list/tuple of the individual ones)		Set all command/address output delays to the same value (or a list/tuple of the individual ones)
	<delay> 8-bit (5+3) delay value to use or list/tuple containing individual values		@param delay 8-bit (5+3) delay value to use or list/tuple containing individual values
	List elements may be None, those values will not be overwritten		List elements may be None, those values will not be overwritten
	if delay is None will restore default values		if delay is None will restore default values
	<indx> if present, delay only applies to the specified index (delay should be int/long)		@param indx if present, delay only applies to the specified index (delay should be int/long)
	<quiet> reduce output		@param quiet reduce output
	"""		"""
	if delay is None:		if delay is None:
	delay=[]		delay=[]
	@@ -317,10 +320,10 @@ class X393McntrlTiming(object):
	quiet=1):		quiet=1):
	"""		"""
	Set output delays for address lines only		Set output delays for address lines only
	<delay> 8-bit (5+3) delay value to use or list/tuple containing individual values		@param delay 8-bit (5+3) delay value to use or list/tuple containing individual values
	List elements may be None, those values will not be overwritten		List elements may be None, those values will not be overwritten
	if delay is None will restore default values		if delay is None will restore default values
	<indx> if present, delay only applies to the specified index (delay should be int/long)		@param indx if present, delay only applies to the specified index (delay should be int/long)
	"""		"""
	if delay is None:		if delay is None:
	delay=[]		delay=[]
	@@ -345,10 +348,10 @@ class X393McntrlTiming(object):
	indx=None): # address index		indx=None): # address index
	"""		"""
	Set output delays for bank lines only		Set output delays for bank lines only
	<delay> 8-bit (5+3) delay value to use or list/tuple containing individual values		@param delay 8-bit (5+3) delay value to use or list/tuple containing individual values
	List elements may be None, those values will not be overwritten		List elements may be None, those values will not be overwritten
	if delay is None will restore default values		if delay is None will restore default values
	<indx> if present, delay only applies to the specified index (delay should be int/long)		@param indx if present, delay only applies to the specified index (delay should be int/long)
	"""		"""
	bank_offset=24		bank_offset=24
	if delay is None:		if delay is None:
	@@ -374,10 +377,10 @@ class X393McntrlTiming(object):
	indx=None): # address index		indx=None): # address index
	"""		"""
	Set output delays for command lines only. command=(we,ras,cas,cke,odt)		Set output delays for command lines only. command=(we,ras,cas,cke,odt)
	<delay> 8-bit (5+3) delay value to use or list/tuple containing individual values		@param delay 8-bit (5+3) delay value to use or list/tuple containing individual values
	List elements may be None, those values will not be overwritten		List elements may be None, those values will not be overwritten
	if delay is None will restore default values		if delay is None will restore default values
	<indx> if present, delay only applies to the specified index (delay should be int/long)		@param indx if present, delay only applies to the specified index (delay should be int/long)
	"""		"""
	command_offset=24+3		command_offset=24+3
	if delay is None:		if delay is None:
	@@ -410,7 +413,7 @@ class X393McntrlTiming(object):
	<reg_addr> control register address of the first register in the range		<reg_addr> control register address of the first register in the range
	<offset> add this offset to address		<offset> add this offset to address
	<number> number of registers to write		<number> number of registers to write
	<delay> 8-bit (5+3) delay value to use or list/tuple containing individual values		@param delay 8-bit (5+3) delay value to use or list/tuple containing individual values
	List elements may be None, those values will not be overwritten		List elements may be None, those values will not be overwritten
	<vname> Verilog parameter name		<vname> Verilog parameter name
	"""		"""
	@@ -439,7 +442,7 @@ class X393McntrlTiming(object):
	delay=None): # input [3:0] delay;		delay=None): # input [3:0] delay;
	"""		"""
	Set write to buffer latency		Set write to buffer latency
	<delay> 4-bit write to buffer signal delay (in mclk clock cycles)		@param delay 4-bit write to buffer signal delay (in mclk clock cycles)
	if delay is None will restore default values		if delay is None will restore default values
	"""		"""
	if delay is None:		if delay is None:

Original line number	Original line	Diff line number	Diff line
	@@ -166,7 +166,7 @@ class X393LMA(object):
	use np.nan instead of the None data		use np.nan instead of the None data
	np.isnan() test		np.isnan() test
	, dtype=np.float		, dtype=np.float
	@compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,		@param compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,
	save None for fraction in unknown (previous -0.5, next +0.5)		save None for fraction in unknown (previous -0.5, next +0.5)
	"""		"""
	halfStep=0.5		halfStep=0.5
	@@ -546,15 +546,15 @@ class X393LMA(object):
	each of 2x2 elements (DQ delay values) or null		each of 2x2 elements (DQ delay values) or null
	Create data set template - for each DQS delay and inPhase		Create data set template - for each DQS delay and inPhase
	- branch - number of full periods to add		- branch - number of full periods to add
	@lane byte lane to process		@param lane byte lane to process
	@bin_size bin size for the histograms (should be 5/10/20/40)		@param bin_size bin size for the histograms (should be 5/10/20/40)
	@clk_period SDCLK period in ps		@param clk_period SDCLK period in ps
	@dly_step_ds IDELAY step (from the datasheet)		@param dly_step_ds IDELAY step (from the datasheet)
	@primary_set which of the data edge series to use as leading (other will be trailing by 180)		@param primary_set which of the data edge series to use as leading (other will be trailing by 180)
	@data_set measured data set		@param data_set measured data set
	@compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,		@param compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,
	save None for fraction in unknown (previous -0.5, next +0.5)		save None for fraction in unknown (previous -0.5, next +0.5)
	@quiet reduce output		@param quiet reduce output
	"""		"""
	num_hist_steps=2*((DLY_STEPS+bin_size-1)//bin_size)		num_hist_steps=2*((DLY_STEPS+bin_size-1)//bin_size)

	@@ -756,7 +756,7 @@ class X393LMA(object):
	hist_estimated,		hist_estimated,
	quiet=1):		quiet=1):
	"""		"""
	@compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,		@param compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,
	save None for fraction in unknown (previous -0.5, next +0.5)		save None for fraction in unknown (previous -0.5, next +0.5)

	"""		"""
	@@ -864,16 +864,16 @@ class X393LMA(object):
	After initial parametersn are created - run LMA to find optimal ones,		After initial parametersn are created - run LMA to find optimal ones,
	then return up to 3 varints (early, nominal, late) providing the best		then return up to 3 varints (early, nominal, late) providing the best
	DQ input delay for each DQS one		DQ input delay for each DQS one
	@lane byte lane to process (or non-number - process all byte lanes of the device)		@param lane byte lane to process (or non-number - process all byte lanes of the device)
	@bin_size bin size for the histograms (should be 5/10/20/40)		@param bin_size bin size for the histograms (should be 5/10/20/40)
	@clk_period SDCLK period in ps		@param clk_period SDCLK period in ps
	@dly_step_ds IDELAY step (from the datasheet)		@param dly_step_ds IDELAY step (from the datasheet)

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