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Commit fbf5fddb authored by Andrey Filippov's avatar Andrey Filippov
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adding measurement of DQ_ODELAY vs DQS_ODELAY

parent 1417d17e
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Showing with 664 additions and 92 deletions
py393/x393_lma.py
View file @ fbf5fddb
...@@ -166,7 +166,7 @@ class X393LMA(object): ...@@ -166,7 +166,7 @@ class X393LMA(object):
use np.nan instead of the None data use np.nan instead of the None data
np.isnan() test np.isnan() test
, dtype=np.float , dtype=np.float
@compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step, @param compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,
save None for fraction in unknown (previous -0.5, next +0.5) save None for fraction in unknown (previous -0.5, next +0.5)
""" """
halfStep=0.5 halfStep=0.5
...@@ -546,15 +546,15 @@ class X393LMA(object): ...@@ -546,15 +546,15 @@ class X393LMA(object):
each of 2x2 elements (DQ delay values) or null each of 2x2 elements (DQ delay values) or null
Create data set template - for each DQS delay and inPhase Create data set template - for each DQS delay and inPhase
- branch - number of full periods to add - branch - number of full periods to add
@lane byte lane to process @param lane byte lane to process
@bin_size bin size for the histograms (should be 5/10/20/40) @param bin_size bin size for the histograms (should be 5/10/20/40)
@clk_period SDCLK period in ps @param clk_period SDCLK period in ps
@dly_step_ds IDELAY step (from the datasheet) @param dly_step_ds IDELAY step (from the datasheet)
@primary_set which of the data edge series to use as leading (other will be trailing by 180) @param primary_set which of the data edge series to use as leading (other will be trailing by 180)
@data_set measured data set @param data_set measured data set
@compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step, @param compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,
save None for fraction in unknown (previous -0.5, next +0.5) save None for fraction in unknown (previous -0.5, next +0.5)
@quiet reduce output @param quiet reduce output
""" """
num_hist_steps=2*((DLY_STEPS+bin_size-1)//bin_size) num_hist_steps=2*((DLY_STEPS+bin_size-1)//bin_size)
...@@ -756,7 +756,7 @@ class X393LMA(object): ...@@ -756,7 +756,7 @@ class X393LMA(object):
hist_estimated, hist_estimated,
quiet=1): quiet=1):
""" """
@compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step, @param compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,
save None for fraction in unknown (previous -0.5, next +0.5) save None for fraction in unknown (previous -0.5, next +0.5)
""" """
...@@ -864,16 +864,16 @@ class X393LMA(object): ...@@ -864,16 +864,16 @@ class X393LMA(object):
After initial parametersn are created - run LMA to find optimal ones, After initial parametersn are created - run LMA to find optimal ones,
then return up to 3 varints (early, nominal, late) providing the best then return up to 3 varints (early, nominal, late) providing the best
DQ input delay for each DQS one DQ input delay for each DQS one
@lane byte lane to process (or non-number - process all byte lanes of the device) @param lane byte lane to process (or non-number - process all byte lanes of the device)
@bin_size bin size for the histograms (should be 5/10/20/40) @param bin_size bin size for the histograms (should be 5/10/20/40)
@clk_period SDCLK period in ps @param clk_period SDCLK period in ps
@dly_step_ds IDELAY step (from the datasheet) @param dly_step_ds IDELAY step (from the datasheet)
@primary_set which of the data edge series to use as leading (other will be trailing by 180) @param primary_set which of the data edge series to use as leading (other will be trailing by 180)
@data_set measured data set @param data_set measured data set
@compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step, @param compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,
save None for fraction in unknown (previous -0.5, next +0.5) save None for fraction in unknown (previous -0.5, next +0.5)
@scale_w weight for "uncertain" values (where samples chane from all 0 to all 1 in one step) @param scale_w weight for "uncertain" values (where samples chane from all 0 to all 1 in one step)
@quiet reduce output @param quiet reduce output
@return 3-element dictionary of ('early','nominal','late'), each being None or a 160-element list, @return 3-element dictionary of ('early','nominal','late'), each being None or a 160-element list,
each element being either None, or a list of 3 best DQ delay values for the DQS delay (some mey be None too) each element being either None, or a list of 3 best DQ delay values for the DQS delay (some mey be None too)
""" """
......
py393/x393_mcntrl_adjust.py
View file @ fbf5fddb
This diff is collapsed.
py393/x393_mcntrl_buffers.py
View file @ fbf5fddb
...@@ -135,9 +135,9 @@ class X393McntrlBuffers(object): ...@@ -135,9 +135,9 @@ class X393McntrlBuffers(object):
num_words_or_data_list): # input integer num_words; # number of words to write (will be rounded up to multiple of 16) num_words_or_data_list): # input integer num_words; # number of words to write (will be rounded up to multiple of 16)
""" """
Fill specified buffer with the pattern data Fill specified buffer with the pattern data
<chn> 4-bit buffer channel (0..4) to write data to @param chn 4-bit buffer channel (0..4) to write data to
<page> 2-bit buffer page to write to @param page 2-bit buffer page to write to
<num_words_or_data_list> number of 32-bit words to generate/write or a list with integer data @param num_words_or_data_list> number of 32-bit words to generate/write or a list with integer data
""" """
print("===write_block_buf_chn() chn=0x%x, page=0x%x"%(chn,page), end=" ") print("===write_block_buf_chn() chn=0x%x, page=0x%x"%(chn,page), end=" ")
if isinstance (num_words_or_data_list,list): if isinstance (num_words_or_data_list,list):
......
py393/x393_mcntrl_tests.py
View file @ fbf5fddb
...@@ -283,7 +283,7 @@ class X393McntrlTests(object): ...@@ -283,7 +283,7 @@ class X393McntrlTests(object):
self.x393_mcntrl_timing.axi_set_dq_odelay(dq_odelay) self.x393_mcntrl_timing.axi_set_dq_odelay(dq_odelay)
if (not dqs_odelay is None) and (dqs_odelay != []): if (not dqs_odelay is None) and (dqs_odelay != []):
self.x393_mcntrl_timing.axi_set_dqs_odelay(dqs_odelay) self.x393_mcntrl_timing.axi_set_dqs_odelay(dqs_odelay)
return self.x393_pio_sequences.write_block(wait_complete) # Wait for operation to complete return self.x393_pio_sequences.write_block(0,wait_complete) # Wait for operation to complete
def test_read_block(self, def test_read_block(self,
dq_idelay=None, dq_idelay=None,
......
py393/x393_mcntrl_timing.py
View file @ fbf5fddb
...@@ -82,7 +82,7 @@ class X393McntrlTiming(object): ...@@ -82,7 +82,7 @@ class X393McntrlTiming(object):
<phase> 8-bit clock phase value (None will use default) <phase> 8-bit clock phase value (None will use default)
<wait_phase_en> compare phase shift to programmed (will not work if the program was restarted) <wait_phase_en> compare phase shift to programmed (will not work if the program was restarted)
<wait_seq> read and re-send status request to make sure status reflects new data (just for testing, too fast for Python) <wait_seq> read and re-send status request to make sure status reflects new data (just for testing, too fast for Python)
<quiet> reduce output @param quiet reduce output
Returns 1 if success, 0 if timeout (or no wait was performed) Returns 1 if success, 0 if timeout (or no wait was performed)
""" """
if phase is None: if phase is None:
...@@ -182,10 +182,10 @@ class X393McntrlTiming(object): ...@@ -182,10 +182,10 @@ class X393McntrlTiming(object):
quiet=1): quiet=1):
""" """
Set all DQ input delays to the same value Set all DQ input delays to the same value
<delay> 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1) @param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
Each of the two elements in the delay tuple/list may be a a common integer or a list/tuple itself Each of the two elements in the delay tuple/list may be a a common integer or a list/tuple itself
if delay is None will restore default values if delay is None will restore default values
<quiet> reduce output @param quiet reduce output
""" """
# print("====axi_set_dq_idelay %s"%str(delay)) # print("====axi_set_dq_idelay %s"%str(delay))
...@@ -203,12 +203,15 @@ class X393McntrlTiming(object): ...@@ -203,12 +203,15 @@ class X393McntrlTiming(object):
self.x393_axi_tasks.write_contol_register (vrlg.DLY_SET,0);# // set all delays self.x393_axi_tasks.write_contol_register (vrlg.DLY_SET,0);# // set all delays
def axi_set_dq_odelay(self, def axi_set_dq_odelay(self,
delay=None): # input [7:0] delay; delay=None, # input [7:0] delay;
quiet=1):
""" """
Set all DQ OUTput delays to the same value Set all DQ OUTput delays to the same value
<delay> 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1) @param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
Each of the two elements in the delay tuple/list may be a a common integer or a list/tuple itself Each of the two elements in the delay tuple/list may be a a common integer or a list/tuple itself
if delay is None will restore default values if delay is None will restore default values
@param quiet reduce output
""" """
if delay is None: if delay is None:
delay=[[],[]] delay=[[],[]]
...@@ -217,7 +220,7 @@ class X393McntrlTiming(object): ...@@ -217,7 +220,7 @@ class X393McntrlTiming(object):
delay[1].append(vrlg.get_default_field("DLY_LANE1_ODELAY",i)) delay[1].append(vrlg.get_default_field("DLY_LANE1_ODELAY",i))
if isinstance(delay,(int,long)): if isinstance(delay,(int,long)):
delay=(delay,delay) delay=(delay,delay)
if self.DEBUG_MODE > 1: if quiet < 2:
print("SET DQ ODELAY="+hexMultiple(delay)) # hexMultiple print("SET DQ ODELAY="+hexMultiple(delay)) # hexMultiple
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_ODELAY, 0, 8, delay[0], "DLY_LANE0_ODELAY"); self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_ODELAY, 0, 8, delay[0], "DLY_LANE0_ODELAY");
self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_ODELAY, 0, 8, delay[1], "DLY_LANE1_ODELAY"); self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_ODELAY, 0, 8, delay[1], "DLY_LANE1_ODELAY");
...@@ -228,9 +231,9 @@ class X393McntrlTiming(object): ...@@ -228,9 +231,9 @@ class X393McntrlTiming(object):
quiet=1): quiet=1):
""" """
Set all DQs input delays to the same value Set all DQs input delays to the same value
<delay> 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1) @param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
if delay is None will restore default values if delay is None will restore default values
<quiet> reduce output @param quiet reduce output
""" """
if delay is None: if delay is None:
delay=(vrlg.get_default_field("DLY_LANE0_IDELAY",8),vrlg.get_default_field("DLY_LANE1_IDELAY",8)) delay=(vrlg.get_default_field("DLY_LANE0_IDELAY",8),vrlg.get_default_field("DLY_LANE1_IDELAY",8))
...@@ -247,9 +250,9 @@ class X393McntrlTiming(object): ...@@ -247,9 +250,9 @@ class X393McntrlTiming(object):
quiet=1): quiet=1):
""" """
Set all DQs OUTput delays to the same value Set all DQs OUTput delays to the same value
<delay> 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1) @param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
if delay is None will restore default values if delay is None will restore default values
<quiet> reduce output @param quiet reduce output
""" """
if delay is None: if delay is None:
...@@ -267,9 +270,9 @@ class X393McntrlTiming(object): ...@@ -267,9 +270,9 @@ class X393McntrlTiming(object):
quiet=1): quiet=1):
""" """
Set all DM output delays to the same value Set all DM output delays to the same value
<delay> 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1) @param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
if delay is None will restore default values if delay is None will restore default values
<quiet> reduce output @param quiet reduce output
""" """
if delay is None: if delay is None:
delay=(vrlg.get_default_field("DLY_LANE0_ODELAY",9),vrlg.get_default_field("DLY_LANE1_ODELAY",9)) delay=(vrlg.get_default_field("DLY_LANE0_ODELAY",9),vrlg.get_default_field("DLY_LANE1_ODELAY",9))
...@@ -287,11 +290,11 @@ class X393McntrlTiming(object): ...@@ -287,11 +290,11 @@ class X393McntrlTiming(object):
quiet=1): quiet=1):
""" """
Set all command/address output delays to the same value (or a list/tuple of the individual ones) Set all command/address output delays to the same value (or a list/tuple of the individual ones)
<delay> 8-bit (5+3) delay value to use or list/tuple containing individual values @param delay 8-bit (5+3) delay value to use or list/tuple containing individual values
List elements may be None, those values will not be overwritten List elements may be None, those values will not be overwritten
if delay is None will restore default values if delay is None will restore default values
<indx> if present, delay only applies to the specified index (delay should be int/long) @param indx if present, delay only applies to the specified index (delay should be int/long)
<quiet> reduce output @param quiet reduce output
""" """
if delay is None: if delay is None:
delay=[] delay=[]
...@@ -317,10 +320,10 @@ class X393McntrlTiming(object): ...@@ -317,10 +320,10 @@ class X393McntrlTiming(object):
quiet=1): quiet=1):
""" """
Set output delays for address lines only Set output delays for address lines only
<delay> 8-bit (5+3) delay value to use or list/tuple containing individual values @param delay 8-bit (5+3) delay value to use or list/tuple containing individual values
List elements may be None, those values will not be overwritten List elements may be None, those values will not be overwritten
if delay is None will restore default values if delay is None will restore default values
<indx> if present, delay only applies to the specified index (delay should be int/long) @param indx if present, delay only applies to the specified index (delay should be int/long)
""" """
if delay is None: if delay is None:
delay=[] delay=[]
...@@ -345,10 +348,10 @@ class X393McntrlTiming(object): ...@@ -345,10 +348,10 @@ class X393McntrlTiming(object):
indx=None): # address index indx=None): # address index
""" """
Set output delays for bank lines only Set output delays for bank lines only
<delay> 8-bit (5+3) delay value to use or list/tuple containing individual values @param delay 8-bit (5+3) delay value to use or list/tuple containing individual values
List elements may be None, those values will not be overwritten List elements may be None, those values will not be overwritten
if delay is None will restore default values if delay is None will restore default values
<indx> if present, delay only applies to the specified index (delay should be int/long) @param indx if present, delay only applies to the specified index (delay should be int/long)
""" """
bank_offset=24 bank_offset=24
if delay is None: if delay is None:
...@@ -374,10 +377,10 @@ class X393McntrlTiming(object): ...@@ -374,10 +377,10 @@ class X393McntrlTiming(object):
indx=None): # address index indx=None): # address index
""" """
Set output delays for command lines only. command=(we,ras,cas,cke,odt) Set output delays for command lines only. command=(we,ras,cas,cke,odt)
<delay> 8-bit (5+3) delay value to use or list/tuple containing individual values @param delay 8-bit (5+3) delay value to use or list/tuple containing individual values
List elements may be None, those values will not be overwritten List elements may be None, those values will not be overwritten
if delay is None will restore default values if delay is None will restore default values
<indx> if present, delay only applies to the specified index (delay should be int/long) @param indx if present, delay only applies to the specified index (delay should be int/long)
""" """
command_offset=24+3 command_offset=24+3
if delay is None: if delay is None:
...@@ -410,7 +413,7 @@ class X393McntrlTiming(object): ...@@ -410,7 +413,7 @@ class X393McntrlTiming(object):
<reg_addr> control register address of the first register in the range <reg_addr> control register address of the first register in the range
<offset> add this offset to address <offset> add this offset to address
<number> number of registers to write <number> number of registers to write
<delay> 8-bit (5+3) delay value to use or list/tuple containing individual values @param delay 8-bit (5+3) delay value to use or list/tuple containing individual values
List elements may be None, those values will not be overwritten List elements may be None, those values will not be overwritten
<vname> Verilog parameter name <vname> Verilog parameter name
""" """
...@@ -439,7 +442,7 @@ class X393McntrlTiming(object): ...@@ -439,7 +442,7 @@ class X393McntrlTiming(object):
delay=None): # input [3:0] delay; delay=None): # input [3:0] delay;
""" """
Set write to buffer latency Set write to buffer latency
<delay> 4-bit write to buffer signal delay (in mclk clock cycles) @param delay 4-bit write to buffer signal delay (in mclk clock cycles)
if delay is None will restore default values if delay is None will restore default values
""" """
if delay is None: if delay is None:
......
py393/x393_pio_sequences.py
View file @ fbf5fddb
...@@ -452,7 +452,6 @@ class X393PIOSequences(object): ...@@ -452,7 +452,6 @@ class X393PIOSequences(object):
@num8 - number of 8-bursts to read (maximal 64, min- 2) @num8 - number of 8-bursts to read (maximal 64, min- 2)
@sel - 0 - early, 1 - late read command @sel - 0 - early, 1 - late read command
@verbose print data being written (default: False) @verbose print data being written (default: False)
""" """
cmd_addr = vrlg.MCONTR_CMD_WR_ADDR + vrlg.READ_BLOCK_OFFSET cmd_addr = vrlg.MCONTR_CMD_WR_ADDR + vrlg.READ_BLOCK_OFFSET
# activate # activate
...@@ -520,17 +519,20 @@ class X393PIOSequences(object): ...@@ -520,17 +519,20 @@ class X393PIOSequences(object):
ca, # input[9:0]ca; ca, # input[9:0]ca;
num8=64, num8=64,
extraTgl=0, # extraTgl=0, #
sel=1,
verbose=0): verbose=0):
""" """
Setup write block sequence at parameter defined address in the sequencer memory Setup write block sequence at parameter defined address in the sequencer memory
<ba> 3-bit memory bank address @ba 3-bit memory bank address
<ra> 15-bit memory row address @ra 15-bit memory row address
<ca> 10-bit memory column address @ca 10-bit memory column address
<num8> - number of 8-bursts (default=64, should be >2) @num8 - number of 8-bursts (default=64, should be >2)
<verbose> print data being written (default: False) @extraTgl add extra 8-burst of toggling DQS
@sel - 0 - early, 1 - late read command
@verbose print data being written (default: False)
""" """
print("===set_write_block ba=0x%x, ra=0x%x, ca=0x%x"%(ba,ra,ca)) print("===set_write_block ba=0x%x, ra=0x%x, ca=0x%x, num8=%d extraTgl=%d, sel=%d, verbose=%d"%(ba,ra,ca,num8,extraTgl,sel, verbose))
cmd_addr = vrlg.MCONTR_CMD_WR_ADDR + vrlg.WRITE_BLOCK_OFFSET cmd_addr = vrlg.MCONTR_CMD_WR_ADDR + vrlg.WRITE_BLOCK_OFFSET
# activate # activate
# addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST # addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
...@@ -545,7 +547,7 @@ class X393PIOSequences(object): ...@@ -545,7 +547,7 @@ class X393PIOSequences(object):
# first write, 3 rd_buf # first write, 3 rd_buf
# write # write
# addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST # addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data=self.func_encode_cmd(ca&0x3ff, ba, 3, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0) # B_RD moved 1 cycle earlier data=self.func_encode_cmd(ca&0x3ff, ba, 3, 1, 0, sel, 0, 0, 0, 0, 0, 1, 0, 0) # B_RD moved 1 cycle earlier
self.x393_mem.axi_write_single_w(cmd_addr, data, verbose) self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
cmd_addr += 1 cmd_addr += 1
# nop 4-th rd_buf # nop 4-th rd_buf
...@@ -557,24 +559,24 @@ class X393PIOSequences(object): ...@@ -557,24 +559,24 @@ class X393PIOSequences(object):
for i in range(1,num8-2): # 62) : #(i = 1; i < 62; i = i + 1) begin for i in range(1,num8-2): # 62) : #(i = 1; i < 62; i = i + 1) begin
# write # write
# addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST # addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data=self.func_encode_cmd((ca&0x3ff)+(i<<3), ba, 3, 1, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0) data=self.func_encode_cmd((ca&0x3ff)+(i<<3), ba, 3, 1, 0, sel, 1, 1, 1, 0, 0, 1, 1, 0)
self.x393_mem.axi_write_single_w(cmd_addr, data, verbose) self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
cmd_addr += 1 cmd_addr += 1
# addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST # addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
# data=self.func_encode_cmd((ca&0x3ff)+(62<<3), ba, 3, 1, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0) # write w/o nop # data=self.func_encode_cmd((ca&0x3ff)+(62<<3), ba, 3, 1, 0, sel, 1, 1, 1, 0, 0, 1, 0, 0) # write w/o nop
data=self.func_encode_cmd((ca&0x3ff)+((num8-2)<<3), ba, 3, 1, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0) # write w/o nop data=self.func_encode_cmd((ca&0x3ff)+((num8-2)<<3), ba, 3, 1, 0, sel, 1, 1, 1, 0, 0, 1, 0, 0) # write w/o nop
self.x393_mem.axi_write_single_w(cmd_addr, data, verbose) self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
cmd_addr += 1 cmd_addr += 1
#nop #nop
# skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST # skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data=self.func_encode_skip( 0, 0, ba, 1, 0, 1, 1, 1, 1, 0, 0, 0, 0) # nop with buffer read off data=self.func_encode_skip( 0, 0, ba, 1, 0, sel, 1, 1, 1, 0, 0, 0, 0) # nop with buffer read off
self.x393_mem.axi_write_single_w(cmd_addr, data, verbose) self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
cmd_addr += 1 cmd_addr += 1
# One last write pair w/o buffer # One last write pair w/o buffer
# addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST # addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
# data=self.func_encode_cmd((ca&0x3ff)+(63<<3), ba, 3, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0) # write with nop # data=self.func_encode_cmd((ca&0x3ff)+(63<<3), ba, 3, 1, 0, sel, 1, 1, 1, 0, 0, 0, 1, 0) # write with nop
data=self.func_encode_cmd((ca&0x3ff)+((num8-1)<<3),ba, 3, 1, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0) # write with nop data=self.func_encode_cmd((ca&0x3ff)+((num8-1)<<3),ba, 3, 1, 0, sel, 1, 1, 1, 0, 0, 0, 1, 0) # write with nop
self.x393_mem.axi_write_single_w(cmd_addr, data, verbose) self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
cmd_addr += 1 cmd_addr += 1
# nop # nop
...@@ -589,7 +591,7 @@ class X393PIOSequences(object): ...@@ -589,7 +591,7 @@ class X393PIOSequences(object):
cmd_addr += 1 cmd_addr += 1
# nop # nop
# skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST # skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
data=self.func_encode_skip( extraTgl, 0, ba, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0) data=self.func_encode_skip( extraTgl, 0, ba, sel, 0, 0, 1, 1, 1, 0, 0, 0, 0)
self.x393_mem.axi_write_single_w(cmd_addr, data, verbose) self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
cmd_addr += 1 cmd_addr += 1
# ODT off, it has latency # ODT off, it has latency
...@@ -945,15 +947,17 @@ class X393PIOSequences(object): ...@@ -945,15 +947,17 @@ class X393PIOSequences(object):
return self.x393_mcntrl_buffers.read_block_buf_chn (0, 3, num, show_rslt ) # chn=0, page=3, number of 32-bit words=num, show_rslt return self.x393_mcntrl_buffers.read_block_buf_chn (0, 3, num, show_rslt ) # chn=0, page=3, number of 32-bit words=num, show_rslt
def write_block(self, def write_block(self,
wait_complete): # Wait for operation to complete page=0,
wait_complete=1): # Wait for operation to complete
""" """
Write block in PS PIO mode Write block in PS PIO mode
<wait_complete> wait write block operation to complete (0 - may initiate multiple PS PIO operations) @param page buffer page to use
@param wait_complete wait write block operation to complete (0 - may initiate multiple PS PIO operations)
""" """
# write_block_buf_chn; # fill block memory - already set in set_up task # write_block_buf_chn; # fill block memory - already set in set_up task
self.schedule_ps_pio ( # schedule software-control memory operation (may need to check FIFO status first) self.schedule_ps_pio ( # schedule software-control memory operation (may need to check FIFO status first)
vrlg.WRITE_BLOCK_OFFSET, # input [9:0] seq_addr; # sequence start address vrlg.WRITE_BLOCK_OFFSET, # input [9:0] seq_addr; # sequence start address
0, # input [1:0] page; # buffer page number page, # input [1:0] page; # buffer page number
0, # input urgent; # high priority request (only for competion with other channels, will not pass in this FIFO) 0, # input urgent; # high priority request (only for competion with other channels, will not pass in this FIFO)
1, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write 1, # input chn; # channel buffer to use: 0 - memory read, 1 - memory write
wait_complete) # `PS_PIO_WAIT_COMPLETE )# wait_complete; # Do not request a newer transaction from the scheduler until previous memory transaction is finished wait_complete) # `PS_PIO_WAIT_COMPLETE )# wait_complete; # Do not request a newer transaction from the scheduler until previous memory transaction is finished
...@@ -1008,11 +1012,17 @@ class X393PIOSequences(object): ...@@ -1008,11 +1012,17 @@ class X393PIOSequences(object):
""" """
Read and process data in 'read patter' mode Read and process data in 'read patter' mode
refresh may be off, delays: cmda_edelay, dq_idelay, dqs_idelauy should be set refresh may be off, delays: cmda_edelay, dq_idelay, dqs_idelauy should be set
<nrep> number of times pattern burst is read (8-bursts), actually will be read nrep+3, nut the first/last will be discarded @param nrep number of times pattern burst is read (8-bursts), actually will be read nrep+3, nut the first/last will be discarded
<sel> 0 - early, 1 - late read command (shift by a SDCLK period) @param sel 0 - early, 1 - late read command (shift by a SDCLK period) -1 - use pre-programmed sequence,
-2 - use (pre-programmed) read_block sequence
""" """
if sel>=0: if sel>=0:
self.set_read_pattern(nrep+3,sel) # do not use first/last pair of the 32 bit words self.set_read_pattern(nrep+3,sel) # do not use first/last pair of the 32 bit words
if sel == -2:
buf= self.read_block((4*(nrep+1)+2), # num,
(0,1)[quiet<1], # show_rslt,
1) # Wait for operation to complete
else:
buf= self.read_pattern((4*(nrep+1)+2), # num, buf= self.read_pattern((4*(nrep+1)+2), # num,
(0,1)[quiet<1], # show_rslt, (0,1)[quiet<1], # show_rslt,
1) # Wait for operation to complete 1) # Wait for operation to complete
......
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