adding measurement of DQ_ODELAY vs DQS_ODELAY

py393/x393_lma.py

@@ -166,7 +166,7 @@ class X393LMA(object):
         use np.nan instead of the None data
         np.isnan() test
         , dtype=np.float
-        @compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,
+        @param compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,
                             save None for fraction in unknown (previous -0.5, next +0.5)
         """
         halfStep=0.5
@@ -546,15 +546,15 @@ class X393LMA(object):
         each of 2x2 elements (DQ delay values) or null
         Create data set template - for each DQS delay and inPhase
          - branch - number of full periods to add
-        @lane          byte lane to process 
-        @bin_size     bin size for the histograms (should be 5/10/20/40)
-        @clk_period   SDCLK period in ps
-        @dly_step_ds  IDELAY step (from the datasheet)
-        @primary_set  which of the data edge series to use as leading (other will be trailing by 180) 
-        @data_set     measured data set
-        @compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,
+        @param lane          byte lane to process 
+        @param bin_size     bin size for the histograms (should be 5/10/20/40)
+        @param clk_period   SDCLK period in ps
+        @param dly_step_ds  IDELAY step (from the datasheet)
+        @param primary_set  which of the data edge series to use as leading (other will be trailing by 180) 
+        @param data_set     measured data set
+        @param compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,
                             save None for fraction in unknown (previous -0.5, next +0.5)
-        @quiet        reduce output   
+        @param quiet        reduce output   
         """
         num_hist_steps=2*((DLY_STEPS+bin_size-1)//bin_size)
         
@@ -756,7 +756,7 @@ class X393LMA(object):
                          hist_estimated,
                          quiet=1): 
         """
-        @compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,
+        @param compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,
                             save None for fraction in unknown (previous -0.5, next +0.5)
         
         """                      
@@ -864,16 +864,16 @@ class X393LMA(object):
         After initial parametersn are created - run LMA to find optimal ones,
         then return up to 3 varints (early, nominal, late) providing the best
         DQ input delay for each DQS one
-        @lane         byte lane to process (or non-number - process all byte lanes of the device) 
-        @bin_size     bin size for the histograms (should be 5/10/20/40)
-        @clk_period   SDCLK period in ps
-        @dly_step_ds  IDELAY step (from the datasheet)
-        @primary_set  which of the data edge series to use as leading (other will be trailing by 180) 
-        @data_set     measured data set
-        @compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,
+        @param lane         byte lane to process (or non-number - process all byte lanes of the device) 
+        @param bin_size     bin size for the histograms (should be 5/10/20/40)
+        @param clk_period   SDCLK period in ps
+        @param dly_step_ds  IDELAY step (from the datasheet)
+        @param primary_set  which of the data edge series to use as leading (other will be trailing by 180) 
+        @param data_set     measured data set
+        @param compare_prim_steps while scanning, compare this delay with 1 less by primary(not fine) step,
                             save None for fraction in unknown (previous -0.5, next +0.5)
-        @scale_w        weight for "uncertain" values (where samples chane from all 0 to all 1 in one step)
-        @quiet        reduce output
+        @param scale_w        weight for "uncertain" values (where samples chane from all 0 to all 1 in one step)
+        @param quiet        reduce output
         @return 3-element dictionary of ('early','nominal','late'), each being None or a 160-element list,
                 each element being either None, or a list of 3 best DQ delay values for the DQS delay (some mey be None too) 
         """

py393/x393_mcntrl_buffers.py

@@ -135,9 +135,9 @@ class X393McntrlBuffers(object):
                             num_words_or_data_list): # input integer num_words; # number of words to write (will be rounded up to multiple of 16)
         """
         Fill specified buffer with the pattern data
-        <chn>                    4-bit buffer channel (0..4) to write data to
-        <page>                   2-bit buffer page to write to
-        <num_words_or_data_list> number of 32-bit words to generate/write or a list with integer data
+        @param chn                    4-bit buffer channel (0..4) to write data to
+        @param page                   2-bit buffer page to write to
+        @param num_words_or_data_list> number of 32-bit words to generate/write or a list with integer data
         """
         print("===write_block_buf_chn() chn=0x%x, page=0x%x"%(chn,page), end=" ")
         if isinstance (num_words_or_data_list,list):

py393/x393_mcntrl_tests.py

@@ -283,7 +283,7 @@ class X393McntrlTests(object):
             self.x393_mcntrl_timing.axi_set_dq_odelay(dq_odelay)
         if (not dqs_odelay is None) and (dqs_odelay != []):
             self.x393_mcntrl_timing.axi_set_dqs_odelay(dqs_odelay)
-        return self.x393_pio_sequences.write_block(wait_complete) # Wait for operation to complete
+        return self.x393_pio_sequences.write_block(0,wait_complete) # Wait for operation to complete
 
     def test_read_block(self,
                         dq_idelay=None,

py393/x393_mcntrl_timing.py

@@ -82,7 +82,7 @@ class X393McntrlTiming(object):
         <phase>    8-bit clock phase value (None will use default)
         <wait_phase_en> compare phase shift to programmed (will not work if the program was restarted)
         <wait_seq> read and re-send status request to make sure status reflects new data (just for testing, too fast for Python)
-        <quiet> reduce output
+        @param quiet reduce output
         Returns 1 if success, 0 if timeout (or no wait was performed)
         """
         if phase is None:
@@ -182,10 +182,10 @@ class X393McntrlTiming(object):
                           quiet=1):
         """
         Set all DQ input delays to the same value
-        <delay> 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
+        @param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
                 Each of the two elements in the delay tuple/list may be a a common integer or a list/tuple itself
                 if delay is None will restore default values
-        <quiet> reduce output                  
+        @param quiet reduce output                  
         """
 #        print("====axi_set_dq_idelay %s"%str(delay))
         
@@ -203,12 +203,15 @@ class X393McntrlTiming(object):
         self.x393_axi_tasks.write_contol_register  (vrlg.DLY_SET,0);# // set all delays
         
     def axi_set_dq_odelay(self,
-                          delay=None): # input [7:0] delay;
+                          delay=None, # input [7:0] delay;
+                          quiet=1):
+
         """
         Set all DQ OUTput delays to the same value
-        <delay> 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
+        @param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
                 Each of the two elements in the delay tuple/list may be a a common integer or a list/tuple itself
                 if delay is None will restore default values
+        @param quiet reduce output                  
         """
         if delay is None:
             delay=[[],[]]
@@ -217,7 +220,7 @@ class X393McntrlTiming(object):
                 delay[1].append(vrlg.get_default_field("DLY_LANE1_ODELAY",i))
         if isinstance(delay,(int,long)):
             delay=(delay,delay)
-        if self.DEBUG_MODE > 1:
+        if quiet < 2:
             print("SET DQ ODELAY="+hexMultiple(delay)) # hexMultiple
         self.axi_set_multiple_delays(vrlg.LD_DLY_LANE0_ODELAY, 0, 8, delay[0], "DLY_LANE0_ODELAY");
         self.axi_set_multiple_delays(vrlg.LD_DLY_LANE1_ODELAY, 0, 8, delay[1], "DLY_LANE1_ODELAY");
@@ -228,9 +231,9 @@ class X393McntrlTiming(object):
                            quiet=1):
         """
         Set all DQs input delays to the same value
-        <delay> 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
+        @param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
                 if delay is None will restore default values
-        <quiet> reduce output                  
+        @param quiet reduce output                  
         """
         if delay is None:
             delay=(vrlg.get_default_field("DLY_LANE0_IDELAY",8),vrlg.get_default_field("DLY_LANE1_IDELAY",8))
@@ -247,9 +250,9 @@ class X393McntrlTiming(object):
                            quiet=1):
         """
         Set all DQs OUTput delays to the same value
-        <delay> 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
+        @param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
                 if delay is None will restore default values
-        <quiet> reduce output                  
+        @param quiet reduce output                  
                 
         """
         if delay is None:
@@ -267,9 +270,9 @@ class X393McntrlTiming(object):
                            quiet=1):
         """
         Set all DM output delays to the same value
-        <delay> 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
+        @param delay 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
                 if delay is None will restore default values
-        <quiet> reduce output                  
+        @param quiet reduce output                  
         """
         if delay is None:
             delay=(vrlg.get_default_field("DLY_LANE0_ODELAY",9),vrlg.get_default_field("DLY_LANE1_ODELAY",9))
@@ -287,11 +290,11 @@ class X393McntrlTiming(object):
                                quiet=1):
         """
         Set all command/address output delays to the same value (or a list/tuple of the individual ones)
-        <delay> 8-bit (5+3) delay value to use or list/tuple containing individual values
+        @param delay 8-bit (5+3) delay value to use or list/tuple containing individual values
                 List elements may be None, those values will not be overwritten
                 if delay is None will restore default values
-        <indx>  if present, delay only applies to the specified index (delay should be int/long)
-        <quiet> reduce output                  
+        @param indx  if present, delay only applies to the specified index (delay should be int/long)
+        @param quiet reduce output                  
         """
         if delay is None:
             delay=[]
@@ -317,10 +320,10 @@ class X393McntrlTiming(object):
                                quiet=1):
         """
         Set output delays for address lines only
-        <delay> 8-bit (5+3) delay value to use or list/tuple containing individual values
+        @param delay 8-bit (5+3) delay value to use or list/tuple containing individual values
                 List elements may be None, those values will not be overwritten
                 if delay is None will restore default values
-        <indx>  if present, delay only applies to the specified index (delay should be int/long)                  
+        @param indx  if present, delay only applies to the specified index (delay should be int/long)                  
         """
         if delay is None:
             delay=[]
@@ -345,10 +348,10 @@ class X393McntrlTiming(object):
                             indx=None): # address index
         """
         Set output delays for bank lines only
-        <delay>    8-bit (5+3) delay value to use or list/tuple containing individual values
+        @param delay    8-bit (5+3) delay value to use or list/tuple containing individual values
                    List elements may be None, those values will not be overwritten
                 if delay is None will restore default values
-        <indx>  if present, delay only applies to the specified index (delay should be int/long)                  
+        @param indx  if present, delay only applies to the specified index (delay should be int/long)                  
         """
         bank_offset=24
         if delay is None:
@@ -374,10 +377,10 @@ class X393McntrlTiming(object):
                            indx=None): # address index
         """
         Set output delays for command lines only. command=(we,ras,cas,cke,odt)
-        <delay>    8-bit (5+3) delay value to use or list/tuple containing individual values
+        @param delay    8-bit (5+3) delay value to use or list/tuple containing individual values
                    List elements may be None, those values will not be overwritten
                    if delay is None will restore default values
-        <indx>  if present, delay only applies to the specified index (delay should be int/long)                  
+        @param indx  if present, delay only applies to the specified index (delay should be int/long)                  
         """
         command_offset=24+3
         if delay is None:
@@ -410,7 +413,7 @@ class X393McntrlTiming(object):
         <reg_addr> control register address of the first register in the range
         <offset>   add this offset to address
         <number>   number of registers to write
-        <delay>    8-bit (5+3) delay value to use or list/tuple containing individual values
+        @param delay    8-bit (5+3) delay value to use or list/tuple containing individual values
                    List elements may be None, those values will not be overwritten
         <vname>    Verilog parameter name
         """
@@ -439,7 +442,7 @@ class X393McntrlTiming(object):
                             delay=None): # input [3:0] delay;
         """
         Set write to buffer latency
-        <delay>    4-bit write to buffer signal delay (in mclk clock cycles)
+        @param delay    4-bit write to buffer signal delay (in mclk clock cycles)
                    if delay is None will restore default values
         """
         if delay is None:

py393/x393_pio_sequences.py

@@ -452,7 +452,6 @@ class X393PIOSequences(object):
         @num8 - number of 8-bursts to read (maximal 64, min- 2)
         @sel - 0 - early, 1 - late read command
         @verbose print data being written (default: False)
-            
         """
         cmd_addr = vrlg.MCONTR_CMD_WR_ADDR + vrlg.READ_BLOCK_OFFSET
 # activate
@@ -520,17 +519,20 @@ class X393PIOSequences(object):
                         ca,  # input[9:0]ca;
                         num8=64,
                         extraTgl=0, #
+                        sel=1,
                         verbose=0):
 
         """
         Setup write block sequence at parameter defined address in the sequencer memory
-        <ba>   3-bit memory bank address
-        <ra>  15-bit memory row address
-        <ca>  10-bit memory column address
-        <num8> - number of 8-bursts (default=64, should be >2)
-        <verbose> print data being written (default: False)
+        @ba   3-bit memory bank address
+        @ra  15-bit memory row address
+        @ca  10-bit memory column address
+        @num8 - number of 8-bursts (default=64, should be >2)
+        @extraTgl add extra 8-burst of toggling DQS
+        @sel - 0 - early, 1 - late read command
+        @verbose print data being written (default: False)
         """
-        print("===set_write_block ba=0x%x, ra=0x%x, ca=0x%x"%(ba,ra,ca))
+        print("===set_write_block ba=0x%x, ra=0x%x, ca=0x%x, num8=%d extraTgl=%d, sel=%d, verbose=%d"%(ba,ra,ca,num8,extraTgl,sel, verbose))
         cmd_addr = vrlg.MCONTR_CMD_WR_ADDR + vrlg.WRITE_BLOCK_OFFSET
 # activate
         #                          addr                 bank     RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
@@ -545,7 +547,7 @@ class X393PIOSequences(object):
 # first write, 3 rd_buf
 # write
         #                          addr                 bank     RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
-        data=self.func_encode_cmd(ca&0x3ff,              ba,      3,  1,  0,  1,  0,    0,    0,    0,  0,   1,   0,   0) # B_RD moved 1 cycle earlier 
+        data=self.func_encode_cmd(ca&0x3ff,              ba,      3,  1,  0, sel, 0,    0,    0,    0,  0,   1,   0,   0) # B_RD moved 1 cycle earlier 
         self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
         cmd_addr += 1
 # nop 4-th rd_buf
@@ -557,24 +559,24 @@ class X393PIOSequences(object):
         for i in range(1,num8-2): # 62) : #(i = 1; i < 62; i = i + 1) begin
 # write
         #                          addr                 bank     RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
-            data=self.func_encode_cmd((ca&0x3ff)+(i<<3), ba,      3,  1,  0,  1,  1,    1,    1,    0,  0,   1,   1,   0) 
+            data=self.func_encode_cmd((ca&0x3ff)+(i<<3), ba,      3,  1,  0, sel, 1,    1,    1,    0,  0,   1,   1,   0) 
             self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
             cmd_addr += 1
         #                          addr                 bank     RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
-#        data=self.func_encode_cmd((ca&0x3ff)+(62<<3),    ba,      3,  1,  0,  1,  1,    1,    1,    0,  0,   1,   0,   0) # write w/o nop
-        data=self.func_encode_cmd((ca&0x3ff)+((num8-2)<<3), ba,    3,  1,  0,  1,  1,    1,    1,    0,  0,   1,   0,   0) # write w/o nop
+#        data=self.func_encode_cmd((ca&0x3ff)+(62<<3),    ba,     3,  1,  0, sel, 1,    1,    1,    0,  0,   1,   0,   0) # write w/o nop
+        data=self.func_encode_cmd((ca&0x3ff)+((num8-2)<<3), ba,   3,  1,  0, sel, 1,    1,    1,    0,  0,   1,   0,   0) # write w/o nop
         self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
         cmd_addr += 1
 #nop
         #                          skip     done        bank         ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD      B_RST
-        data=self.func_encode_skip( 0,       0,          ba,          1,  0,  1,  1,    1,    1,    0,  0,   0,        0) # nop with buffer read off
+        data=self.func_encode_skip( 0,       0,          ba,          1,  0, sel, 1,    1,    1,    0,  0,   0,        0) # nop with buffer read off
         self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
         cmd_addr += 1
         
 # One last write pair w/o buffer
         #                          addr                 bank     RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
-#        data=self.func_encode_cmd((ca&0x3ff)+(63<<3),    ba,      3,  1,  0,  1,  1,    1,    1,    0,  0,   0,   1,   0) # write with nop
-        data=self.func_encode_cmd((ca&0x3ff)+((num8-1)<<3),ba,     3,  1,  0,  1,  1,    1,    1,    0,  0,   0,   1,   0) # write with nop
+#        data=self.func_encode_cmd((ca&0x3ff)+(63<<3),    ba,     3,  1,  0, sel, 1,    1,    1,    0,  0,   0,   1,   0) # write with nop
+        data=self.func_encode_cmd((ca&0x3ff)+((num8-1)<<3),ba,    3,  1,  0, sel, 1,    1,    1,    0,  0,   0,   1,   0) # write with nop
         self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
         cmd_addr += 1
 # nop
@@ -589,7 +591,7 @@ class X393PIOSequences(object):
         cmd_addr += 1
 # nop
         #                          skip     done        bank         ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD      B_RST
-        data=self.func_encode_skip( extraTgl,       0,          ba,          1,  0,  0,  1,    1,    1,    0,  0,   0,        0)
+        data=self.func_encode_skip( extraTgl,       0,          ba,          sel, 0,  0,  1,    1,    1,    0,  0,   0,        0)
         self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
         cmd_addr += 1
 # ODT off, it has latency
@@ -945,18 +947,20 @@ class X393PIOSequences(object):
         return self.x393_mcntrl_buffers.read_block_buf_chn (0, 3, num, show_rslt ) # chn=0, page=3, number of 32-bit words=num, show_rslt
 
     def write_block(self,
-                     wait_complete): # Wait for operation to complete
+                    page=0,
+                    wait_complete=1): # Wait for operation to complete
         """
         Write block in PS PIO mode 
-        <wait_complete> wait write block operation to complete (0 - may initiate multiple PS PIO operations)
+        @param page buffer page to use
+        @param wait_complete wait write block operation to complete (0 - may initiate multiple PS PIO operations)
         """
 #    write_block_buf_chn; # fill block memory - already set in set_up task
         self.schedule_ps_pio ( # schedule software-control memory operation (may need to check FIFO status first)
-                        vrlg.WRITE_BLOCK_OFFSET,    # input [9:0] seq_addr; # sequence start address
-                        0,                     # input [1:0] page;     # buffer page number
-                        0,                     # input       urgent;   # high priority request (only for competion with other channels, will not pass in this FIFO)
-                        1,                     # input       chn;      # channel buffer to use: 0 - memory read, 1 - memory write
-                        wait_complete)         # `PS_PIO_WAIT_COMPLETE )#  wait_complete; # Do not request a newer transaction from the scheduler until previous memory transaction is finished
+                        vrlg.WRITE_BLOCK_OFFSET, # input [9:0] seq_addr; # sequence start address
+                        page,                    # input [1:0] page;     # buffer page number
+                        0,                       # input       urgent;   # high priority request (only for competion with other channels, will not pass in this FIFO)
+                        1,                       # input       chn;      # channel buffer to use: 0 - memory read, 1 - memory write
+                        wait_complete)           # `PS_PIO_WAIT_COMPLETE )#  wait_complete; # Do not request a newer transaction from the scheduler until previous memory transaction is finished
 # temporary - for debugging:
 #        self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1) # wait previous memory transaction finished before changing delays (effective immediately)
 
@@ -1003,19 +1007,25 @@ class X393PIOSequences(object):
     
     def read_levelling(self,
                        nrep,
-                       sel=1, # 0 - early, 1 - late read command (shift by a SDCLK period), -1 - use current sequence 
+                       sel=1, # 0 - early, 1 - late read command (shift by a SDCLK period), -1 - use current sequence
                        quiet=1):
         """
         Read and process data in 'read patter' mode
         refresh may be off, delays: cmda_edelay, dq_idelay, dqs_idelauy should be set
-        <nrep>   number of times pattern burst is read (8-bursts), actually will be read nrep+3, nut the first/last will be discarded
-        <sel>    0 - early, 1 - late read command (shift by a SDCLK period)
+        @param nrep   number of times pattern burst is read (8-bursts), actually will be read nrep+3, nut the first/last will be discarded
+        @param sel    0 - early, 1 - late read command (shift by a SDCLK period) -1 - use pre-programmed sequence,
+                     -2 - use (pre-programmed) read_block sequence
         """
         if sel>=0:
             self.set_read_pattern(nrep+3,sel) # do not use first/last pair of the 32 bit words
-        buf= self.read_pattern((4*(nrep+1)+2),     # num,
-                               (0,1)[quiet<1],     # show_rslt,
-                               1) # Wait for operation to complete
+        if sel == -2:
+            buf= self.read_block((4*(nrep+1)+2),     # num,
+                                   (0,1)[quiet<1],     # show_rslt,
+                                   1) # Wait for operation to complete
+        else:
+            buf= self.read_pattern((4*(nrep+1)+2),     # num,
+                                   (0,1)[quiet<1],     # show_rslt,
+                                   1) # Wait for operation to complete
         buf= buf[4:] # discard first 4*32-bit words
         if quiet <1:
             hbuf=[]