Commit fb273d85 authored by Andrey Filippov's avatar Andrey Filippov

Generated first bitstream with raw mode bypassing compressor

parent aeb5b749
[*] [*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Wed Mar 27 16:19:27 2019 [*] Thu Mar 28 02:06:10 2019
[*] [*]
[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190326233222169.fst" [dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190327185524057.fst"
[dumpfile_mtime] "Wed Mar 27 07:01:51 2019" [dumpfile_mtime] "Thu Mar 28 02:04:11 2019"
[dumpfile_size] 734417120 [dumpfile_size] 520738951
[savefile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/cocotb/x393_cocotb_03.sav" [savefile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/cocotb/x393_cocotb_03.sav"
[timestart] 0 [timestart] 379540790
[size] 1804 1171 [size] 1804 1171
[pos] -1 -1 [pos] -1 -1
*-26.910084 660545833 212597388 212637388 379925000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-14.159636 379618470 212597388 212637388 379925000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_dut. [treeopen] x393_dut.
[treeopen] x393_dut.simul_sensor12bits_2_i. [treeopen] x393_dut.simul_sensor12bits_2_i.
[treeopen] x393_dut.simul_sensor12bits_3_i. [treeopen] x393_dut.simul_sensor12bits_3_i.
...@@ -71,7 +71,7 @@ ...@@ -71,7 +71,7 @@
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i. [treeopen] x393_dut.x393_i.timing393_i.camsync393_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0. [treeopen] x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0.
[sst_width] 309 [sst_width] 309
[signals_width] 379 [signals_width] 333
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 486 [sst_vpaned_height] 486
@820 @820
...@@ -3687,7 +3687,6 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_bu ...@@ -3687,7 +3687,6 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_bu
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_en x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_en
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_en_r x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_en_r
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_en_w x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_en_w
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_finish_r[1:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_finish_w x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_finish_w
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_go x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_go
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_pre_run x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_pre_run
...@@ -3828,6 +3827,12 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuf ...@@ -3828,6 +3827,12 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuf
-group_end -group_end
@28 @28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.stb x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.stb
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_finish_w
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_finish_r[3:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_flush
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_stb
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.stb1 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.stb1
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.chn_rst x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.chn_rst
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.chn_en x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.chn_en
...@@ -3859,8 +3864,10 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer ...@@ -3859,8 +3864,10 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.pending_xfers[1:0] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.pending_xfers[1:0]
@28 @28
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_done x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_done
@29
[color] 2 [color] 2
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.busy_r x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.busy_r
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_en_mclk x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_en_mclk
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_run_mclk x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_run_mclk
@22 @22
...@@ -3873,7 +3880,6 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuf ...@@ -3873,7 +3880,6 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuf
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.bytes_in[1:0] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.bytes_in[1:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.flush x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.flush
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.last_stb_4 x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.last_stb_4
@29
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_flush x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_flush
@c00022 @c00022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.ts_in[3:0] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.ts_in[3:0]
......
...@@ -94,10 +94,10 @@ module bit_stuffer_raw_metadata( ...@@ -94,10 +94,10 @@ module bit_stuffer_raw_metadata(
{raw_bs[2], raw_bs[1], raw_bs[0], raw_prefb}; {raw_bs[2], raw_bs[1], raw_bs[0], raw_prefb};
if (xrst) raw_stb <= 0; if (xrst) raw_stb <= 0;
else raw_stb <= raw_be16 ? raw_bs[2] : raw_bs[3]; else raw_stb <= raw_be16 ? raw_bs[2] : raw_bs[3];
if (raw_bs[0]) raw32[ 7: 0] <= raw_bytes; if (raw_bs[0]) raw32[31:24] <= raw_bytes;
if (raw_bs[1]) raw32[15: 8] <= raw_bytes; if (raw_bs[1]) raw32[23:16] <= raw_bytes;
if (raw_bs[2]) raw32[23:16] <= raw_bytes; if (raw_bs[2]) raw32[15: 8] <= raw_bytes;
if (raw_bs[3]) raw32[31:24] <= raw_bytes; if (raw_bs[3]) raw32[ 7: 0] <= raw_bytes;
end end
reg [7:0] time_ram0[0:3]; // 0 - seconds, 1 - microseconds MSB in the output 32-bit word, byt LSB of the sec/usec reg [7:0] time_ram0[0:3]; // 0 - seconds, 1 - microseconds MSB in the output 32-bit word, byt LSB of the sec/usec
...@@ -119,6 +119,7 @@ module bit_stuffer_raw_metadata( ...@@ -119,6 +119,7 @@ module bit_stuffer_raw_metadata(
reg trailer; reg trailer;
reg meta_out; reg meta_out;
reg [1:0] meta_word; reg [1:0] meta_word;
reg raw_flush_d; // raw_flush delayed by 1 cysle
reg zeros_out; // output of 32 bytes (8 words) of zeros reg zeros_out; // output of 32 bytes (8 words) of zeros
wire trailer_done = (imgsz4[2:0] == 7) && zeros_out; wire trailer_done = (imgsz4[2:0] == 7) && zeros_out;
wire meta_last = (imgsz4[2:0] == 7) && meta_out; wire meta_last = (imgsz4[2:0] == 7) && meta_out;
...@@ -127,13 +128,15 @@ module bit_stuffer_raw_metadata( ...@@ -127,13 +128,15 @@ module bit_stuffer_raw_metadata(
// wire ts_rstb= raw_mode ? raw_ts_copy: (last_block && !last_block_d); // enough time to have timestamp data; // one cycle before getting timestamp data from FIFO // wire ts_rstb= raw_mode ? raw_ts_copy: (last_block && !last_block_d); // enough time to have timestamp data; // one cycle before getting timestamp data from FIFO
wire ts_rstb= (raw_mode && raw_ts_copy) || ( compressed_mode && last_block && !last_block_d); // enough time to have timestamp data; // one cycle before getting timestamp data from FIFO wire ts_rstb= (raw_mode && raw_ts_copy) || ( compressed_mode && last_block && !last_block_d); // enough time to have timestamp data; // one cycle before getting timestamp data from FIFO
wire [7:0] ts_dout; // timestamp data, byte at a time wire [7:0] ts_dout; // timestamp data, byte at a time
wire write_size = (in_stb && (bytes_in != 0)) || (flush && last_stb_4) || raw_flush; // TODO: never in raw mode? wire write_size = (in_stb && (bytes_in != 0)) || (flush && last_stb_4) || raw_flush_d; // raw_flush; // TODO: never in raw mode?
// wire stb_start = raw_mode? raw_start: (!color_first && color_first_r) ; // wire stb_start = raw_mode? raw_start: (!color_first && color_first_r) ;
wire stb_start = (raw_mode && raw_start) || (compressed_mode && !color_first && color_first_r) ; wire stb_start = (raw_mode && raw_start) || (compressed_mode && !color_first && color_first_r) ;
wire stb = compressed_mode && in_stb && !trailer && !force_flush; wire stb = compressed_mode && in_stb && !trailer && !force_flush;
wire stb1 = raw_mode && raw_stb && !trailer && !force_flush; wire stb1 = raw_mode && raw_stb && !trailer && !force_flush;
always @ (posedge xclk) begin always @ (posedge xclk) begin
raw_flush_d <= raw_mode && raw_flush;
if (xrst ||trailer_done) imgsz4 <= 0; if (xrst ||trailer_done) imgsz4 <= 0;
else if (stb || stb1 || trailer) imgsz4 <= imgsz4 + 1; // raw included else if (stb || stb1 || trailer) imgsz4 <= imgsz4 + 1; // raw included
......
...@@ -86,7 +86,7 @@ module cmprs_raw_buf_iface #( ...@@ -86,7 +86,7 @@ module cmprs_raw_buf_iface #(
reg cmprs_run_xclk; reg cmprs_run_xclk;
reg frame_pre_run; reg frame_pre_run;
reg [FRAME_QUEUE_WIDTH:0] frame_que_cntr; // width+1 reg [FRAME_QUEUE_WIDTH:0] frame_que_cntr; // width+1
reg [1:0] frame_finish_r; // active after last macroblock in a frame reg [3:0] frame_finish_r; // active after last macroblock in a frame
reg [ 2:0] next_valid; // number of next valid page (only 2 LSB are actual page number) reg [ 2:0] next_valid; // number of next valid page (only 2 LSB are actual page number)
reg [ 2:0] needed_page; // calculate at MB start reg [ 2:0] needed_page; // calculate at MB start
...@@ -131,7 +131,7 @@ module cmprs_raw_buf_iface #( ...@@ -131,7 +131,7 @@ module cmprs_raw_buf_iface #(
// assign release_buf = page_end_w; // assign release_buf = page_end_w;
assign release_buf = page_end_r; assign release_buf = page_end_r;
assign frame_finish_w = frame_finish_r[1] && !frame_finish_r[0]; assign frame_finish_w = frame_finish_r[1] && !frame_finish_r[0]; // now just single-cycle, no need for frame_finish_r[0]
assign frames_pending = !frame_que_cntr[FRAME_QUEUE_WIDTH] && (|frame_que_cntr[FRAME_QUEUE_WIDTH-1:0]); assign frames_pending = !frame_que_cntr[FRAME_QUEUE_WIDTH] && (|frame_que_cntr[FRAME_QUEUE_WIDTH-1:0]);
assign frame_en_w = frame_en && frame_go; assign frame_en_w = frame_en && frame_go;
...@@ -144,7 +144,7 @@ module cmprs_raw_buf_iface #( ...@@ -144,7 +144,7 @@ module cmprs_raw_buf_iface #(
reg [11:0] bufa_r; // buffer read address (2 MSB - page number) reg [11:0] bufa_r; // buffer read address (2 MSB - page number)
reg [1:0] buf_rd_r; reg [1:0] buf_rd_r;
assign raw_flush = frame_finish_w; assign raw_flush = frame_finish_r[3]; // frame_finish_w;
assign buf_ra = bufa_r; assign buf_ra = bufa_r;
...@@ -198,7 +198,7 @@ module cmprs_raw_buf_iface #( ...@@ -198,7 +198,7 @@ module cmprs_raw_buf_iface #(
buf_rd_r <= {buf_rd_r[0], page_start | (|quad_r[2:0] | (quad_r[3] & page_run))}; buf_rd_r <= {buf_rd_r[0], page_start | (|quad_r[2:0] | (quad_r[3] & page_run))};
if (!frame_en) frame_finish_r <= 0; if (!frame_en) frame_finish_r <= 0;
else frame_finish_r <= {frame_finish_r[0], quad_r[2] & quad_last & rows_last[0]}; else frame_finish_r <= {frame_finish_r[2:0], quad_r[2] & quad_last & rows_last[0]};
//quads_left //quads_left
if (frame_pre_start_r || (quad_r[2] && quad_last)) quads_left <= {n_blocks_in_row_m1, 2'b11}; if (frame_pre_start_r || (quad_r[2] && quad_last)) quads_left <= {n_blocks_in_row_m1, 2'b11};
......
...@@ -36,7 +36,7 @@ ...@@ -36,7 +36,7 @@
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
parameter FPGA_VERSION = 32'h03930104; // serial - 17.4 - trigger polarity on GP1 inverted parameter FPGA_VERSION = 32'h03930104; // serial - 17.4 - added RAW mode (for tiff files) timing met
// parameter FPGA_VERSION = 32'h03930103; // serial - 17.4 - trigger polarity on GP1 inverted // parameter FPGA_VERSION = 32'h03930103; // serial - 17.4 - trigger polarity on GP1 inverted
// parameter FPGA_VERSION = 32'h03930102; // serial - 17.4 - disabling SOF when setting interface, bug fix // parameter FPGA_VERSION = 32'h03930102; // serial - 17.4 - disabling SOF when setting interface, bug fix
// parameter FPGA_VERSION = 32'h03930101; // serial - 17.4 - disabling SOF when setting interface - met // parameter FPGA_VERSION = 32'h03930101; // serial - 17.4 - disabling SOF when setting interface - met
......
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