continue simulation, moved some code to includes after modifying VDT to... (f9e935af) · Commits · Elphel / x393

ddr3.v

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includes/x393_localparams.vh

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			/*******************************************************************************
			* File: x393_localparams.vh
			* Date:2015-02-07
			* Author: andrey
			* Description: Local parameters for simulation of the x393
			*
			* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
			* x393_localparams.vh is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License as published by
			* the Free Software Foundation, either version 3 of the License, or
			* (at your option) any later version.
			*
			* x393_localparams.vh is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*
			* You should have received a copy of the GNU General Public License
			* along with this program. If not, see <http://www.gnu.org/licenses/> .
			*******************************************************************************/
	// S uppressWarnings VEditor		// S uppressWarnings VEditor
	localparam LD_DLY_LANE0_ODELAY = DLY_LD+'h00; // 0x1080		localparam LD_DLY_LANE0_ODELAY = DLY_LD+'h00; // 0x1080
	localparam LD_DLY_LANE0_IDELAY = DLY_LD+'h10; // 0x1090		localparam LD_DLY_LANE0_IDELAY = DLY_LD+'h10; // 0x1090

includes/x393_mcontr_encode_cmd.vh

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			/*******************************************************************************
			* File: x393_mcontr_encode_cmd.vh
			* Date:2015-02-09
			* Author: andrey
			* Description: Functions used to encode memory controller sequences
			*
			* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
			* x393_mcontr_encode_cmd.vh is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License as published by
			* the Free Software Foundation, either version 3 of the License, or
			* (at your option) any later version.
			*
			* x393_mcontr_encode_cmd.vh is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*
			* You should have received a copy of the GNU General Public License
			* along with this program. If not, see <http://www.gnu.org/licenses/> .
			*******************************************************************************/

			function [31:0] func_encode_skip;
			input [CMD_PAUSE_BITS-1:0] skip; // number of extra cycles to skip (and keep all the other outputs)
			input done; // end of sequence
			input [2:0] bank; // bank (here OK to be any)
			input odt_en; // enable ODT
			input cke; // disable CKE
			input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
			input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
			input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
			input dqs_toggle; // enable toggle DQS according to the pattern
			input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
			input buf_wr; // connect to external buffer (but only if not paused)
			input buf_rd; // connect to external buffer (but only if not paused)
			input buf_rst; // connect to external buffer (but only if not paused)
			begin
			func_encode_skip= func_encode_cmd (
			{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column adderss
			bank[2:0], // bank (here OK to be any)
			3'b0, // RAS/CAS/WE, positive logic
			odt_en, // enable ODT
			cke, // disable CKE
			sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
			dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
			dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
			dqs_toggle, // enable toggle DQS according to the pattern
			dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
			buf_wr, // connect to external buffer (but only if not paused)
			buf_rd, // connect to external buffer (but only if not paused)
			1'b0, // nop
			buf_rst);
			end
			endfunction

			function [31:0] func_encode_cmd;
			input [14:0] addr; // 15-bit row/column adderss
			input [2:0] bank; // bank (here OK to be any)
			input [2:0] rcw; // RAS/CAS/WE, positive logic
			input odt_en; // enable ODT
			input cke; // disable CKE
			input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
			input dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
			input dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
			input dqs_toggle; // enable toggle DQS according to the pattern
			input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
			input buf_wr; // connect to external buffer (but only if not paused)
			input buf_rd; // connect to external buffer (but only if not paused)
			input nop; // add NOP after the current command, keep other data
			input buf_rst; // connect to external buffer (but only if not paused)
			begin
			func_encode_cmd={
			addr[14:0], // 15-bit row/column adderss
			bank [2:0], // bank
			rcw[2:0], // RAS/CAS/WE
			odt_en, // enable ODT
			cke, // may be optimized (removed from here)?
			sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
			dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
			dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
			dqs_toggle, // enable toggle DQS according to the pattern
			dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
			buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)
			buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)
			nop, // add NOP after the current command, keep other data
			buf_rst // Reserved for future use
			};
			end
			endfunction

includes/x393_parameters.vh

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			/*******************************************************************************
			* File: x393_parameters.vh
			* Date:2015-02-07
			* Author: andrey
			* Description: Parameters for the x393 (simulation and implementation)
			*
			* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
			* x393_parameters.vh is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License as published by
			* the Free Software Foundation, either version 3 of the License, or
			* (at your option) any later version.
			*
			* x393_parameters.vh is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*
			* You should have received a copy of the GNU General Public License
			* along with this program. If not, see <http://www.gnu.org/licenses/> .
			*******************************************************************************/
	parameter MCONTR_WR_MASK = 'h1c00, // AXI write address mask for the 1Kx32 buffers command sequence memory		parameter MCONTR_WR_MASK = 'h1c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
	parameter MCONTR_RD_MASK = 'h1c00, // AXI read address mask to generate busy		parameter MCONTR_RD_MASK = 'h1c00, // AXI read address mask to generate busy

includes/x393_simulation_parameters.vh

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	// simulation-specific parameters		/*******************************************************************************
	, // to continue previous list		* File: x393_simulation_parameters.vh
			* Date:2015-02-07
			* Author: andrey
			* Description: Simulation-specific parameters for the x393
			*
			* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
			* x393_simulation_parameters.vh is free software; you can redistribute it and/or modify
			* it under the terms of the GNU General Public License as published by
			* the Free Software Foundation, either version 3 of the License, or
			* (at your option) any later version.
			*
			* x393_simulation_parameters.vh is distributed in the hope that it will be useful,
			* but WITHOUT ANY WARRANTY; without even the implied warranty of
			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
			* GNU General Public License for more details.
			*
			* You should have received a copy of the GNU General Public License
			* along with this program. If not, see <http://www.gnu.org/licenses/> .
			*******************************************************************************/
			, // to continue previous parameter list
	parameter integer AXI_RDADDR_LATENCY= 2, // 2, //2, //2,		parameter integer AXI_RDADDR_LATENCY= 2, // 2, //2, //2,
	parameter integer AXI_WRADDR_LATENCY= 1, // 1, //2, //4,		parameter integer AXI_WRADDR_LATENCY= 1, // 1, //2, //4,
	parameter integer AXI_WRDATA_LATENCY= 2, // 1, //1, //1		parameter integer AXI_WRDATA_LATENCY= 2, // 1, //1, //1

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