simulating/debugging modified i2c sequencer

f8eca99e · Andrey Filippov · 74db68c1 · f8eca99e · f8eca99e · f8eca99e
Commit f8eca99e authored Oct 09, 2015 by Andrey Filippov
10 changed files
--- a/includes/x393_parameters.vh
+++ b/includes/x393_parameters.vh
@@ -352,10 +352,24 @@
        parameter SENSI2C_CMD_RESET =       14, // [14]   reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
        parameter SENSI2C_CMD_RUN =         13, // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
        parameter SENSI2C_CMD_RUN_PBITS =    1,
-        parameter SENSI2C_CMD_FIFO_RD =      3, // advane I2C read data FIFO by 1  
+        parameter SENSI2C_CMD_FIFO_RD =      3, // advance I2C read data FIFO by 1  
        parameter SENSI2C_CMD_ACIVE =        2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
        parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
        parameter SENSI2C_CMD_ACIVE_SDA =    0,  // drive SDA=1 during the second half of SCL=1
+    //i2c page table bit fields
+        parameter SENSI2C_TBL_RAH =          0, // high byte of the register address 
+        parameter SENSI2C_TBL_RAH_BITS =     8,
+        parameter SENSI2C_TBL_RNWREG =       8, // read register (when 0 - write register
+        parameter SENSI2C_TBL_SA =           9, // Slave address in write mode
+        parameter SENSI2C_TBL_SA_BITS =      7,
+        parameter SENSI2C_TBL_NBWR =        16, // number of bytes to write (1..10)
+        parameter SENSI2C_TBL_NBWR_BITS =    4,
+        parameter SENSI2C_TBL_NBRD =        16, // number of bytes to read (1 - 8) "0" means "8"
+        parameter SENSI2C_TBL_NBRD_BITS =    3,
+        parameter SENSI2C_TBL_NABRD =       19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
+        parameter SENSI2C_TBL_DLY =         20, // bit delay (number of mclk periods in 1/4 of SCL period)
+        parameter SENSI2C_TBL_DLY_BITS=      8,
+        
      
      parameter SENSI2C_STATUS =        'h1,
    

--- a/sensor/sensor_channel.v
+++ b/sensor/sensor_channel.v
@@ -73,6 +73,20 @@ module  sensor_channel#(
        parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
        parameter SENSI2C_CMD_ACIVE_SDA =    0,  // drive SDA=1 during the second half of SCL=1
        
+    //i2c page table bit fields
+        parameter SENSI2C_TBL_RAH =          0, // high byte of the register address 
+        parameter SENSI2C_TBL_RAH_BITS =     8,
+        parameter SENSI2C_TBL_RNWREG =       8, // read register (when 0 - write register
+        parameter SENSI2C_TBL_SA =           9, // Slave address in write mode
+        parameter SENSI2C_TBL_SA_BITS =      7,
+        parameter SENSI2C_TBL_NBWR =        16, // number of bytes to write (1..10)
+        parameter SENSI2C_TBL_NBWR_BITS =    4,
+        parameter SENSI2C_TBL_NBRD =        16, // number of bytes to read (1 - 8) "0" means "8"
+        parameter SENSI2C_TBL_NBRD_BITS =    3,
+        parameter SENSI2C_TBL_NABRD =       19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
+        parameter SENSI2C_TBL_DLY =         20, // bit delay (number of mclk periods in 1/4 of SCL period)
+        parameter SENSI2C_TBL_DLY_BITS=      8,
+      
      parameter SENSI2C_STATUS =        'h1,
    
    parameter SENS_GAMMA_RADDR =       'h38, //4,  'h38..'h3b
@@ -493,6 +507,18 @@ module  sensor_channel#(
        .SENSI2C_CMD_ACIVE       (SENSI2C_CMD_ACIVE),
        .SENSI2C_CMD_ACIVE_EARLY0(SENSI2C_CMD_ACIVE_EARLY0),
        .SENSI2C_CMD_ACIVE_SDA   (SENSI2C_CMD_ACIVE_SDA),
+        .SENSI2C_TBL_RAH         (SENSI2C_TBL_RAH), // high byte of the register address 
+        .SENSI2C_TBL_RAH_BITS    (SENSI2C_TBL_RAH_BITS),
+        .SENSI2C_TBL_RNWREG      (SENSI2C_TBL_RNWREG), // read register (when 0 - write register
+        .SENSI2C_TBL_SA          (SENSI2C_TBL_SA), // Slave address in write mode
+        .SENSI2C_TBL_SA_BITS     (SENSI2C_TBL_SA_BITS),
+        .SENSI2C_TBL_NBWR        (SENSI2C_TBL_NBWR), // number of bytes to write (1..10)
+        .SENSI2C_TBL_NBWR_BITS   (SENSI2C_TBL_NBWR_BITS),
+        .SENSI2C_TBL_NBRD        (SENSI2C_TBL_NBRD), // number of bytes to read (1 - 8) "0" means "8"
+        .SENSI2C_TBL_NBRD_BITS   (SENSI2C_TBL_NBRD_BITS),
+        .SENSI2C_TBL_NABRD       (SENSI2C_TBL_NABRD), // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
+        .SENSI2C_TBL_DLY         (SENSI2C_TBL_DLY),   // bit delay (number of mclk periods in 1/4 of SCL period)
+        .SENSI2C_TBL_DLY_BITS    (SENSI2C_TBL_DLY_BITS),
        .SENSI2C_DRIVE           (SENSI2C_DRIVE),
        .SENSI2C_IBUF_LOW_PWR    (SENSI2C_IBUF_LOW_PWR),
        .SENSI2C_IOSTANDARD      (SENSI2C_IOSTANDARD),

--- a/sensor/sensor_i2c.v
+++ b/sensor/sensor_i2c.v
@@ -39,7 +39,21 @@ module  sensor_i2c#(
    parameter SENSI2C_CMD_FIFO_RD =      3, // advane I2C read data FIFO by 1  
    parameter SENSI2C_CMD_ACIVE =        2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
    parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
-    parameter SENSI2C_CMD_ACIVE_SDA =    0  // drive SDA=1 during the second half of SCL=1
+    parameter SENSI2C_CMD_ACIVE_SDA =    0,  // drive SDA=1 during the second half of SCL=1
+
+    //i2c page table bit fields
+    parameter SENSI2C_TBL_RAH =          0, // high byte of the register address 
+    parameter SENSI2C_TBL_RAH_BITS =     8,
+    parameter SENSI2C_TBL_RNWREG =       8, // read register (when 0 - write register
+    parameter SENSI2C_TBL_SA =           9, // Slave address in write mode
+    parameter SENSI2C_TBL_SA_BITS =      7,
+    parameter SENSI2C_TBL_NBWR =        16, // number of bytes to write (1..10)
+    parameter SENSI2C_TBL_NBWR_BITS =    4,
+    parameter SENSI2C_TBL_NBRD =        16, // number of bytes to read (1 - 8) "0" means "8"
+    parameter SENSI2C_TBL_NBRD_BITS =    3,
+    parameter SENSI2C_TBL_NABRD =       19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
+    parameter SENSI2C_TBL_DLY =         20, // bit delay (number of mclk periods in 1/4 of SCL period)
+    parameter SENSI2C_TBL_DLY_BITS=      8
 )(
    input         mrst,         // @ posedge mclk
    input         mclk,         // global clock, half DDR3 clock, synchronizes all I/O through the command port
@@ -304,7 +318,7 @@ module  sensor_i2c#(
      if      (reset_cmd || page_r_inc[0])  rpointer[5:0] <= 6'h0;
      else if (i2c_run_d && ! i2c_run)      rpointer[5:0] <= rpointer[5:0] + 1;

-      i2c_start <= i2c_enrun && !i2c_run && !i2c_start && (rpointer[5:0]!= fifo_wr_pointers_outr_r[5:0]) && !(|page_r_inc);
+      i2c_start <= i2c_enrun && !i2c_run && !i2c_run_d && !i2c_start && (rpointer[5:0]!= fifo_wr_pointers_outr_r[5:0]) && !(|page_r_inc);
      page_r_inc[1:0] <= {page_r_inc[0],
                           !i2c_run &&                              // not i2c in progress
                           !page_r_inc[0] &&                        // was not incrementing in previous cycle
@@ -326,7 +340,20 @@ module  sensor_i2c#(
     
    end
    
-    sensor_i2c_prot sensor_i2c_prot_i (
+    sensor_i2c_prot  #(
+        .SENSI2C_TBL_RAH         (SENSI2C_TBL_RAH), // high byte of the register address 
+        .SENSI2C_TBL_RAH_BITS    (SENSI2C_TBL_RAH_BITS),
+        .SENSI2C_TBL_RNWREG      (SENSI2C_TBL_RNWREG), // read register (when 0 - write register
+        .SENSI2C_TBL_SA          (SENSI2C_TBL_SA), // Slave address in write mode
+        .SENSI2C_TBL_SA_BITS     (SENSI2C_TBL_SA_BITS),
+        .SENSI2C_TBL_NBWR        (SENSI2C_TBL_NBWR), // number of bytes to write (1..10)
+        .SENSI2C_TBL_NBWR_BITS   (SENSI2C_TBL_NBWR_BITS),
+        .SENSI2C_TBL_NBRD        (SENSI2C_TBL_NBRD), // number of bytes to read (1 - 8) "0" means "8"
+        .SENSI2C_TBL_NBRD_BITS   (SENSI2C_TBL_NBRD_BITS),
+        .SENSI2C_TBL_NABRD       (SENSI2C_TBL_NABRD), // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
+        .SENSI2C_TBL_DLY         (SENSI2C_TBL_DLY),   // bit delay (number of mclk periods in 1/4 of SCL period)
+        .SENSI2C_TBL_DLY_BITS    (SENSI2C_TBL_DLY_BITS)
+    ) sensor_i2c_prot_i(
        .mrst            (mrst),            // input
        .mclk            (mclk),            // input
        .i2c_rst         (reset_cmd),       // input

--- a/sensor/sensor_i2c_io.v
+++ b/sensor/sensor_i2c_io.v
@@ -40,6 +40,19 @@ module  sensor_i2c_io#(
    parameter SENSI2C_CMD_ACIVE =        2, // [2] - SENSI2C_CMD_ACIVE_EARLY0, SENSI2C_CMD_ACIVE_SDA
    parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
    parameter SENSI2C_CMD_ACIVE_SDA =    0,  // drive SDA=1 during the second half of SCL=1
+    //i2c page table bit fields
+    parameter SENSI2C_TBL_RAH =          0, // high byte of the register address 
+    parameter SENSI2C_TBL_RAH_BITS =     8,
+    parameter SENSI2C_TBL_RNWREG =       8, // read register (when 0 - write register
+    parameter SENSI2C_TBL_SA =           9, // Slave address in write mode
+    parameter SENSI2C_TBL_SA_BITS =      7,
+    parameter SENSI2C_TBL_NBWR =        16, // number of bytes to write (1..10)
+    parameter SENSI2C_TBL_NBWR_BITS =    4,
+    parameter SENSI2C_TBL_NBRD =        16, // number of bytes to read (1 - 8) "0" means "8"
+    parameter SENSI2C_TBL_NBRD_BITS =    3,
+    parameter SENSI2C_TBL_NABRD =       19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
+    parameter SENSI2C_TBL_DLY =         20, // bit delay (number of mclk periods in 1/4 of SCL period)
+    parameter SENSI2C_TBL_DLY_BITS=      8,
 // I/O parameters   
    parameter integer SENSI2C_DRIVE = 12,
    parameter SENSI2C_IBUF_LOW_PWR = "TRUE",
@@ -81,8 +94,19 @@ module  sensor_i2c_io#(
        .SENSI2C_CMD_FIFO_RD     (SENSI2C_CMD_FIFO_RD),
        .SENSI2C_CMD_ACIVE       (SENSI2C_CMD_ACIVE),
        .SENSI2C_CMD_ACIVE_EARLY0(SENSI2C_CMD_ACIVE_EARLY0),
-        .SENSI2C_CMD_ACIVE_SDA   (SENSI2C_CMD_ACIVE_SDA)
-        
+        .SENSI2C_CMD_ACIVE_SDA   (SENSI2C_CMD_ACIVE_SDA),
+        .SENSI2C_TBL_RAH         (SENSI2C_TBL_RAH), // high byte of the register address 
+        .SENSI2C_TBL_RAH_BITS    (SENSI2C_TBL_RAH_BITS),
+        .SENSI2C_TBL_RNWREG      (SENSI2C_TBL_RNWREG), // read register (when 0 - write register
+        .SENSI2C_TBL_SA          (SENSI2C_TBL_SA), // Slave address in write mode
+        .SENSI2C_TBL_SA_BITS     (SENSI2C_TBL_SA_BITS),
+        .SENSI2C_TBL_NBWR        (SENSI2C_TBL_NBWR), // number of bytes to write (1..10)
+        .SENSI2C_TBL_NBWR_BITS   (SENSI2C_TBL_NBWR_BITS),
+        .SENSI2C_TBL_NBRD        (SENSI2C_TBL_NBRD), // number of bytes to read (1 - 8) "0" means "8"
+        .SENSI2C_TBL_NBRD_BITS   (SENSI2C_TBL_NBRD_BITS),
+        .SENSI2C_TBL_NABRD       (SENSI2C_TBL_NABRD), // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
+        .SENSI2C_TBL_DLY         (SENSI2C_TBL_DLY),   // bit delay (number of mclk periods in 1/4 of SCL period)
+        .SENSI2C_TBL_DLY_BITS    (SENSI2C_TBL_DLY_BITS)
    ) sensor_i2c_i (
        .mrst          (mrst),         // input
        .mclk          (mclk),         // input

--- a/sensor/sensor_i2c_prot.v
+++ b/sensor/sensor_i2c_prot.v
@@ -20,7 +20,20 @@
 *******************************************************************************/
 `timescale 1ns/1ps

-module  sensor_i2c_prot(
+module  sensor_i2c_prot#(
+    parameter SENSI2C_TBL_RAH =          0, // high byte of the register address 
+    parameter SENSI2C_TBL_RAH_BITS =     8,
+    parameter SENSI2C_TBL_RNWREG =       8, // read register (when 0 - write register
+    parameter SENSI2C_TBL_SA =           9, // Slave address in write mode
+    parameter SENSI2C_TBL_SA_BITS =      7,
+    parameter SENSI2C_TBL_NBWR =        16, // number of bytes to write (1..10)
+    parameter SENSI2C_TBL_NBWR_BITS =    4,
+    parameter SENSI2C_TBL_NBRD =        16, // number of bytes to read (1 - 8) "0" means "8"
+    parameter SENSI2C_TBL_NBRD_BITS =    3,
+    parameter SENSI2C_TBL_NABRD =       19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
+    parameter SENSI2C_TBL_DLY =         20, // bit delay (number of mclk periods in 1/4 of SCL period)
+    parameter SENSI2C_TBL_DLY_BITS=      8
+)(
    input            mrst,         // @ posedge mclk
    input            mclk,         // global clock
    input            i2c_rst,
@@ -83,6 +96,7 @@ module  sensor_i2c_prot(
    reg           run_extra_wr_d;  // any of run_extra_wr bits, delayed by 1
    reg           run_any_d;       // any of command states, delayed by 1
    reg    [1:0]  pre_cmd;         // from i2c_start until run_any_d will be active
+    reg           first_mem_re;
 //    reg           i2c_done;
 //    wire          i2c_next_byte;
    reg    [ 2:0] mem_re;
@@ -92,13 +106,13 @@ module  sensor_i2c_prot(
 //    reg           read_mem_msb;
 //    wire          decode_reg_rd = &seq_rd[7:4];
 //    wire          start_wr_seq_w = !run_extra_wr_d && !decode_reg_rd && read_mem_msb;
-    wire          start_wr_seq_w = table_re[2] && !tdout[8];
-    wire          start_rd_seq_w = table_re[2] &&  tdout[8];
+    wire          start_wr_seq_w = table_re[2] && !tdout[SENSI2C_TBL_RNWREG];
+    wire          start_rd_seq_w = table_re[2] &&  tdout[SENSI2C_TBL_RNWREG];
    wire          start_extra_seq_w = i2c_start && (bytes_left_send !=0);
    
-    wire          snd_start_w = run_reg_wr[6] || 1'b0; // add start & restart of read
-    wire          snd_stop_w =  run_reg_wr[0] || 1'b0; // add stop of read
-    wire          snd9_w     =  (|run_reg_wr[5:1]) || 1'b0; // add for read and extra write;
+ //   wire          snd_start_w = run_reg_wr[6] || 1'b0; // add start & restart of read
+ //   wire          snd_stop_w =  run_reg_wr[0] || 1'b0; // add stop of read
+ //   wire          snd9_w     =  (|run_reg_wr[5:1]) || 1'b0; // add for read and extra write;

    reg           snd_start;
    reg           snd_stop;
@@ -129,7 +143,7 @@ module  sensor_i2c_prot(
    wire   [ 3:0] initial_address_w =  bytes_left_send - 1; // if bytes left to send == 0 - will be 3                      
    wire          unused;            // unused ackn signal SuppressThisWarning VEditor
    
-    wire          pre_table_re = !run_extra_wr_d && (&seq_mem_ra[1:0]) && mem_re[1];
+    wire          pre_table_re = !run_extra_wr_d && first_mem_re && mem_re[1];
    
    
      
@@ -140,6 +154,10 @@ module  sensor_i2c_prot(
        
        run_any_d <= (|run_reg_wr) || (|run_extra_wr) || (|run_reg_rd);
        
+        if (mrst || i2c_rst)  first_mem_re <= 0;
+        else if (i2c_start)   first_mem_re <= 1;
+        else if (mem_re[2])   first_mem_re <= 0;
+        
        if (mrst || i2c_rst) pre_cmd <= 0;
        else if (i2c_start)  pre_cmd <= 1;
        else if (run_any_d)  pre_cmd <= 0;
@@ -154,25 +172,25 @@ module  sensor_i2c_prot(
        table_re <= {table_re[2:0], pre_table_re}; // start_wr_seq_w};
        
        if (table_re[2]) begin
-            reg_ah <=         tdout[7:0];   // MSB of the register address (instead of the byte 2)
-            num_bytes_send <= tdout[19:16]; // number of bytes to send (if more than 4 will skip stop and continue with next data
-            i2c_dly <=        tdout[27:20];
+            reg_ah <=         tdout[SENSI2C_TBL_RAH +: SENSI2C_TBL_RAH_BITS]; //[ 7:0];   // MSB of the register address (instead of the byte 2)
+            num_bytes_send <= tdout[SENSI2C_TBL_NBWR +: SENSI2C_TBL_NBWR_BITS] ; // [19:16]; // number of bytes to send (if more than 4 will skip stop and continue with next data
+            i2c_dly <=        tdout[SENSI2C_TBL_DLY +: SENSI2C_TBL_DLY_BITS]; //[27:20];
        end
-        if      (table_re[2])               slave_a_rah <= {tdout[15:9], 1'b0};
-        else if (next_cmd && run_reg_wr[6]) slave_a_rah <= reg_ah; // will copy even if not used
+        if      (table_re[2])               slave_a_rah <= {tdout[SENSI2C_TBL_SA +: SENSI2C_TBL_SA_BITS], 1'b0}; // {tdout[15:9], 1'b0};
+        else if (next_cmd && run_reg_wr[5]) slave_a_rah <= reg_ah; // will copy even if not used
        
        next_cmd <= pre_next_cmd;
        
        next_cmd_d <= next_cmd;
        
-        next_byte_wr <= snd9 && i2c_rdy; // same time as next_cmd
+        next_byte_wr <= snd9 && i2c_rdy && !run_reg_wr[5]; // same time as next_cmd, no pulse when sending SA during write

-        snd_start <= snd_start_w; // add & i2c_ready? Not really needed as any i2c stage will be busy for long enough
-        snd_stop <=  snd_stop_w;
-        snd9 <=      snd9_w;
+//        snd_start <= snd_start_w; // add & i2c_ready? Not really needed as any i2c stage will be busy for long enough
+//        snd_stop <=  snd_stop_w;
+//        snd9 <=      snd9_w;
        
        if     (mrst || i2c_rst) bytes_left_send <= 0;
-        else if (start_wr_seq_w) bytes_left_send <= num_bytes_send;
+        else if (start_wr_seq_w) bytes_left_send <= tdout[SENSI2C_TBL_NBWR +: SENSI2C_TBL_NBWR_BITS]; // num_bytes_send;
        else if (next_byte_wr)   bytes_left_send <= bytes_left_send - 1;

        // calculate stages for each type of commands
@@ -206,12 +224,11 @@ module  sensor_i2c_prot(

 //     reg    [ 7:0] run_reg_rd; // [7] - start, [6] SA (byte 3), [5] (optional) - RA_msb, [4] - RA_lsb, [3] - restart, [2] - SA, [1] - read bytes, [0] - stop

-//        if (!run_extra_wr &&  decode_reg_rd && read_mem_msb) read_address_bytes <= seq_rd[3];
-//        if (!run_extra_wr &&  decode_reg_rd && read_mem_msb) read_data_bytes <= seq_rd[2:0];
-
-        if      (table_re[2] &&  tdout[8])  read_address_bytes <= tdout[19];
+//        if      (table_re[2] &&  tdout[8])  read_address_bytes <= tdout[19];
+        if      (table_re[2] &&  tdout[SENSI2C_TBL_RNWREG])  read_address_bytes <= tdout[SENSI2C_TBL_NABRD]; // [19];
        
-        if      (table_re[2] &&  tdout[8])  read_data_bytes <= tdout[18:16];
+//        if      (table_re[2] &&  tdout[8])  read_data_bytes <= tdout[18:16];
+        if      (table_re[2] &&  tdout[SENSI2C_TBL_RNWREG])  read_data_bytes <= tdout[SENSI2C_TBL_NBRD +: SENSI2C_TBL_NBRD_BITS];
        else if (run_reg_rd[1] && next_cmd) read_data_bytes <= read_data_bytes - 1;
        
        // read i2c data
@@ -245,11 +262,18 @@ module  sensor_i2c_prot(
        
        send_seq_data <= !next_cmd && mem_valid && ((|run_reg_wr[3:1]) || (|run_extra_wr[4:1]) || (|run_reg_rd[6:4])); 
        send_rd_sa <=    !next_cmd && run_reg_rd[2];
-        send_sa_rah <=   !next_cmd && (|run_reg_wr[6:5]);
+        send_sa_rah <=   !next_cmd && (|run_reg_wr[5:4]);
        send_rd <=       !next_cmd && run_reg_rd[1];
        
-        if (mrst || i2c_rst) snd9 <= 0;
+        if (mrst || i2c_rst || next_cmd) snd9 <= 0;
        else                             snd9 <= snd9 ? (!i2c_rdy) : ((send_seq_data || send_rd_sa || send_sa_rah || send_rd) && !next_cmd);
+
+        if (mrst || i2c_rst || next_cmd) snd_start <= 0;
+        else                             snd_start <= snd_start? (!i2c_rdy) : (run_reg_wr[6] || run_reg_rd[7] || run_reg_rd[3]);
+
+        if (mrst || i2c_rst || next_cmd) snd_stop <= 0;
+        else                             snd_stop <= snd_stop? (!i2c_rdy) : (run_reg_wr[0] || run_extra_wr[0] || run_reg_rd[0]);
+        
        case (sel_sr_in)
            2'h0: sr_in <= {seq_rd, 1'b1};
            2'h1: sr_in <= {rd_sa, 2'b11};
@@ -269,6 +293,7 @@ module  sensor_i2c_prot(
        .snd_start       (snd_start),     // input
        .snd_stop        (snd_stop),      // input
        .snd9            (snd9),          // input
+        .rcv             (run_reg_rd[1]), // input       
        .din             (sr_in),         // input[8:0] 
        .dout            ({rdata,unused}),// output[8:0] 
        .dout_stb        (rvalid),        // output reg 

--- a/sensor/sensor_i2c_scl_sda.v
+++ b/sensor/sensor_i2c_scl_sda.v
@@ -30,7 +30,7 @@ module  sensor_i2c_scl_sda(
    input         snd_start,
    input         snd_stop,
    input         snd9,
-//    input         rcv,         // recieve mode (valid with snd9) - master receives, slave - sends
+    input         rcv,         // receive mode (valid with snd9) - master receives, slave - sends
    input  [ 8:0] din,
    output [ 8:0] dout,        //
    output reg    dout_stb,    // dout contains valid data
@@ -47,12 +47,13 @@ module  sensor_i2c_scl_sda(
    reg    [8:0] sr;
    reg    [7:0] dly_cntr;
    reg          busy_r;
-    wire         snd_start_w =  snd_start && !busy_r;
-    wire         snd_stop_w =   snd_stop && !busy_r;
-    wire         snd9_w =       snd9 && !busy_r;
-    wire         start_w =      (snd_start || snd_stop || snd9_w) && !busy_r;
+    wire         snd_start_w =  snd_start && ready; //!busy_r;
+    wire         snd_stop_w =   snd_stop && ready; // !busy_r;
+    wire         snd9_w =       snd9 && ready; //!busy_r;
+    wire         start_w =      (snd_start || snd_stop || snd9_w) && ready; //!busy_r;
    reg          pre_dly_over;
    reg          dly_over;
+//    reg          dly_over_d;
    reg    [3:0] seq_start_restart;
    reg    [2:0] seq_stop;
    reg    [3:0] seq_bit;
@@ -60,12 +61,26 @@ module  sensor_i2c_scl_sda(
    reg          done_r;
    reg          sda_r;
    reg          first_cyc; // first clock cycle for the delay interval - update SCL/SDA outputs
-    assign ready = !busy_r;
+    reg          active_sda_r; // registered @ snd9, disable in rcv mode
+    reg          active_sda_was_0; // only use active SDA if previous bit was 0 or it is receive mode
+    reg          rcv_r;
+    wire         busy_w = busy_r && ! done_r; 
+//    assign ready = !busy_r;
+    assign ready = !busy_w;
+    
    assign is_open =  is_open_r;
    assign dout =     sr;
    always @ (posedge mclk) begin
+        active_sda_was_0 <= !sda || rcv_r;
+        if (snd9_w) rcv_r <= rcv;
+
+        // disable active_sda in send messages for the last (ACKN) bit, for the receive - all but ACKN
+        if      (snd9_w)                    active_sda_r <= active_sda && !rcv;
+        else if (snd_start_w || snd_stop_w) active_sda_r <= active_sda;
+        else if (dly_over && seq_bit[0])    active_sda_r <= active_sda && ((bits_left != 1) ^ rcv_r);
+//active_sda_r && !sda    
        if      (rst)         seq_start_restart <= 0;
-        else if (snd_start_w) seq_start_restart <= is_open_r ? 4'h8 : 4'h4;
+        else if (snd_start_w) seq_start_restart <= (is_open_r && !seq_stop[0]) ? 4'h8 : 4'h4;
        else if (dly_over)    seq_start_restart <= {1'b0,seq_start_restart[3:1]};
    
        if      (rst)         seq_stop <= 0;
@@ -73,35 +88,39 @@ module  sensor_i2c_scl_sda(
        else if (dly_over)    seq_stop <= {1'b0,seq_stop[2:1]};

        if      (rst)                                                    seq_bit <= 0;
-        else if (snd_start_w || (seq_bit[0] && (bits_left != 0))) seq_bit <= 4'h8;
+        else if (snd9_w || (seq_bit[0] && (bits_left != 0) && dly_over)) seq_bit <= 4'h8;
        else if (dly_over)                                               seq_bit <= {1'b0,seq_bit[3:1]};
        
-        if      (rst)                                             bits_left <= 0;
+        if      (rst)                                             bits_left <= 4'h0;
        else if (snd9_w)                                          bits_left <= 4'h8;
-        else if (dly_over && seq_bit[0])                          bits_left <= bits_left - 1;
+        else if (dly_over && seq_bit[0] && (|bits_left))          bits_left <= bits_left - 1;


        if      (rst)     busy_r <= 0;
        else if (start_w) busy_r <= 1;
        else if (done_r)  busy_r <= 0;
        
+//        pre_dly_over <=  (dly_cntr == 3);
        pre_dly_over <=  (dly_cntr == 2);
        
        dly_over <=      pre_dly_over;
-        
+//        dly_over_d <=    dly_over;
        if      (rst)     done_r <= 0;
        else              done_r <= pre_dly_over &&
                                   (bits_left == 0) &&
                                   (seq_start_restart[3:1] == 0) &&
                                   (seq_stop[2:1] == 0) &&
-                                   (bits_left[3:1] == 0);
+                                   (seq_bit[3:1] == 0);
+                                   
+//        if (!busy_r || dly_over_d) dly_cntr <= i2c_dly;
+//        else                       dly_cntr <= dly_cntr - 1;
        
-        if (!busy_r || dly_over) dly_cntr <= i2c_dly;
+        if (!busy_w || dly_over) dly_cntr <= i2c_dly;
        else                     dly_cntr <= dly_cntr - 1;
        
        if (dly_over && seq_bit[1]) sda_r <= sda_in; // just before the end of SCL pulse - delay it by a few clocks to match external latencies?
        
-        if      (snd_start_w)            sr <= din;
+        if      (snd9_w)                 sr <= din;
        else if (dly_over && seq_bit[0]) sr <= {sr[7:0], sda_r};
        
        dout_stb <= dly_over && seq_bit[0] && (bits_left == 0);
@@ -113,20 +132,24 @@ module  sensor_i2c_scl_sda(
        first_cyc <= start_w || dly_over;

        if      (rst)        scl <= 1;
-        else if (first_cyc)  scl <= !busy_r ||
+//        else if (first_cyc)  scl <= !busy_r || // Wrong whe "open"?
+        else if (first_cyc)  scl <= (scl && !busy_w) || // Wrong whe "open"?
                                     seq_start_restart[2] ||  seq_start_restart[1] ||
                                     seq_stop[1] || seq_stop[0] ||
                                     seq_bit[2] || seq_bit[1];
                                                       
        if      (rst)        sda <= 1;
-        else if (first_cyc)  sda <= !busy_r ||
+//        else if (first_cyc)  sda <= !busy_r ||
+        else if (first_cyc)  sda <= (sda && !busy_w) ||
                                     seq_start_restart[3] ||  seq_start_restart[2] ||
                                     seq_stop[0] ||
                                     (sr[8] && (|seq_bit));

        if      (rst)        sda_en <= 1;
-        else if (first_cyc)  sda_en <= busy_r && (
-                                     (active_sda && (seq_start_restart[3] || seq_stop[0] || (sr[8] && seq_bit[3]))) ||
+//        else if (first_cyc)  sda_en <= busy_r && (
+// TODO: no active SDA if previous SDA was 1
+        else if (first_cyc)  sda_en <= busy_w && (
+                                     (active_sda_r && active_sda_was_0 && (seq_start_restart[3] || seq_stop[0] || (sr[8] && seq_bit[3]))) || // !sda uses output reg
                                     (|seq_start_restart[1:0]) ||
                                     (|seq_stop[2:1]) ||
                                     (!sr[8] && (|seq_bit[3:1])) ||

--- a/sensor/sensors393.v
+++ b/sensor/sensors393.v
@@ -64,6 +64,20 @@ module  sensors393 #(
        parameter SENSI2C_CMD_ACIVE_EARLY0 = 1, // release SDA==0 early if next bit ==1
        parameter SENSI2C_CMD_ACIVE_SDA =    0,  // drive SDA=1 during the second half of SCL=1

+    //i2c page table bit fields
+        parameter SENSI2C_TBL_RAH =          0, // high byte of the register address 
+        parameter SENSI2C_TBL_RAH_BITS =     8,
+        parameter SENSI2C_TBL_RNWREG =       8, // read register (when 0 - write register
+        parameter SENSI2C_TBL_SA =           9, // Slave address in write mode
+        parameter SENSI2C_TBL_SA_BITS =      7,
+        parameter SENSI2C_TBL_NBWR =        16, // number of bytes to write (1..10)
+        parameter SENSI2C_TBL_NBWR_BITS =    4,
+        parameter SENSI2C_TBL_NBRD =        16, // number of bytes to read (1 - 8) "0" means "8"
+        parameter SENSI2C_TBL_NBRD_BITS =    3,
+        parameter SENSI2C_TBL_NABRD =       19, // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
+        parameter SENSI2C_TBL_DLY =         20, // bit delay (number of mclk periods in 1/4 of SCL period)
+        parameter SENSI2C_TBL_DLY_BITS=      8,
+
      parameter SENSI2C_STATUS =        'h1,
    
    parameter SENS_SYNC_RADDR  =        'h4,
@@ -386,6 +400,18 @@ module  sensors393 #(
                .SENSI2C_CMD_ACIVE             (SENSI2C_CMD_ACIVE),
                .SENSI2C_CMD_ACIVE_EARLY0      (SENSI2C_CMD_ACIVE_EARLY0),
                .SENSI2C_CMD_ACIVE_SDA         (SENSI2C_CMD_ACIVE_SDA),
+                .SENSI2C_TBL_RAH               (SENSI2C_TBL_RAH), // high byte of the register address 
+                .SENSI2C_TBL_RAH_BITS          (SENSI2C_TBL_RAH_BITS),
+                .SENSI2C_TBL_RNWREG            (SENSI2C_TBL_RNWREG), // read register (when 0 - write register
+                .SENSI2C_TBL_SA                (SENSI2C_TBL_SA), // Slave address in write mode
+                .SENSI2C_TBL_SA_BITS           (SENSI2C_TBL_SA_BITS),
+                .SENSI2C_TBL_NBWR              (SENSI2C_TBL_NBWR), // number of bytes to write (1..10)
+                .SENSI2C_TBL_NBWR_BITS         (SENSI2C_TBL_NBWR_BITS),
+                .SENSI2C_TBL_NBRD              (SENSI2C_TBL_NBRD), // number of bytes to read (1 - 8) "0" means "8"
+                .SENSI2C_TBL_NBRD_BITS         (SENSI2C_TBL_NBRD_BITS),
+                .SENSI2C_TBL_NABRD             (SENSI2C_TBL_NABRD), // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
+                .SENSI2C_TBL_DLY               (SENSI2C_TBL_DLY),   // bit delay (number of mclk periods in 1/4 of SCL period)
+                .SENSI2C_TBL_DLY_BITS          (SENSI2C_TBL_DLY_BITS),
                .SENSI2C_STATUS                (SENSI2C_STATUS),
                .SENS_GAMMA_RADDR              (SENS_GAMMA_RADDR),
                .SENS_GAMMA_ADDR_MASK          (SENS_GAMMA_ADDR_MASK),

--- a/x393.v
+++ b/x393.v
@@ -1431,6 +1431,18 @@ assign axi_grst = axi_rst_pre;
        .SENSI2C_CMD_ACIVE          (SENSI2C_CMD_ACIVE),
        .SENSI2C_CMD_ACIVE_EARLY0   (SENSI2C_CMD_ACIVE_EARLY0),
        .SENSI2C_CMD_ACIVE_SDA      (SENSI2C_CMD_ACIVE_SDA),
+        .SENSI2C_TBL_RAH            (SENSI2C_TBL_RAH),      // high byte of the register address 
+        .SENSI2C_TBL_RAH_BITS       (SENSI2C_TBL_RAH_BITS),
+        .SENSI2C_TBL_RNWREG         (SENSI2C_TBL_RNWREG),   // read register (when 0 - write register
+        .SENSI2C_TBL_SA             (SENSI2C_TBL_SA),       // Slave address in write mode
+        .SENSI2C_TBL_SA_BITS        (SENSI2C_TBL_SA_BITS),
+        .SENSI2C_TBL_NBWR           (SENSI2C_TBL_NBWR),     // number of bytes to write (1..10)
+        .SENSI2C_TBL_NBWR_BITS      (SENSI2C_TBL_NBWR_BITS),
+        .SENSI2C_TBL_NBRD           (SENSI2C_TBL_NBRD),     // number of bytes to read (1 - 8) "0" means "8"
+        .SENSI2C_TBL_NBRD_BITS      (SENSI2C_TBL_NBRD_BITS),
+        .SENSI2C_TBL_NABRD          (SENSI2C_TBL_NABRD),    // number of address bytes for read (0 - 1 byte, 1 - 2 bytes)
+        .SENSI2C_TBL_DLY            (SENSI2C_TBL_DLY),      // bit delay (number of mclk periods in 1/4 of SCL period)
+        .SENSI2C_TBL_DLY_BITS       (SENSI2C_TBL_DLY_BITS),
        .SENSI2C_STATUS             (SENSI2C_STATUS),
        .SENS_SYNC_RADDR            (SENS_SYNC_RADDR),
        .SENS_SYNC_MASK             (SENS_SYNC_MASK),

--- a/x393_testbench02.sav
+++ b/x393_testbench02.sav
 [*]
 [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
-[*] Tue Oct  6 05:07:11 2015
+[*] Fri Oct  9 02:08:25 2015
 [*]
-[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench02-20151005131204826.fst"
-[dumpfile_mtime] "Mon Oct  5 19:34:17 2015"
-[dumpfile_size] 84326452
+[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench02-20151008192535819.fst"
+[dumpfile_mtime] "Fri Oct  9 02:02:14 2015"
+[dumpfile_size] 165875504
 [savefile] "/home/andrey/git/x393/x393_testbench02.sav"
-[timestart] 73479300
+[timestart] 0
 [size] 1823 1180
 [pos] 1922 0
-*-15.146479 73577388 102872500 116192500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-25.015932 71267388 102872500 116192500 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] x393_testbench02.
 [treeopen] x393_testbench02.compressor_control.
 [treeopen] x393_testbench02.simul_axi_hp1_wr_i.
@@ -67,7 +67,6 @@
 [treeopen] x393_testbench02.x393_i.sensors393_i.histogram_saxi_i.
 [treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].
 [treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
-[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.
 [treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.
 [treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk7.sens_histogram_i.
 [treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.pxd_block[2].
@@ -75,6 +74,8 @@
 [treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_fifo_i.hact_dly_16_i.bit_block[0].
 [treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.
 [treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.
+[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.
+[treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.
 [treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.
 [treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
 [treeopen] x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.lens_flat393_i.
@@ -93,8 +94,8 @@
 [treeopen] x393_testbench02.x393_i.timing393_i.
 [treeopen] x393_testbench02.x393_i.timing393_i.camsync393_i.
 [treeopen] x393_testbench02.x393_i.timing393_i.rtc393_i.
-[sst_width] 353
-[signals_width] 345
+[sst_width] 324
+[signals_width] 359
 [sst_expanded] 1
 [sst_vpaned_height] 611
 @820
@@ -186,7 +187,7 @@ x393_testbench02.TEST_TITLE[639:0]
 -
 @1401200
 -debug_ring
-@800200
+@c00200
 -PX1
 @28
 x393_testbench02.simul_sensor12bits_i.MRST
@@ -218,7 +219,7 @@ x393_testbench02.simul_sensor12bits_i.ARO
 x393_testbench02.simul_sensor12bits_i.DCLK
 @28
 x393_testbench02.simul_sensor12bits_i.OFST
-@1000200
+@1401200
 -PX1
 @c00200
 -PX2
@@ -249,7 +250,7 @@ x393_testbench02.simul_sensor12bits_3_i.DCLK
 -
 @1401200
 -PX3
-@800200
+@c00200
 -PX4
 @28
 x393_testbench02.simul_sensor12bits_4_i.MRST
@@ -263,7 +264,7 @@ x393_testbench02.simul_sensor12bits_4_i.ARO
 x393_testbench02.simul_sensor12bits_4_i.DCLK
 @200
 -
-@1000200
+@1401200
 -PX4
 @c00200
 -sensor_channel
@@ -379,8 +380,6 @@ x393_testbench02.x393_i.sns1_dn[7:0]
 @c00200
 -set_sensor_i2c_command
 @22
-x393_testbench02.set_sensor_i2c_command.bytes[1:0]
-x393_testbench02.set_sensor_i2c_command.dly[7:0]
 x393_testbench02.set_sensor_i2c_command.num_sensor[1:0]
 x393_testbench02.set_sensor_i2c_command.rst_cmd
 @800022
@@ -391,10 +390,6 @@ x393_testbench02.set_sensor_i2c_command.run_cmd[1:0]
 @1001200
 -group_end
 @22
-x393_testbench02.set_sensor_i2c_command.scl_ctl[1:0]
-x393_testbench02.set_sensor_i2c_command.sda_ctl[1:0]
-x393_testbench02.set_sensor_i2c_command.set_bytes
-x393_testbench02.set_sensor_i2c_command.set_dly
 x393_testbench02.set_sensor_i2c_command.tmp[31:0]
 @1401200
 -set_sensor_i2c_command
@@ -453,7 +448,6 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
 @28
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_start
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_run
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_done
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.scl_in
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_in
 @200
@@ -471,21 +465,12 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
 -group_end
 @22
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.byte_number[1:0]
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.byte_sending[1:0]
-@28
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.bytes_cmd
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.bytes_left[1:0]
-@22
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.cmd_ad[7:0]
 @28
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.cmd_stb
 @22
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.di[31:0]
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.di_r[31:0]
-@28
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.dly_cmd
-@22
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.dly_cntr[7:0]
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.fifo_wr_pointers_outr[5:0]
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.fifo_wr_pointers_outr_r[5:0]
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.fifo_wr_pointers_outw[5:0]
@@ -493,9 +478,6 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.frame_num[3:0]
 @28
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.frame_sync
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_bit_last
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_byte_start[2:0]
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_bytes[1:0]
 @22
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_cmd_wa[9:0]
 @28
@@ -503,32 +485,9 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
 @22
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_data[7:0]
 @28
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_dataseq_done
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_dataseq_last
-@22
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_dly[7:0]
-@28
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_dly_over
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_dly_pre2_over
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_dly_pre_over
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_done
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_enrun
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_is_ackn
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_is_data
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_is_start
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_is_stop
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_run
-@22
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_sr[8:0]
-@28
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_sr_shift
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_start
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_startseq_last
-@22
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_state[5:0]
-@28
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_stop_start
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_stopseq_last
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.mclk
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.mrst
 @22
@@ -543,21 +502,12 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.rpointer[5:0]
 @28
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.run_cmd
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.scl_0
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.scl_en
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.scl_en_soft
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.scl_hard
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.scl_in
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.scl_out
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.scl_soft
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_0
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_en
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_en_hard
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_en_soft
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_hard
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_in
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_out
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_soft
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.set_ctrl_w
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.set_status_w
 @22
@@ -970,17 +920,8 @@ x393_testbench02.x393_i.membridge_i.read_busy
 -membridge_select
 @800200
 -DDR3
-@28
-x393_testbench02.SDCLK
 @22
 x393_testbench02.SDCAS
-x393_testbench02.SDRAS
-x393_testbench02.SDWE
-x393_testbench02.SDBA[2:0]
-x393_testbench02.SDA[14:0]
-x393_testbench02.SDD[15:0]
-@28
-x393_testbench02.DQSU
 @1000200
 -DDR3
 @c00200
@@ -3911,84 +3852,444 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.frame_sync
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.mclk
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.mrst
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sda
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.scl
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.scl_en
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.scl_in
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.scl_out
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sda
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sda_en
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sda_in
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sda_out
 @22
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.status_ad[7:0]
 @28
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.status_rq
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.status_start
 @800200
+-chn0
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sda_in
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sda_en
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sda_out
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.scl_out
+@1000200
+-chn0
+@800200
+-chn1
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sda_in
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sda_en
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.sda_out
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sensor_i2c_io_i.scl_out
+@1000200
+-chn1
+@800200
+-chn2
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sensor_i2c_io_i.sda_in
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sensor_i2c_io_i.sda_en
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sensor_i2c_io_i.sda_out
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sensor_i2c_io_i.scl_out
+@1000200
+-chn2
+@800201
+-chn3
+@29
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sensor_i2c_io_i.sda_in
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sensor_i2c_io_i.sda_en
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sensor_i2c_io_i.sda_out
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sensor_i2c_io_i.scl_out
+@1000201
+-chn3
+@200
+-
+@800200
 -sens_i2c_selected
 @28
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.mclk
-@22
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_dly[7:0]
-@28
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_start
-@29
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_run
-@28
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_done
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.busy
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.scl_out
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.scl_en
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_out
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_en
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.run_cmd
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.rpointer[5:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.fifo_wr_pointers_outr_r[5:0]
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_start
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.page_r_inc[1:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_run
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_enrun
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.wpage_wr[3:0]
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.we_fifo_wp
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.fifo_wr_pointers_outr[5:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.page_r[3:0]
 @200
 -i2c sequence
+-
+@800200
+-task_set_sensor_i2c_cmd
+@28
+x393_testbench02.set_sensor_i2c_command.active_sda
+x393_testbench02.set_sensor_i2c_command.early_release_0
 @22
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.bytes_left[1:0]
+x393_testbench02.set_sensor_i2c_command.num_sensor[1:0]
 @28
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_startseq_last
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_stopseq_last
-@800028
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_byte_start[2:0]
+x393_testbench02.set_sensor_i2c_command.rst_cmd
+@22
+x393_testbench02.set_sensor_i2c_command.run_cmd[1:0]
 @28
-(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_byte_start[2:0]
-(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_byte_start[2:0]
-(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_byte_start[2:0]
+x393_testbench02.set_sensor_i2c_command.set_active
+@22
+x393_testbench02.set_sensor_i2c_command.tmp[31:0]
+@1000200
+-task_set_sensor_i2c_cmd
+@200
+-
+@1000200
+-sens_i2c_selected
+@800200
+-sens_i2c
+-i2c_prot_sel
 @800022
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_state[5:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.mem_re[2:0]
+@28
+(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.mem_re[2:0]
+(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.mem_re[2:0]
+(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.mem_re[2:0]
+@1001200
+-group_end
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.i2c_start
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.start_extra_seq_w
+@c00022
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_extra_wr[4:0]
 @28
-(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_state[5:0]
-(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_state[5:0]
-(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_state[5:0]
-(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_state[5:0]
-(4)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_state[5:0]
-(5)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_state[5:0]
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_dly_over
+(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_extra_wr[4:0]
+(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_extra_wr[4:0]
+(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_extra_wr[4:0]
+(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_extra_wr[4:0]
+(4)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_extra_wr[4:0]
+@1401200
+-group_end
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_extra_wr_d
 @22
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_dly[7:0]
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_data[7:0]
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_sr[8:0]
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.byte_number[1:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.seq_mem_ra[1:0]
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.pre_table_re
+@800022
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.table_re[3:0]
+@28
+(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.table_re[3:0]
+(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.table_re[3:0]
+(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.table_re[3:0]
+(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.table_re[3:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.snd9
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.i2c_rdy
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.next_cmd
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.next_byte_wr
 @1001200
 -group_end
+@c00022
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_wr[6:0]
+@28
+(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_wr[6:0]
+(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_wr[6:0]
+(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_wr[6:0]
+(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_wr[6:0]
+(4)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_wr[6:0]
+(5)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_wr[6:0]
+(6)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_wr[6:0]
+@1401200
+-group_end
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_extra_wr_d
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.start_rd_seq_w
+@800022
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_rd[7:0]
+@28
+(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_rd[7:0]
+(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_rd[7:0]
+(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_rd[7:0]
+(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_rd[7:0]
+(4)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_rd[7:0]
+(5)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_rd[7:0]
+(6)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_rd[7:0]
+(7)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_rd[7:0]
+@1001200
 -group_end
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.start_wr_seq_w
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.slave_a_rah[7:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.rd_sa[6:0]
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.send_rd_sa
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sr_in[8:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.num_bytes_send[3:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.bytes_left_send[3:0]
 @200
 -
-
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sda
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.scl
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sda_en
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sda_in
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.pre_next_cmd
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.next_cmd
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.next_cmd_d
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.snd9
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.i2c_rdy
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.send_seq_data
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.send_rd_sa
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.send_sa_rah
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.send_rd
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sel_sr_in[1:0]
 @1000200
-sens_i2c_selected
+-i2c_prot_sel
+@c00200
+-sensor_i2c_prot
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.active_sda
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.bus_busy
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.bus_open
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.bytes_left_send[3:0]
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.early_release_0
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.i2c_busy
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.i2c_dly[7:0]
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.i2c_rdy
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.i2c_rst
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.i2c_run
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.i2c_start
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.initial_address[1:0]
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.initial_address_w[3:0]
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.mclk
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.mem_re[2:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.mem_valid
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.mrst
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.next_byte_wr
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.next_cmd
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.next_cmd_d
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.num_bytes_send[3:0]
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.pre_cmd[1:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.pre_next_cmd
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.pre_table_re
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.rd_sa[6:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.rdata[7:0]
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.read_address_bytes
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.read_data_bytes[2:0]
+@22
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+@28
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+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_extra_wr[4:0]
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_extra_wr_d
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_rd[7:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.run_reg_wr[6:0]
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.rvalid
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.scl
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sda
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sda_en
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sda_in
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sel_sr_in[1:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.send_rd
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.send_rd_sa
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.send_sa_rah
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.send_seq_data
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.seq_mem_ra[1:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.seq_mem_re[1:0]
+@22
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+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.slave_a_rah[7:0]
+@28
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+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.snd_start
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.snd_stop
+@22
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+@28
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+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.start_rd_seq_w
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.start_wr_seq_w
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.table_re[3:0]
+@28
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+@22
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+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.tdout[31:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.twa[7:0]
+@28
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+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.unused
+@1401200
+-sensor_i2c_prot
 @800200
-sens_i2c
+-scl_sda_selected
+@28
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+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.dly_over
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.snd_start
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.snd_start_w
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.snd9
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.snd9_w
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.snd_stop
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.snd_stop_w
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.busy_w
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.ready
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.done_r
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.busy_r
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.rcv
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.active_sda_was_0
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.active_sda_r
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.din[8:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sr[8:0]
+@c00022
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
+@28
+(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
+(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
+(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
+(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
+@1401200
+-group_end
 @28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.first_cyc
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.bus_busy
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sda_en
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sda
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.scl
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.is_open
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.is_open_r
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.i2c_dly[7:0]
+@c00022
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.bits_left[3:0]
+@28
+(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.bits_left[3:0]
+(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.bits_left[3:0]
+(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.bits_left[3:0]
+(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.bits_left[3:0]
+@1401200
+-group_end
+@800022
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_stop[2:0]
+@28
+(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_stop[2:0]
+(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_stop[2:0]
+(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_stop[2:0]
+@1001200
+-group_end
+@800022
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
+@28
+(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
+(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
+(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
+(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.bits_left[3:0]
+@1001200
+-group_end
+@800022
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_start_restart[3:0]
+@28
+(0)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_start_restart[3:0]
+(1)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_start_restart[3:0]
+(2)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_start_restart[3:0]
+(3)x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_start_restart[3:0]
+@1001200
+-group_end
+@1000200
+-scl_sda_selected
+@800200
+-scl_sda
+@200
+-
+@28
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+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.bits_left[3:0]
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.bus_busy
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.busy_r
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.din[8:0]
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.dly_over
+@22
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+@28
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+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.done_r
+@22
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+@28
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+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.early_release_0
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.first_cyc
+@22
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+@28
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+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.is_open
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.is_open_r
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.mclk
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.mrst
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.pre_dly_over
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.ready
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.rst
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.scl
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sda
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sda_en
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sda_in
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sda_r
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_bit[3:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.seq_start_restart[3:0]
+@28
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+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.snd9
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.snd9_w
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.snd_start
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.snd_start_w
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.snd_stop
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.snd_stop_w
+@22
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.sr[8:0]
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sensor_i2c_prot_i.sensor_i2c_scl_sda_i.start_w
+@1000200
+-scl_sda
+@28
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.active_cmd
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.active_sda
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.alive_fs
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.busy
 @22
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.busy_cntr[3:0]
 @28
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.byte_number[1:0]
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.byte_sending[1:0]
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.bytes_cmd
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.bytes_left[1:0]
 @22
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.cmd_ad[7:0]
 @28
@@ -3997,9 +4298,8 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.di[31:0]
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.di_r[31:0]
 @28
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.dly_cmd
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.early_release_0
 @22
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.dly_cntr[7:0]
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.fifo_wr_pointers_outr[5:0]
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.fifo_wr_pointers_outr_r[5:0]
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.fifo_wr_pointers_outw[5:0]
@@ -4007,9 +4307,6 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.frame_num[3:0]
 @28
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.frame_sync
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_bit_last
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_byte_start[2:0]
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_bytes[1:0]
 @22
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_cmd_wa[9:0]
 @28
@@ -4017,32 +4314,20 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
 @22
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_data[7:0]
 @28
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_dataseq_done
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_dataseq_last
-@22
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_dly[7:0]
-@28
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_dly_over
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_dly_pre2_over
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_dly_pre_over
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_done
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_enrun
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_is_ackn
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_is_data
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_is_start
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_is_stop
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_run
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_fifo_cntrl
 @22
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_sr[8:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_fifo_dout[7:0]
 @28
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_sr_shift
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_start
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_startseq_last
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_fifo_nempty
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_fifo_rd
 @22
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_state[5:0]
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_rdata[7:0]
 @28
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_stop_start
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_stopseq_last
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_run
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_run_d
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_rvalid
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.i2c_start
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.mclk
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.mrst
 @22
@@ -4057,21 +4342,13 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.rpointer[5:0]
 @28
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.run_cmd
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.scl_0
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.scl_en
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.scl_en_soft
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.scl_hard
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.scl_in
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.scl_out
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.scl_soft
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_0
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_en
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_en_hard
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_en_soft
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_hard
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_in
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_out
-x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.sda_soft
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.seq_mem_re[1:0]
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.set_ctrl_w
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.set_status_w
 @22
@@ -4079,6 +4356,7 @@ x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
 @28
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.status_rq
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.status_start
+x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.twe
 @22
 x393_testbench02.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.wa[3:0]
 @28

--- a/x393_testbench02.tf
+++ b/x393_testbench02.tf
@@ -948,48 +948,92 @@ assign #10 gpio_pins[9] = gpio_pins[8];
            0,   // input                             [1:0] num_sensor;
            1'b1,   // input                                   rst_cmd;    // [14]   reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
            2'b0,   // input       [SENSI2C_CMD_RUN_PBITS : 0] run_cmd;    // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
-            1'b1,   // input                                   set_bytes;  // [11] if 1, use bytes (below), 0 - nop
-            2'h3,   // input  [SENSI2C_CMD_BYTES_PBITS -1 : 0] bytes;      // [10:9] set command bytes to send after slave address (0..3)
-            1'b1,   // input                                   set_dly;    // [8] if 1, use dly (0 - ignore)
-            8'h02, //a,  // input   [SENSI2C_CMD_DLY_PBITS - 1 : 0] dly;        // [7:0]  - duration of quarter i2c cycle (if 0, [3:0] control SCL+SDA)
-            2'b0,   // input    [SENSI2C_CMD_SCL_WIDTH -1 : 0] scl_ctl;    // [1:0] : 0: NOP, 1: 1'b0->SCL, 2: 1'b1->SCL, 3: 1'bz -> SCL 
-            2'b0);  // input    [SENSI2C_CMD_SDA_WIDTH -1 : 0] sda_ctl;    // [3:2] : 0: NOP, 1: 1'b0->SDA, 2: 1'b1->SDA, 3: 1'bz -> SDA  
+            1'b1,   // input                                   set_active; 
+            1'b1,   // input                                   active_sda; 
+            1'b1);  // input                                   early_release_0;
+        set_sensor_i2c_table_reg_wr(
+            0,     // input                             [1:0] num_sensor;
+            8'h90, // input                             [7:0] page;       // set parameters for 32-bit command with this MSB
+            7'h48, // input                             [6:0] slave_addr; // 7-bit slave address
+            8'h0,  // input                             [7:0] rah;        // register address high byte
+            4'h3,  // input                             [3:0] num_bytes;  // number of bytes to send
+            8'h4); // input                             [7:0] bit_delay;
+        set_sensor_i2c_table_reg_rd(
+            0,     // input                             [1:0] num_sensor;
+            8'h91, // input                             [7:0] page;       // set parameters for 32-bit command with this MSB
+            1'b0,  // input                                   num_bytes_addr; // number of address bytes (0 - 1, 1 - 2)
+            3'h2,  // input                             [2:0] num_bytes_rd;  // number of bytes to read, with "0" meaning all 8
+            8'h5); // input                             [7:0] bit_delay;
+
+             
    TEST_TITLE = "RESEST_I2C_SEQUENCER1";
    $display("===================== TEST_%s =========================",TEST_TITLE);
        set_sensor_i2c_command(
            1,   // input                             [1:0] num_sensor;
            1'b1,   // input                                   rst_cmd;    // [14]   reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
            2'b0,   // input       [SENSI2C_CMD_RUN_PBITS : 0] run_cmd;    // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
-            1'b1,   // input                                   set_bytes;  // [11] if 1, use bytes (below), 0 - nop
-            2'h3,   // input  [SENSI2C_CMD_BYTES_PBITS -1 : 0] bytes;      // [10:9] set command bytes to send after slave address (0..3)
-            1'b1,   // input                                   set_dly;    // [8] if 1, use dly (0 - ignore)
-            8'h02, //a,  // input   [SENSI2C_CMD_DLY_PBITS - 1 : 0] dly;        // [7:0]  - duration of quarter i2c cycle (if 0, [3:0] control SCL+SDA)
-            2'b0,   // input    [SENSI2C_CMD_SCL_WIDTH -1 : 0] scl_ctl;    // [1:0] : 0: NOP, 1: 1'b0->SCL, 2: 1'b1->SCL, 3: 1'bz -> SCL 
-            2'b0);  // input    [SENSI2C_CMD_SDA_WIDTH -1 : 0] sda_ctl;    // [3:2] : 0: NOP, 1: 1'b0->SDA, 2: 1'b1->SDA, 3: 1'bz -> SDA  
+            1'b1,   // input                                   set_active; 
+            1'b0,   // input                                   active_sda; 
+            1'b1);  // input                                   early_release_0; 
+        set_sensor_i2c_table_reg_wr(
+            1,     // input                             [1:0] num_sensor;
+            8'h90, // input                             [7:0] page;       // set parameters for 32-bit command with this MSB
+            7'h48, // input                             [6:0] slave_addr; // 7-bit slave address
+            8'h12, // input                             [7:0] rah;        // register address high byte
+            4'ha,  // input                             [3:0] num_bytes;  // number of bytes to send
+            8'h4); // input                             [7:0] bit_delay;
+        set_sensor_i2c_table_reg_rd(
+            1,     // input                             [1:0] num_sensor;
+            8'h91, // input                             [7:0] page;       // set parameters for 32-bit command with this MSB
+            1'b1,  // input                                   num_bytes_addr; // number of address bytes (0 - 1, 1 - 2)
+            3'h0,  // input                             [2:0] num_bytes_rd;  // number of bytes to read, with "0" meaning all 8
+            8'h4); // input                             [7:0] bit_delay;
+
    TEST_TITLE = "RESEST_I2C_SEQUENCER2";
    $display("===================== TEST_%s =========================",TEST_TITLE);
        set_sensor_i2c_command(
            2,   // input                             [1:0] num_sensor;
            1'b1,   // input                                   rst_cmd;    // [14]   reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
            2'b0,   // input       [SENSI2C_CMD_RUN_PBITS : 0] run_cmd;    // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
-            1'b1,   // input                                   set_bytes;  // [11] if 1, use bytes (below), 0 - nop
-            2'h3,   // input  [SENSI2C_CMD_BYTES_PBITS -1 : 0] bytes;      // [10:9] set command bytes to send after slave address (0..3)
-            1'b1,   // input                                   set_dly;    // [8] if 1, use dly (0 - ignore)
-            8'h02, //a,  // input   [SENSI2C_CMD_DLY_PBITS - 1 : 0] dly;        // [7:0]  - duration of quarter i2c cycle (if 0, [3:0] control SCL+SDA)
-            2'b0,   // input    [SENSI2C_CMD_SCL_WIDTH -1 : 0] scl_ctl;    // [1:0] : 0: NOP, 1: 1'b0->SCL, 2: 1'b1->SCL, 3: 1'bz -> SCL 
-            2'b0);  // input    [SENSI2C_CMD_SDA_WIDTH -1 : 0] sda_ctl;    // [3:2] : 0: NOP, 1: 1'b0->SDA, 2: 1'b1->SDA, 3: 1'bz -> SDA  
+            1'b1,   // input                                   set_active; 
+            1'b1,   // input                                   active_sda; 
+            1'b0);  // input                                   early_release_0; 
+        set_sensor_i2c_table_reg_wr(
+            2,     // input                             [1:0] num_sensor;
+            8'h90, // input                             [7:0] page;       // set parameters for 32-bit command with this MSB
+            7'h48, // input                             [6:0] slave_addr; // 7-bit slave address
+            8'h34, // input                             [7:0] rah;        // register address high byte
+            4'h4,  // input                             [3:0] num_bytes;  // number of bytes to send
+            8'h4); // input                             [7:0] bit_delay;
+        set_sensor_i2c_table_reg_rd(
+            2,     // input                             [1:0] num_sensor;
+            8'h91, // input                             [7:0] page;       // set parameters for 32-bit command with this MSB
+            1'b1,  // input                                   num_bytes_addr; // number of address bytes (0 - 1, 1 - 2)
+            3'h2,  // input                             [2:0] num_bytes_rd;  // number of bytes to read, with "0" meaning all 8
+            8'h4); // input                             [7:0] bit_delay;
+
    TEST_TITLE = "RESEST_I2C_SEQUENCER3";
    $display("===================== TEST_%s =========================",TEST_TITLE);
        set_sensor_i2c_command(
            3,   // input                             [1:0] num_sensor;
            1'b1,   // input                                   rst_cmd;    // [14]   reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
            2'b0,   // input       [SENSI2C_CMD_RUN_PBITS : 0] run_cmd;    // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
-            1'b1,   // input                                   set_bytes;  // [11] if 1, use bytes (below), 0 - nop
-            2'h3,   // input  [SENSI2C_CMD_BYTES_PBITS -1 : 0] bytes;      // [10:9] set command bytes to send after slave address (0..3)
-            1'b1,   // input                                   set_dly;    // [8] if 1, use dly (0 - ignore)
-            8'h02, //a,  // input   [SENSI2C_CMD_DLY_PBITS - 1 : 0] dly;        // [7:0]  - duration of quarter i2c cycle (if 0, [3:0] control SCL+SDA)
-            2'b0,   // input    [SENSI2C_CMD_SCL_WIDTH -1 : 0] scl_ctl;    // [1:0] : 0: NOP, 1: 1'b0->SCL, 2: 1'b1->SCL, 3: 1'bz -> SCL 
-            2'b0);  // input    [SENSI2C_CMD_SDA_WIDTH -1 : 0] sda_ctl;    // [3:2] : 0: NOP, 1: 1'b0->SDA, 2: 1'b1->SDA, 3: 1'bz -> SDA  
+            1'b1,   // input                                   set_active; 
+            1'b0,   // input                                   active_sda; 
+            1'b0);  // input                                   early_release_0; 
+        set_sensor_i2c_table_reg_wr(
+            3,     // input                             [1:0] num_sensor;
+            8'h90, // input                             [7:0] page;       // set parameters for 32-bit command with this MSB
+            7'h48, // input                             [6:0] slave_addr; // 7-bit slave address
+            8'h0,  // input                             [7:0] rah;        // register address high byte
+            4'h2,  // input                             [3:0] num_bytes;  // number of bytes to send
+            8'h5); // input                             [7:0] bit_delay;
+        set_sensor_i2c_table_reg_rd(
+            3,     // input                             [1:0] num_sensor;
+            8'h91, // input                             [7:0] page;       // set parameters for 32-bit command with this MSB
+            1'b0,  // input                                   num_bytes_addr; // number of address bytes (0 - 1, 1 - 2)
+            3'h1,  // input                             [2:0] num_bytes_rd;  // number of bytes to read, with "0" meaning all 8
+            8'h5); // input                             [7:0] bit_delay;

    TEST_TITLE = "DELAY_FOR_I2C_RESET";
    $display("===================== TEST_%s =========================",TEST_TITLE);
@@ -2415,8 +2459,12 @@ task setup_sensor_channel;
            QUADRANTS_PXD_HACT_VACT); // data-0, hact - 1, vact - 2 input  [SENS_CTRL_QUADRANTS_WIDTH-1:0] quadrants;  // 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
    TEST_TITLE = "I2C_TEST";
    $display("===================== TEST_%s =========================",TEST_TITLE);
-
-        test_i2c_353 (num_sensor); // test soft/sequencer i2c
+        case (num_sensor)
+        2'h0: test_i2c_353 (num_sensor,0); // test soft/sequencer i2c
+        2'h1: test_i2c_353 (num_sensor,2); // test soft/sequencer i2c
+        2'h2: test_i2c_353 (num_sensor,0); // test soft/sequencer i2c
+        2'h3: test_i2c_353 (num_sensor,0); // test soft/sequencer i2c
+        endcase
        
    TEST_TITLE = "LENS_FLAT_SETUP";
    $display("===================== TEST_%s =========================",TEST_TITLE);
@@ -2855,48 +2903,37 @@ endtask

 task test_i2c_353;
    input [1:0] chn;
+    input integer num_extra;
+    integer i;
    begin
    // Reset moved out, done for all channels, then 1 usec delay
-    /*
-        set_sensor_i2c_command(
-            chn,   // input                             [1:0] num_sensor;
-            1'b1,   // input                                   rst_cmd;    // [14]   reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
-            2'b0,   // input       [SENSI2C_CMD_RUN_PBITS : 0] run_cmd;    // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
-            1'b1,   // input                                   set_bytes;  // [11] if 1, use bytes (below), 0 - nop
-            2'h3,   // input  [SENSI2C_CMD_BYTES_PBITS -1 : 0] bytes;      // [10:9] set command bytes to send after slave address (0..3)
-            1'b1,   // input                                   set_dly;    // [8] if 1, use dly (0 - ignore)
-            8'h0a,  // input   [SENSI2C_CMD_DLY_PBITS - 1 : 0] dly;        // [7:0]  - duration of quarter i2c cycle (if 0, [3:0] control SCL+SDA)
-            2'b0,   // input    [SENSI2C_CMD_SCL_WIDTH -1 : 0] scl_ctl;    // [1:0] : 0: NOP, 1: 1'b0->SCL, 2: 1'b1->SCL, 3: 1'bz -> SCL 
-            2'b0);  // input    [SENSI2C_CMD_SDA_WIDTH -1 : 0] sda_ctl;    // [3:2] : 0: NOP, 1: 1'b0->SDA, 2: 1'b1->SDA, 3: 1'bz -> SDA  
-        repeat (10) @ (posedge CLK); // wait for initialization to be done TODO: use status
-        */
-        set_sensor_i2c_command (chn, 0, 3, 0, 0, 0, 0, 0, 0); // run i2c - reset software bits
-        set_sensor_i2c_command (chn, 0, 2, 0, 0, 0, 0, 0, 0); // stop i2c, enable software control
-
-        set_sensor_i2c_command (chn, 0, 0, 0, 0, 0, 0, 0, 2); // SDA = 1 
-        set_sensor_i2c_command (chn, 0, 0, 0, 0, 0, 0, 0, 1); // SDA = 0
-        set_sensor_i2c_command (chn, 0, 0, 0, 0, 0, 0, 2, 0); // SCL = 1 
-        set_sensor_i2c_command (chn, 0, 0, 0, 0, 0, 0, 1, 0); // SCL = 0 
-        set_sensor_i2c_command (chn, 0, 0, 0, 0, 0, 0, 0, 2); // SDA = 1 
-        set_sensor_i2c_command (chn, 0, 0, 0, 0, 0, 0, 2, 0); // SCL = 1 
-        set_sensor_i2c_command (chn, 0, 0, 0, 0, 0, 0, 0, 3); // SDA = 'bz 
-        set_sensor_i2c_command (chn, 0, 0, 0, 0, 0, 0, 3, 0); // SCL = 'bz 
-
-        set_sensor_i2c_command (chn, 0, 3, 0, 0, 0, 0, 0, 0); // run i2c
+        set_sensor_i2c_command (chn, 0, 3, 0, 0, 0); // run i2c
+        write_sensor_i2c (chn, 1, 0,'h90050922);
+        for (i=0; i<num_extra; i=i+1) write_sensor_i2c (chn, 1, 0, i+ 'h12);
+        write_sensor_i2c (chn, 1, 0,'h91123456);
+
        write_sensor_i2c (
            chn,           // input   [1:0] num_sensor;
            0,           // input         rel_addr; // 0 - absolute, 1 - relative
            1,           // input integer addr;
            'h90040793); // input  [31:0] data;
-                    
+        for (i=0; i<num_extra; i=i+1) write_sensor_i2c (chn, 0, 1, i+ 'h1);
        write_sensor_i2c (chn, 0, 1,'h90050a23);
+        for (i=0; i<num_extra; i=i+1) write_sensor_i2c (chn, 0, 1, i+ 'h123);
        write_sensor_i2c (chn, 0, 2,'h90080001);        
+        for (i=0; i<num_extra; i=i+1) write_sensor_i2c (chn, 0, 2, i+ 'h1234);
        write_sensor_i2c (chn, 0, 3,'h90090123);        
+        for (i=0; i<num_extra; i=i+1) write_sensor_i2c (chn, 0, 3, i+ 'h12345);
        write_sensor_i2c (chn, 1, 2,'h90091234);        
+        for (i=0; i<num_extra; i=i+1) write_sensor_i2c (chn, 1, 2, i+ 'h123456);
        write_sensor_i2c (chn, 0, 4,'h9004001f);        
+        for (i=0; i<num_extra; i=i+1) write_sensor_i2c (chn, 0, 4, i+ 'h1234567);
        write_sensor_i2c (chn, 0, 4,'h9005002f);        
+        for (i=0; i<num_extra; i=i+1) write_sensor_i2c (chn, 0, 4, i+ 'h12345678);
        write_sensor_i2c (chn, 1, 3,'h90020013);        
+        for (i=0; i<num_extra; i=i+1) write_sensor_i2c (chn, 1, 3, i+ 'h4567);
        write_sensor_i2c (chn, 1, 3,'h90030017);        
+        for (i=0; i<num_extra; i=i+1) write_sensor_i2c (chn, 1, 3, i+ 'h456789);
    
    end
 endtask
@@ -3021,19 +3058,63 @@ task set_sensor_i2c_command;
    input                             [1:0] num_sensor;
    input                                   rst_cmd;    // [14]   reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
    input       [SENSI2C_CMD_RUN_PBITS : 0] run_cmd;    // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
-    input                                   set_bytes;  // [11] if 1, use bytes (below), 0 - nop
-    input  [SENSI2C_CMD_BYTES_PBITS -1 : 0] bytes;      // [10:9] set command bytes to send after slave address (0..3)
-    input                                   set_dly;    // [8] if 1, use dly (0 - ignore)
-    input   [SENSI2C_CMD_DLY_PBITS - 1 : 0] dly;        // [7:0]  - duration of quarter i2c cycle (if 0, [3:0] control SCL+SDA)
-    input    [SENSI2C_CMD_SCL_WIDTH -1 : 0] scl_ctl;    // [1:0] : 0: NOP, 1: 1'b0->SCL, 2: 1'b1->SCL, 3: 1'bz -> SCL 
-    input    [SENSI2C_CMD_SDA_WIDTH -1 : 0] sda_ctl;    // [3:2] : 0: NOP, 1: 1'b0->SDA, 2: 1'b1->SDA, 3: 1'bz -> SDA  
+    input                                   set_active; 
+    input                                   active_sda; 
+    input                                   early_release_0; 

    reg                              [31:0] tmp;

    begin
    // only needs wait busy for software i2c
 //        #80; // instead of wait busy - check if it is needed
-        tmp= {func_sensor_i2c_command(rst_cmd, run_cmd, set_bytes, bytes, set_dly, dly, scl_ctl, sda_ctl)};
+        tmp= {func_sensor_i2c_command(rst_cmd, run_cmd, set_active, active_sda, early_release_0)};
+        write_contol_register( SENSOR_GROUP_ADDR + num_sensor * SENSOR_BASE_INC +SENSI2C_CTRL_RADDR, tmp);
+    end
+endtask
+
+task set_sensor_i2c_table_reg_wr;
+    input                             [1:0] num_sensor;
+    input                             [7:0] page;       // set parameters for 32-bit command with this MSB
+    input                             [6:0] slave_addr; // 7-bit slave address
+    input                             [7:0] rah;        // register address high byte
+    input                             [3:0] num_bytes;  // number of bytes to send
+    input                             [7:0] bit_delay;
+
+    reg                              [31:0] tmp;
+
+    begin
+    // set table address
+        tmp = 0;
+        tmp [SENSI2C_CMD_TABLE] = 1;
+        tmp [SENSI2C_CMD_TAND] =  1;
+        tmp [7:0]              =  page;
+        write_contol_register( SENSOR_GROUP_ADDR + num_sensor * SENSOR_BASE_INC +SENSI2C_CTRL_RADDR, tmp);
+        // write table entry
+        tmp = {4'b0, func_sensor_i2c_table_reg_wr(slave_addr, rah, num_bytes, bit_delay)};
+        tmp [SENSI2C_CMD_TABLE] = 1;
+        write_contol_register( SENSOR_GROUP_ADDR + num_sensor * SENSOR_BASE_INC +SENSI2C_CTRL_RADDR, tmp);
+    end
+endtask
+
+task set_sensor_i2c_table_reg_rd;
+    input                             [1:0] num_sensor;
+    input                             [7:0] page;       // set parameters for 32-bit command with this MSB
+    input                                   num_bytes_addr; // number of address bytes (0 - 1, 1 - 2)
+    input                             [2:0] num_bytes_rd;  // number of bytes to read, with "0" meaning all 8
+    input                             [7:0] bit_delay;
+
+    reg                              [31:0] tmp;
+
+    begin
+    // set table address
+        tmp = 0;
+        tmp [SENSI2C_CMD_TABLE] = 1;
+        tmp [SENSI2C_CMD_TAND] =  1;
+        tmp [7:0]              =  page;
+        write_contol_register( SENSOR_GROUP_ADDR + num_sensor * SENSOR_BASE_INC +SENSI2C_CTRL_RADDR, tmp);
+        // write table entry
+        tmp = {4'b0, func_sensor_i2c_table_reg_rd(num_bytes_addr, num_bytes_rd, bit_delay)};
+        tmp [SENSI2C_CMD_TABLE] = 1;
        write_contol_register( SENSOR_GROUP_ADDR + num_sensor * SENSOR_BASE_INC +SENSI2C_CTRL_RADDR, tmp);
    end
 endtask
@@ -3663,29 +3744,56 @@ endfunction
 function [31 : 0] func_sensor_i2c_command;
    input                                   rst_cmd;    // [14]   reset all FIFO (takes 16 clock pulses), also - stops i2c until run command
    input       [SENSI2C_CMD_RUN_PBITS : 0] run_cmd;    // [13:12]3 - run i2c, 2 - stop i2c (needed before software i2c), 1,0 - no change to run state
-    input                                   set_bytes;  // [11] if 1, use bytes (below), 0 - nop
-    input  [SENSI2C_CMD_BYTES_PBITS -1 : 0] bytes;      // [10:9] set command bytes to send after slave address (0..3)
-    input                                   set_dly;    // [8] if 1, use dly (0 - ignore)
-    input   [SENSI2C_CMD_DLY_PBITS - 1 : 0] dly;        // [7:0]  - duration of quarter i2c cycle (if 0, [3:0] control SCL+SDA)
-    input    [SENSI2C_CMD_SCL_WIDTH -1 : 0] scl_ctl;    // [17:16] : 0: NOP, 1: 1'b0->SCL, 2: 1'b1->SCL, 3: 1'bz -> SCL 
-    input    [SENSI2C_CMD_SDA_WIDTH -1 : 0] sda_ctl;    // [19:18] : 0: NOP, 1: 1'b0->SDA, 2: 1'b1->SDA, 3: 1'bz -> SDA  
+    input                                   set_active; 
+    input                                   active_sda; 
+    input                                   early_release_0; 
    
    reg  [31 : 0] tmp;
    begin
        tmp = 0;
        tmp [SENSI2C_CMD_RESET] =                                 rst_cmd;
        tmp [SENSI2C_CMD_RUN  -: SENSI2C_CMD_RUN_PBITS+1] =       run_cmd;
-        tmp [SENSI2C_CMD_BYTES] =                                 set_bytes;
-        tmp [SENSI2C_CMD_BYTES -1 -: SENSI2C_CMD_BYTES_PBITS ] =  bytes;
-        tmp [SENSI2C_CMD_DLY] =                                   set_dly;
-        tmp [SENSI2C_CMD_DLY -1 -: SENSI2C_CMD_DLY_PBITS ] =      dly;
-        tmp [SENSI2C_CMD_SCL +: SENSI2C_CMD_SCL_WIDTH] =          scl_ctl;
-        tmp [SENSI2C_CMD_SDA +: SENSI2C_CMD_SDA_WIDTH] =          sda_ctl;
-
+        tmp [SENSI2C_CMD_ACIVE] =                                 set_active;
+        tmp [SENSI2C_CMD_ACIVE_EARLY0] =                          active_sda;
+        tmp [SENSI2C_CMD_ACIVE_SDA] =                             early_release_0;
        func_sensor_i2c_command = tmp;
    end
 endfunction

+function [27:0] func_sensor_i2c_table_reg_wr; //
+    input                             [6:0] slave_addr; // 7-bit slave address
+    input                             [7:0] rah;        // register address high byte
+    input                             [3:0] num_bytes;  // number of bytes to send
+    input                             [7:0] bit_delay;
+
+    reg  [27 : 0] tmp;
+    begin
+        tmp = 0;
+        tmp[SENSI2C_TBL_RAH +:  SENSI2C_TBL_RAH_BITS] =  rah;
+        tmp[SENSI2C_TBL_RNWREG] =                        1'b0; // write register
+        tmp[SENSI2C_TBL_SA +:   SENSI2C_TBL_SA_BITS] =   slave_addr;
+        tmp[SENSI2C_TBL_NBWR +: SENSI2C_TBL_NBWR_BITS] = num_bytes;
+        tmp[SENSI2C_TBL_DLY +:  SENSI2C_TBL_DLY_BITS] =  bit_delay;
+        func_sensor_i2c_table_reg_wr =tmp;
+    end
+endfunction
+
+function [27:0] func_sensor_i2c_table_reg_rd; //
+    input                                   num_bytes_addr; // number of address bytes (0 - 1, 1 - 2)
+    input                             [2:0] num_bytes_rd;  // number of bytes to read, with "0" meaning all 8
+    input                             [7:0] bit_delay;
+
+    reg  [27 : 0] tmp;
+    begin
+        tmp = 0;
+        tmp[SENSI2C_TBL_RNWREG] =                        1'b1; // read register
+        tmp[SENSI2C_TBL_NBRD +: SENSI2C_TBL_NBRD_BITS] = num_bytes_rd;
+        tmp[SENSI2C_TBL_NABRD] =                         num_bytes_addr;
+        tmp[SENSI2C_TBL_DLY +:  SENSI2C_TBL_DLY_BITS] =  bit_delay;
+        func_sensor_i2c_table_reg_rd =tmp;
+    end
+endfunction
+


 // x393_sensor.py