more verilog tasks converted to python

includes/x393_tasks_ps_pio.vh

@@ -19,7 +19,7 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/> .
  *******************************************************************************/
-task schedule_ps_pio; // shedule software-control memory operation (may need to check FIFO status first)
+task schedule_ps_pio; // schedule software-control memory operation (may need to check FIFO status first)
     input [9:0] seq_addr; // sequence start address
     input [1:0] page;     // buffer page number
     input       urgent;   // high priority request (only for competion wityh other channels, wiil not pass in this FIFO)

py393/import_verilog_parameters.py

@@ -386,10 +386,10 @@ class ImportVerilogParameters(object):
                     print ("ERROR: failed to evaluate expression in '%s' (starting from '%s'"%(line,line[start:]))
                     return None
                 endPos=skipWS(exp[2])
-                if endPosp >= len(line):
+                if endPos >= len(line):
                     print ("ERROR: EOL reached when closing ')' was expected in '%s'"%line)
                     return None
-                if line[ep] != ")":
+                if line[endPos] != ")":
                     print ("ERROR: Found '%s'when closing ')' was expected in '%s'"%(line[endPos],line))
                     return None
                 endPos=skipWS(endPos+1)

py393/test1.py

@@ -46,6 +46,8 @@ import x393_mem
 import x393_axi_control_status
 import x393_pio_sequences
 import x393_mcntrl_timing
+import x393_mcntrl_buffers
+import x393_mcntrl_tests
 __all__ = []
 __version__ = 0.1
 __date__ = '2015-03-01'
@@ -230,6 +232,8 @@ USAGE
     x393tasks=  x393_axi_control_status.X393AxiControlStatus(verbose,True)
     x393Pio=    x393_pio_sequences.X393PIOSequences(verbose,True)
     x393Timing= x393_mcntrl_timing.X393McntrlTiming(verbose,True)
+    x393Buffers=x393_mcntrl_buffers.X393McntrlBuffers(verbose,True)
+    x393Tests=  x393_mcntrl_tests.X393McntrlTests(verbose,True)
     '''
     print ("----------------------")
     print("x393_mem.__dict__="+str(x393_mem.__dict__))
@@ -248,7 +252,10 @@ USAGE
     extractTasks(x393_axi_control_status.X393AxiControlStatus,x393tasks)
     extractTasks(x393_pio_sequences.X393PIOSequences,x393Pio)
     extractTasks(x393_mcntrl_timing.X393McntrlTiming,x393Timing)
+    extractTasks(x393_mcntrl_buffers.X393McntrlBuffers,x393Buffers)
+    extractTasks(x393_mcntrl_tests.X393McntrlTests,x393Tests)
 
+#
     if verbose > 3:     
         funcName="read_mem"
         funcArgs=[0x377,123]

py393/x393_axi_control_status.py

@@ -33,14 +33,15 @@ __status__ = "Development"
 from import_verilog_parameters import VerilogParameters
 from x393_mem import X393Mem
 #from verilog_utils import hx,concat, bits 
-from verilog_utils import hx 
+from verilog_utils import hx
         
 class X393AxiControlStatus(object):
     DRY_MODE= True # True
     DEBUG_MODE=1
 #    vpars=None
     x393_mem=None
-    target_phase=0 # TODO: set!
+    enabled_channels=0 # currently enable channels
+#    verbose=1
     def __init__(self, debug_mode=1,dry_mode=True):
         self.DEBUG_MODE=debug_mode
         self.DRY_MODE=dry_mode
@@ -52,7 +53,10 @@ class X393AxiControlStatus(object):
 #        print (VerilogParameters.__dict__)
 #        self.__dict__.update(VerilogParameters.__dict__) # Add verilog parameters to the class namespace
         self.__dict__.update(VerilogParameters.__dict__["_VerilogParameters__shared_state"]) # Add verilog parameters to the class namespace
-        
+#        try:
+#            verbose=self.verbose
+#        except:
+#            pass
 #        print ("+++++++++++++++ self.__dict__ ++++++++++++++++++++++++++")
 #        print (self.__dict__)
         '''
@@ -86,11 +90,6 @@ class X393AxiControlStatus(object):
             if invert_match:
                 match = not match
             if self.DRY_MODE: break
-    def wait_phase_shifter_ready(self):
-        data=self.read_and_wait_status(self.MCONTR_PHY_STATUS_REG_ADDR)
-        while (((data & self.STATUS_PSHIFTER_RDY_MASK) == 0) or (((data ^ self.target_phase) & 0xff) != 0)):
-            data=self.read_and_wait_status(self.MCONTR_PHY_STATUS_REG_ADDR)
-            if self.DRY_MODE: break
 
     def read_all_status(self):
 #        print (self.__dict__)
@@ -138,6 +137,43 @@ class X393AxiControlStatus(object):
         self.program_status (self.MCNTRL_TEST01_ADDR,        self.MCNTRL_TEST01_CHN2_STATUS_CNTRL,mode,seq_num)#; //MCNTRL_TEST01_STATUS_REG_CHN2_ADDR=  'h3c,
         self.program_status (self.MCNTRL_TEST01_ADDR,        self.MCNTRL_TEST01_CHN3_STATUS_CNTRL,mode,seq_num)#; //MCNTRL_TEST01_STATUS_REG_CHN3_ADDR=  'h3d,
         self.program_status (self.MCNTRL_TEST01_ADDR,        self.MCNTRL_TEST01_CHN4_STATUS_CNTRL,mode,seq_num)#; //MCNTRL_TEST01_STATUS_REG_CHN4_ADDR=  'h3e,
-        '''
-        x393_tasks_ps_pio
-        '''
+        
+    def enable_cmda(self,
+                    en): # input en;
+        self.write_contol_register(self.MCONTR_PHY_0BIT_ADDR +  self.MCONTR_PHY_0BIT_CMDA_EN + en, 0);
+            
+    def enable_cke(self,
+                    en): # input en;
+        self.write_contol_register(self.MCONTR_PHY_0BIT_ADDR +  self.MCONTR_PHY_0BIT_CKE_EN + en, 0);
+
+    def activate_sdrst(self,
+                    en): # input en;
+        self.write_contol_register(self.MCONTR_PHY_0BIT_ADDR +  self.MCONTR_PHY_0BIT_SDRST_ACT + en, 0);
+
+    def enable_refresh(self,
+                    en): # input en;
+        self.write_contol_register(self.MCONTR_TOP_0BIT_ADDR +  self.MCONTR_TOP_0BIT_REFRESH_EN + en, 0);
+        
+    def enable_memcntrl(self,
+                    en): # input en;
+        self.write_contol_register(self.MCONTR_TOP_0BIT_ADDR +  self.MCONTR_TOP_0BIT_MCONTR_EN + en, 0);
+        
+    def enable_memcntrl_channels(self,
+                                 chnen): # input [15:0] chnen; // bit-per-channel, 1 - enable;
+        self.enabled_channels = chnen; # currently enabled memory channels
+        self.write_contol_register(self.MCONTR_TOP_16BIT_ADDR +  self.MCONTR_TOP_16BIT_CHN_EN, self.enabled_channels & 0xffff) # {16'b0,chnen});
+
+    def enable_memcntrl_en_dis(self,
+                               chn, # input [3:0] chn;
+                               en):# input       en;
+        if en:
+            self.enabled_channels = self.enabled_channels | (1<<chn);
+        else:
+            self.enabled_channels = self.enabled_channels & ~(1<<chn);
+        self.write_contol_register(self.MCONTR_TOP_16BIT_ADDR + self. MCONTR_TOP_16BIT_CHN_EN, self.enabled_channels & 0xffff) #  {16'b0,ENABLED_CHANNELS});
+
+    def configure_channel_priority(self,
+                                   chn, # input [ 3:0] chn;
+                                   priority): #input [15:0] priority; // (higher is more important)
+        self.write_contol_register(self.MCONTR_ARBIT_ADDR + chn, priority  & 0xffff)# {16'b0,priority});
+

py393/x393_mcntrl_buffers.py

+from __future__ import print_function
+'''
+# Copyright (C) 2015, Elphel.inc.
+# Methods that mimic Verilog tasks used for simulation  
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http:#www.gnu.org/licenses/>.
+
+@author:     Andrey Filippov
+@copyright:  2015 Elphel, Inc.
+@license:    GPLv3.0+
+@contact:    andrey@elphel.coml
+@deffield    updated: Updated
+'''
+__author__ = "Andrey Filippov"
+__copyright__ = "Copyright 2015, Elphel, Inc."
+__license__ = "GPL"
+__version__ = "3.0+"
+__maintainer__ = "Andrey Filippov"
+__email__ = "andrey@elphel.com"
+__status__ = "Development"
+#import sys
+#import x393_mem
+#x393_pio_sequences
+from import_verilog_parameters import VerilogParameters
+from x393_mem import X393Mem
+from x393_axi_control_status import X393AxiControlStatus
+#from verilog_utils import * # concat, bits 
+#from verilog_utils import hx, concat, bits, getParWidth 
+#from verilog_utils import concat, getParWidth
+#from x393_axi_control_status import concat, bits 
+class X393McntrlBuffers(object):
+    DRY_MODE= True # True
+    DEBUG_MODE=1
+#    vpars=None
+    x393_mem=None
+    x393_axi_tasks=None #x393X393AxiControlStatus
+    verbose=1
+    def __init__(self, debug_mode=1,dry_mode=True):
+        self.DEBUG_MODE=debug_mode
+        self.DRY_MODE=dry_mode
+        self.x393_mem=X393Mem(debug_mode,dry_mode)
+        self.x393_axi_tasks=X393AxiControlStatus(debug_mode,dry_mode)
+        self.__dict__.update(VerilogParameters.__dict__["_VerilogParameters__shared_state"]) # Add verilog parameters to the class namespace
+        try:
+            self.verbose=self.VERBOSE
+        except:
+            pass
+    def write_block_scanline_chn(self,       #
+                                 chn,        # input   [3:0] chn; // buffer channel
+                                 page,       # input   [1:0] page;
+                                 num_bursts, # input [NUM_XFER_BITS:0] num_bursts; // number of 8-bursts to write (will be rounded up to multiple of 16)
+                                 startX,     # input integer startX;
+                                 startY):    #input integer startY;
+        print("====== write_block_scanline_chn:%d page: %x X=0x%x Y=0x%x num=%dt"%(chn, page, startX, startY,num_bursts))
+        if   chn == 0:  start_addr=self.MCONTR_BUF0_WR_ADDR + (page << 8)
+        elif chn == 1:  start_addr=self.MCONTR_BUF1_WR_ADDR + (page << 8)
+        elif chn == 2:  start_addr=self.MCONTR_BUF2_WR_ADDR + (page << 8)
+        elif chn == 3:  start_addr=self.MCONTR_BUF3_WR_ADDR + (page << 8)
+        elif chn == 4:  start_addr=self.MCONTR_BUF4_WR_ADDR + (page << 8)
+        else:
+            print("**** ERROR: Invalid channel for write_block_scanline_chn = %d"% chn)
+            start_addr = self.MCONTR_BUF0_WR_ADDR+ (page << 8);
+        num_words=num_bursts << 2;
+        self.write_block_incremtal (start_addr, num_words, (startX<<2) + (startY<<16));# 1 of startX is 8x16 bit, 16 bytes or 4 32-bit words
+
+    def write_block_buf(self,
+                              start_word_address, # input [29:0] start_word_address;
+                              num_words_or_data_list):          # input integer num_words; # number of words to write (will be rounded up to multiple of 16)
+        if isinstance (num_words_or_data_list,int):
+            data=[]
+            for i in range(num_words_or_data_list):
+                data.append(i | (((i + 7) & 0xff) << 8)  | (((i + 23) & 0xff) << 16) | (((i + 31) & 0xff) << 24))
+        else:
+            data=num_words_or_data_list
+        if self.verbose>0:
+            print("**** write_block_buf, start_word_address=0x%x, num+words=0x%x"%(start_word_address,len(data)))
+        for i,d in enumerate(data):
+            d= i | (((i + 7) & 0xff) << 8)  | (((i + 23) & 0xff) << 16) | (((i + 31) & 0xff) << 24)
+            if self.verbose>2:
+                print("     write_block_buf 0x%x:0x%x"%(start_word_address+i,d))
+            self.x393_mem.axi_write_single_w(start_word_address+i, d)
+
+    def write_block_incremtal(self,
+                              start_word_address, # input [29:0] start_word_address;
+                              num_words,          # input integer num_words; # number of words to write (will be rounded up to multiple of 16)
+                              start_value):       # input integer start_value;      
+        if self.verbose>0:
+            print("**** write_block_incremtal, start_word_address=0x%x, num_words=0x%x, start_value=0x%x "%(start_word_address,num_words,start_value))
+        for i in range(0,num_words):
+            if self.verbose>2:
+                print("     write_block_buf 0x%x:0x%x"%(start_word_address+i,start_value+i))
+            self.x393_mem.axi_write_single_w(start_word_address+i, start_value+i)
+
+    def write_block_buf_chn(self,       #
+                            chn,        # input integer chn; # buffer channel
+                            page,       # input   [1:0] page;
+                            num_words_or_data_list): # input integer num_words; # number of words to write (will be rounded up to multiple of 16)
+        start_addr=-1
+        if   chn==0:start_addr=self.MCONTR_BUF0_WR_ADDR + (page << 8)
+        elif chn==1:start_addr=self.MCONTR_BUF1_WR_ADDR + (page << 8)
+        elif chn==2:start_addr=self.MCONTR_BUF2_WR_ADDR + (page << 8)
+        elif chn==3:start_addr=self.MCONTR_BUF3_WR_ADDR + (page << 8)
+        elif chn==4:start_addr=self.MCONTR_BUF4_WR_ADDR + (page << 8)
+        else:
+            print("**** ERROR: Invalid channel for write buffer = %d"% chn)
+            start_addr = self.MCONTR_BUF0_WR_ADDR+ (page << 8)
+        self.write_block_buf (start_addr, num_words_or_data_list)
+    
+    def read_block_buf(self, 
+                       start_word_address, # input [29:0] start_word_address;
+                       num_read,           # input integer num_read; # number of words to read (will be rounded up to multiple of 16)
+                       show_rslt=True):
+        if self.verbose>0:
+            print("**** read_block_buf, start_word_address=0x%x, num_read=0x%x "%(start_word_address,num_read))
+        result=[]    
+        for i in range(num_read): #for (i = 0; i < num_read; i = i + 16) begin
+            d=self.x393_mem.axi_read_addr_w(start_word_address+i)
+            if (self.verbose>2) or show_rslt:
+                print("     read_block_buf 0x%x:0x%x"%(start_word_address+i,d))
+            result.append(d)
+        return result
+
+    def read_block_buf_chn(self,  # S uppressThisWarning VEditor : may be unused
+                           chn, # input [3:0] chn; # buffer channel
+                           page, #input   [1:0] page;
+                           num_read, #input integer num_read; # number of words to read (will be rounded up to multiple of 16)
+                           show_rslt=True):
+        start_addr=-1
+        if   chn==0:  start_addr=self.MCONTR_BUF0_RD_ADDR + (page << 8)
+        elif chn==1:  start_addr=self.MCONTR_BUF1_RD_ADDR + (page << 8)
+        elif chn==2:  start_addr=self.MCONTR_BUF2_RD_ADDR + (page << 8)
+        elif chn==3:  start_addr=self.MCONTR_BUF3_RD_ADDR + (page << 8)
+        elif chn==4:  start_addr=self.MCONTR_BUF4_RD_ADDR + (page << 8)
+        else:
+            print("**** ERROR: Invalid channel for read buffer = %d"%chn)
+            start_addr = self.MCONTR_BUF0_RD_ADDR+ (page << 8)
+        result=self.read_block_buf (start_addr, num_read, show_rslt)
+        return result

py393/x393_mcntrl_timing.py

@@ -36,7 +36,7 @@ from x393_mem import X393Mem
 from x393_axi_control_status import X393AxiControlStatus
 #from verilog_utils import * # concat, bits 
 #from verilog_utils import hx, concat, bits, getParWidth 
-from verilog_utils import concat, getParWidth 
+from verilog_utils import concat, getParWidth
 #from x393_axi_control_status import concat, bits 
 class X393McntrlTiming(object):
     DRY_MODE= True # True
@@ -45,7 +45,6 @@ class X393McntrlTiming(object):
     x393_mem=None
     x393_axi_tasks=None #x393X393AxiControlStatus
     target_phase=0 # TODO: set!
-    target_phase=0
     def __init__(self, debug_mode=1,dry_mode=True):
         self.DEBUG_MODE=debug_mode
         self.DRY_MODE=dry_mode
@@ -152,6 +151,12 @@ class X393McntrlTiming(object):
         self.x393_axi_tasks.write_contol_register(self.DLY_SET,0)
         self.target_phase = phase
             
+    def wait_phase_shifter_ready(self):
+        data=self.x393_axi_tasks.read_and_wait_status(self.MCONTR_PHY_STATUS_REG_ADDR)
+        while (((data & self.STATUS_PSHIFTER_RDY_MASK) == 0) or (((data ^ self.target_phase) & 0xff) != 0)):
+            data=self.x393_axi_tasks.read_and_wait_status(self.MCONTR_PHY_STATUS_REG_ADDR)
+            if self.DRY_MODE: break
+
     def axi_set_wbuf_delay(self,
                             delay): # input [3:0] delay;
         print("SET WBUF DELAY=0x%x"%delay)

py393/x393_mem.py

@@ -104,4 +104,78 @@ class X393Mem(object):
 
     def axi_read_addr_w(self,addr):
         return self.axi_read_addr(addr<<2)
-        
+   
\ No newline at end of file
+    '''
+    task axi_write_addr_data;
+        input [11:0] id;
+        input [31:0] addr;
+        input [31:0] data;
+        input [ 3:0] len;
+        input [ 1:0] burst;
+        input        data_en; // if 0 - do not send data, only address
+        input [ 3:0] wstrb;
+        input        last;
+        reg          data_sent;
+//        wire         data_sent_d;
+//        assign #(.1) data_sent_d= data_sent;
+        begin
+            wait (!CLK && AW_READY);
+            AWID_IN_r    <= id;
+            AWADDR_IN_r  <= addr;
+            AWLEN_IN_r   <= len;
+            AWSIZE_IN_r  <= 3'b010;
+            AWBURST_IN_r <= burst;
+            AW_SET_CMD_r <= 1'b1;
+            if (data_en && W_READY) begin
+                WID_IN_r <= id;
+                WDATA_IN_r <= data;
+                WSTRB_IN_r <= wstrb;
+                WLAST_IN_r <= last;
+                W_SET_CMD_r <= 1'b1; 
+                data_sent <= 1'b1;
+            end else begin
+                data_sent <= 1'b0;
+            end
+            DEBUG1 <=1'b1;
+            wait (CLK);
+            DEBUG1 <=1'b0;
+            AWID_IN_r    <= 'hz;
+            AWADDR_IN_r  <= 'hz;
+            AWLEN_IN_r   <= 'hz;
+            AWSIZE_IN_r  <= 'hz;
+            AWBURST_IN_r <= 'hz;
+            AW_SET_CMD_r <= 1'b0;
+            DEBUG2 <=1'b1;
+            if (data_sent) begin
+                WID_IN_r    <= 'hz;
+                WDATA_IN_r  <= 'hz;
+                WSTRB_IN_r  <= 'hz;
+                WLAST_IN_r  <= 'hz;
+                W_SET_CMD_r <= 1'b0; 
+            end
+// Now sent data if it was not sent simultaneously with the address
+            if (data_en && !data_sent) begin
+                DEBUG3 <=1'b1;
+                wait (!CLK && W_READY);
+                DEBUG3 <=1'b0;
+                WID_IN_r    <= id;
+                WDATA_IN_r  <= data;
+                WSTRB_IN_r  <= wstrb;
+                WLAST_IN_r  <= last;
+                W_SET_CMD_r <= 1'b1; 
+                wait (CLK);
+                DEBUG3 <=1'bx;
+                WID_IN_r    <= 'hz;
+                WDATA_IN_r  <= 'hz;
+                WSTRB_IN_r  <= 'hz;
+                WLAST_IN_r  <= 'hz;
+                W_SET_CMD_r <= 1'b0; 
+            end
+            DEBUG2 <=1'b0;
+            #0.1;
+            data_sent <= 1'b0;
+            #0.1;
+        end
+    endtask
+    
+    '''     
\ No newline at end of file

py393/x393_pio_sequences.py

@@ -64,7 +64,7 @@ class X393PIOSequences(object):
 #        __dict__.update(VerilogParameters.__dict__) # Add verilog parameters to the class namespace
         '''
         
-    def schedule_ps_pio(self,          #; // shedule software-control memory operation (may need to check FIFO status first)
+    def schedule_ps_pio(self,          #; // schedule software-control memory operation (may need to check FIFO status first)
                         seq_addr,      # input [9:0] seq_addr; // sequence start address
                         page,          # input [1:0] page;     // buffer page number
                         urgent,        # input       urgent;   // high priority request (only for competion wityh other channels, wiil not pass in this FIFO)
@@ -81,7 +81,7 @@ class X393PIOSequences(object):
     def wait_ps_pio_ready(self,      #; // wait PS PIO module can accept comamnds (fifo half empty)
                           mode,      # input [1:0] mode;
                           sync_seq): # input       sync_seq; //  synchronize sequences
-        self.wait_status_condition (
+        self.x393_axi_tasks.wait_status_condition (
             self.MCNTRL_PS_STATUS_REG_ADDR,
             self.MCNTRL_PS_ADDR + self.MCNTRL_PS_STATUS_CNTRL,
             mode & 3,
@@ -93,7 +93,7 @@ class X393PIOSequences(object):
     def wait_ps_pio_done(self,      # // wait PS PIO module has no pending/running memory transaction
                          mode,      # input [1:0] mode;
                          sync_seq): # input       sync_seq; //  synchronize sequences
-        self.wait_status_condition (
+        self.x393_axi_tasks.wait_status_condition (
             self.MCNTRL_PS_STATUS_REG_ADDR,
             self.MCNTRL_PS_ADDR + self.MCNTRL_PS_STATUS_CNTRL,
             mode & 3,

x393_testbench01.tf

@@ -306,7 +306,7 @@ always #(CLKIN_PERIOD/2) CLK = ~CLK;
 
 // set MR registers in DDR3 memory, run DCI calibration (long)
     wait_ps_pio_ready(DEFAULT_STATUS_MODE, 1); // wait FIFO not half full 
-    schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
+    schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
                         INITIALIZE_OFFSET, // input [9:0] seq_addr; // sequence start address
                         0,                 // input [1:0] page;     // buffer page number
                         0,                 // input       urgent;   // high priority request (only for competion with other channels, wiil not pass in this FIFO)
@@ -1097,7 +1097,7 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused
 // Set write buffer (from DDR3) WE signal delay for write leveling mode
         axi_set_wbuf_delay(WBUF_DLY_WLV);
         axi_set_dqs_odelay('h80); // 'h80 - inverted, 'h60 - not - 'h80 will cause warnings during simulation
-        schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
+        schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
                         WRITELEV_OFFSET,   // input [9:0] seq_addr; // sequence start address
                         0,                 // input [1:0] page;     // buffer page number
                         0,                 // input       urgent;   // high priority request (only for competion with other channels, wiil not pass in this FIFO)
@@ -1108,7 +1108,7 @@ task test_write_levelling; // SuppressThisWarning VEditor - may be unused
         read_block_buf_chn (0, 0, 32, 1 ); // chn=0, page=0, number of 32-bit words=32, wait_done
 //        @ (negedge rstb);
         axi_set_dqs_odelay(DLY_DQS_ODELAY);
-        schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
+        schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
                         WRITELEV_OFFSET,   // input [9:0] seq_addr; // sequence start address
                         1,                 // input [1:0] page;     // buffer page number
                         0,                 // input       urgent;   // high priority request (only for competion with other channels, wiil not pass in this FIFO)
@@ -1128,7 +1128,7 @@ endtask
 
 task test_read_pattern; // SuppressThisWarning VEditor - may be unused
     begin  
-        schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
+        schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
                         READ_PATTERN_OFFSET,   // input [9:0] seq_addr; // sequence start address
                         2,                     // input [1:0] page;     // buffer page number
                         0,                     // input       urgent;   // high priority request (only for competion with other channels, wiil not pass in this FIFO)
@@ -1142,7 +1142,7 @@ endtask
 task test_write_block; // SuppressThisWarning VEditor - may be unused
     begin
 //    write_block_buf_chn; // fill block memory - already set in set_up task
-        schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
+        schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
                         WRITE_BLOCK_OFFSET,    // input [9:0] seq_addr; // sequence start address
                         0,                     // input [1:0] page;     // buffer page number
                         0,                     // input       urgent;   // high priority request (only for competion with other channels, wiil not pass in this FIFO)
@@ -1155,19 +1155,19 @@ endtask
 
 task test_read_block; // SuppressThisWarning VEditor - may be unused
     begin
-        schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
+        schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
                         READ_BLOCK_OFFSET,   // input [9:0] seq_addr; // sequence start address
                         3,                     // input [1:0] page;     // buffer page number
                         0,                     // input       urgent;   // high priority request (only for competion with other channels, wiil not pass in this FIFO)
                         0,                    // input       chn;      // channel buffer to use: 0 - memory read, 1 - memory write
                         `PS_PIO_WAIT_COMPLETE );//  wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
-        schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
+        schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
                         READ_BLOCK_OFFSET,   // input [9:0] seq_addr; // sequence start address
                         2,                     // input [1:0] page;     // buffer page number
                         0,                     // input       urgent;   // high priority request (only for competion with other channels, wiil not pass in this FIFO)
                         0,                    // input       chn;      // channel buffer to use: 0 - memory read, 1 - memory write
                         `PS_PIO_WAIT_COMPLETE );//  wait_complete; // Do not request a newe transaction from the scheduler until previous memory transaction is finished
-        schedule_ps_pio ( // shedule software-control memory operation (may need to check FIFO status first)
+        schedule_ps_pio ( // schedule software-control memory operation (may need to check FIFO status first)
                         READ_BLOCK_OFFSET,   // input [9:0] seq_addr; // sequence start address
                         1,                     // input [1:0] page;     // buffer page number
                         0,                     // input       urgent;   // high priority request (only for competion with other channels, wiil not pass in this FIFO)