fixing setup

cocotb_@_COCOTB_DEBUG=false

cocotb_@_CocotbDutTopFile=cocotb/x393_dut.v

cocotb_@_CocotbExtraFiles=glbl.v<-@\#\#@->

cocotb_@_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->

cocotb_@_CocotbMODULE=x393_cocotb_server<-@\#\#@->

cocotb_@_CocotbTESTCASE=run_test<-@\#\#@->

cocotb_@_GTKWaveSavFile=x393_cocotb_02.sav

cocotb_@_GrepFindErr=error|ERROR

cocotb_@_GrepFindErrWarn=error|warning|ERROR|WARNING

cocotb_@_PatternInfo=.*[\\s.](\\w*\\.py)\:([0-9]+)\\s*\\S*\\s*\\S*\\s*(.*)

cocotb_@_SaveLogsPreprocessor=true

cocotb_@_SaveLogsSimulator=true

com.elphel.store.context.cocotb=cocotb_@_CocotbExtraFiles<-@\#\#@->cocotb_@_CocotbMODULE<-@\#\#@->cocotb_@_GTKWaveSavFile<-@\#\#@->cocotb_@_CocotbIncludeDir<-@\#\#@->cocotb_@_CocotbDutTopFile<-@\#\#@->cocotb_@_CocotbTESTCASE<-@\#\#@->cocotb_@_GrepFindErrWarn<-@\#\#@->cocotb_@_SaveLogsPreprocessor<-@\#\#@->cocotb_@_SaveLogsSimulator<-@\#\#@->cocotb_@_GrepFindErr<-@\#\#@->cocotb_@_PatternInfo<-@\#\#@->cocotb_@_COCOTB_DEBUG<-@\#\#@->

com.elphel.store.version.cocotb=0.8

eclipse.preferences.version=1

simulation_data/*.dat

simulation_data/*.jpeg

#these two project files are now in .eclipse_project_setup directory

.project

.pydevproject

/.project

/.pydevproject

#copied from .eclipse_project_setup, can be used to import workin set to limit warnings reported

workingSet.psf

/workingSet.psf

*.fst

cocotb/Makefile

cocotb/sim_build

cocotb/results.xml

*.directory

html.tar.gz

latex

bitbake-logs                                                                                                                                               

sysroots

image

/latex

/bitbake-logs                                                                                                                                               

/sysroots

/image

/scripts

FPGA_project_@_DUTTopFile=cocotb/x393_dut.v

FPGA_project_@_DUTTopModule=x393_dut

FPGA_project_@_ImplementationTopFile=x393.v

FPGA_project_@_SimulationTopFile=x393_testbench03.tf

FPGA_project_@_SimulationTopModule=x393_testbench03

FPGA_project_@_part=xc7z030fbg484-1

com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_DUTTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_DUTTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@->

com.elphel.store.version.FPGA_project=1.0

eclipse.preferences.version=1

ISExst_@_OtherProblems=HDLCompiler\:413<-@\#\#@->

ISExst_@_constraints=ddrc_test01.xcf

com.elphel.store.context.ISExst=ISExst_@_OtherProblems<-@\#\#@->ISExst_@_constraints<-@\#\#@->

eclipse.preferences.version=1

VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->

VivadoBitstream_@_force=true

VivadoBitstream_@_rawfile=x393_parallel

com.elphel.store.context.VivadoBitstream=VivadoBitstream_@_rawfile<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->

eclipse.preferences.version=1