Skip to content

X
x393
Commit f485624d authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

Changing to the new format of timestamp messages

parent 0ca70084
Hide whitespace changes
Inline Side-by-side
Showing with 95 additions and 43 deletions
.project
View file @ f485624d
......@@ -92,7 +92,7 @@
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150609094617774.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150702180615691.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
......@@ -102,7 +102,7 @@
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150609094617774.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150702180615691.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
......@@ -112,7 +112,7 @@
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150609094617774.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150702180615691.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
......@@ -132,7 +132,7 @@
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150609094617774.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150702180615691.dcp</location>
</link>
</linkedResources>
</projectDescription>
compressor_jp/jp_channel.v
View file @ f485624d
......@@ -103,17 +103,13 @@ module jp_channel#(
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
// TODO: Maybe move buffer to memory controller ?
// Buffer interface (buffer to be a part of the memory controller - it is connected there by a 64-bit data, here - by an 9-bit one
input xfer_reset_page_rd, // from mcntrl_tiled_rw (
/// input buf_wpage_nxt, // input
/// input buf_wr, // input
/// input [63:0] buf_wdata, // input[63:0]
output [11:0] buf_ra,
output buf_ren,
output buf_regen,
input [ 7:0] buf_di,
input page_ready_chn, // single mclk (posedge)
output next_page_chn, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
// statistics data was not used in late nc353
......@@ -121,9 +117,11 @@ module jp_channel#(
input [2:0] hfc_sel, // [2:0] (for autofocus) only components with both spacial frequencies higher than specified will be added
output statistics_dv,
output [15:0] statistics_do,
// timestamp input
input [31:0] sec,
input [19:0] usec,
// Timestamp messages (@mclk)
input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
/// output [23:0] imgptr, - removed - use AFI channel MUX
output eof_written_mclk,
output stuffer_done_mclk,
......@@ -156,9 +154,6 @@ module jp_channel#(
input eof_written, // confirm frame written ofer AFI to the system memory (single rclk pulse)
output fifo_flush, // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
output [7:0] fifo_count // number of 32-byte chunks in FIFO
);
// Control signals to be defined
wire frame_en; // if 0 - will reset logic immediately (but not page number)
......@@ -839,31 +834,26 @@ module jp_channel#(
wire stuffer_dv;
wire stuffer_done;
wire eof_written_xclk2xn;
// reg stuffer_done_persist;
// wire stuffer_flushing;
stuffer393 stuffer393_i (
.rst (rst), // input
.mclk (mclk), // input
.ts_pre_stb (ts_pre_stb), // input 1 cycle before timestamp data, @mclk
.ts_data (ts_data), // input[7:0] 8-byte timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
.color_first (color_first), // input valid @xclk - only for sec/usec
.fradv_clk (xclk), // input
.clk (xclk2x), // input clock - uses negedge inside
.en_in (stuffer_en), //
/// .reset_data_counters (reset_data_counters[1]), // input reset data transfer counters (only when DMA and compressor are disabled)
.flush (flush), // input - flush output data (fill byte with 0, long word with FFs)
.abort (force_flush_long), // @ any, extracts 0->1 and flushes
.stb (huff_dv), // input
.dl (huff_dl), // input[3:0] number of bits to send (0 - 16) (0-16??)
.d (huff_do), // input[15:0] data to shift (only lower huff_dl bits are valid)
// time stamping - will copy time at the end of color_first (later than the first hact after vact in the current froma, but before the next one
// and before the data is needed for output
.color_first (color_first), // input valid @xclk - only for sec/usec
.sec (sec[31:0]), // input[31:0] registers to right clock/time inside
.usec (usec[19:0]), // input[19:0]
// outputs valid @negedge xclk2x
.rdy (stuffer_rdy), // output - enable huffman encoder to proceed. Used as CE for many huffman encoder registers
.q (stuffer_do), // output[15:0] reg - output data
.qv (stuffer_dv), // output reg - output data valid
.done (stuffer_done), // output
/// .imgptr (imgptr[23:0]), // output[23:0] reg - image pointer in 32-byte chunks
// .flushing (stuffer_flushing), // output reg
.flushing (), // output reg Not used?
.running (stuffer_running) // from registering timestamp until done
......
compressor_jp/stuffer393.v
View file @ f485624d
......@@ -42,19 +42,24 @@
// Or make FIFO outside of the stuffer?
module stuffer393 (
input rst, // global reset
input mclk,
// time stamping - will copy time at the end of color_first (later than the first hact after vact in the current frame, but before the next one
// and before the data is needed for output
input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
input color_first, // @fradv_clk only used for timestamp
input fradv_clk, // clock to synchronize color_first (leading edge to advance timestamp data for the output)
input clk, // 2x pixel clock
input en_in, // enable, 0- reset (other clock domain, needs re-sync)
/// input reset_data_counters, // reset data transfer counters (only when DMA and compressor are disabled)
input flush, // flush output data (fill byte with 0, long word with 0
input abort, // @ any, extracts 0->1 and flushes
input stb, // input data strobe
input [3:0] dl, // [3:0] number of bits to send (0 - 16) ??
input [15:0] d, // [15:0] input data to shift (only lower bits are valid)
// time stamping - will copy time at the end of color_first (later than the first hact after vact in the current froma, but before the next one
// and before the data is needed for output
input color_first, // (different clock) only used for timestamp
input [31:0] sec, // [31:0] number of seconds
input [19:0] usec, // [19:0] number of microseconds
// input [31:0] sec, // [31:0] number of seconds
// input [19:0] usec, // [19:0] number of microseconds
output rdy, // enable huffman encoder to proceed. Used as CE for many huffman encoder registers
// outputs @ negedge clk
output reg [15:0] q, // [15:0] output data
......@@ -124,7 +129,7 @@ module stuffer393 (
wire [3:0] sum_lengths;
reg [1:0] st2m_r;
reg [2:0] stb_time;
// reg [2:0] stb_time;
reg [31:0] sec_r;
reg [19:0] usec_r;
reg time_out;
......@@ -135,6 +140,53 @@ module stuffer393 (
reg [19:0] imgsz32; // current image size in multiples of 32-bytes
reg inc_imgsz32;
// re-clock enable to this clock
wire ts_rstb; // one cycle before getting timestamp data from FIFO
wire [7:0] ts_dout; // timestamp data, byte at a time
reg [7:0] ts_cycles; // 1-hot we for the portions of the 'old" timestamp registers
reg color_first_r; // registered with the same clock as color_first to extract leading edge
wire stb_start; // re-clocked color_first
assign ts_rstb = trailer && !was_trailer; // enough time to have timestamp data
always @ (negedge clk) begin
ts_cycles <= {ts_cycles[6:0],ts_rstb};
if (ts_cycles[0]) sec_r[ 7: 0] <= ts_dout;
else if (time_size_out) sec_r[ 7: 0] <= sec_r[23:16];
else if (start_sizeout) sec_r[ 7: 0] <= size_count[ 7:0];
if (ts_cycles[1]) sec_r[15: 8] <= ts_dout;
else if (time_size_out) sec_r[15: 8] <= sec_r[31:24];
else if (start_sizeout) sec_r[15: 8] <= size_count[15:8];
if (ts_cycles[2]) sec_r[23:16] <= ts_dout;
else if (time_size_out) sec_r[23:16] <= usec_r[ 7: 0];
else if (start_sizeout) sec_r[23:16] <= size_count[23:16];
if (ts_cycles[3]) sec_r[31:24] <= ts_dout;
else if (time_size_out) sec_r[31:24] <= usec_r[15: 8];
else if (start_sizeout) sec_r[31:24] <= 8'hff;
if (ts_cycles[4]) usec_r[ 7: 0] <= ts_dout;
else if (time_out) usec_r[ 7: 0] <= {4'h0, usec_r[19:16]};
if (ts_cycles[5]) usec_r[15: 8] <= ts_dout;
else if (time_out) usec_r[15: 8] <= 8'h0;
if (ts_cycles[6]) usec_r[19:16] <= ts_dout[3:0];
else if (time_out) usec_r[19:16] <= 4'h0;
/*
stb_time[2:0] <= {stb_time[1] & ~stb_time[0], stb_time[0],color_first};
if (stb_time[2]) sec_r[31:0] <= sec[31:0];
else if (start_sizeout) sec_r[31:0] <= {8'hff, size_count[23:0]};
else if (time_size_out) sec_r[31:0] <= {usec_r[15:0],sec_r[31:16]};
if (stb_time[2]) usec_r[19:0] <= usec[19:0];
else if (time_out) usec_r[19:0] <= {16'h0,usec_r[19:16]};
*/
end
always @ (negedge clk) begin
en <= en_in;
// re-clock abort, extract leading edge
......@@ -144,7 +196,8 @@ module stuffer393 (
else if (flush_end) force_flush <= 0;
if (!en) running <= 0;
else if (stb_time[2]) running <= 1;
// else if (stb_time[2]) running <= 1;
else if (stb_start) running <= 1;
else if (flush_end) running <= 0;
end
......@@ -300,16 +353,7 @@ end
`endif
always @ (negedge clk) begin
stb_time[2:0] <= {stb_time[1] & ~stb_time[0], stb_time[0],color_first};
if (stb_time[2]) sec_r[31:0] <= sec[31:0];
else if (start_sizeout) sec_r[31:0] <= {8'hff, size_count[23:0]};
else if (time_size_out) sec_r[31:0] <= {usec_r[15:0],sec_r[31:16]};
if (stb_time[2]) usec_r[19:0] <= usec[19:0];
else if (time_out) usec_r[19:0] <= {16'h0,usec_r[19:16]};
//reset_data_counters; // reset data transfer counters (only when DMA and compressor are disabled)
// if (reset_data_counters ) etrax_dma[3:0] <= 0; // not needed to be reset after frame, and that was wrong (to early)
if (!en ) etrax_dma[3:0] <= 0; // Now en here waits for flashing to end, so it should not be too early
else if (qv) etrax_dma[3:0] <= etrax_dma[3:0] + 1;
......@@ -366,4 +410,21 @@ end
dly_16 #(.WIDTH(1)) i_pre_flush_end_delayed(.clk(~clk),.rst(1'b0), .dly(14), .din(size_out[1]), .dout(pre_flush_end_delayed)); // dly=14+1 // rather arbitrary?
assign done = flush_end_delayed;
// extract strart of frame run from different clock, re-clock from the source
always @ (posedge fradv_clk) color_first_r <= color_first;
pulse_cross_clock stb_start_i (.rst(rst), .src_clk(fradv_clk), .dst_clk(~clk), .in_pulse(!color_first && color_first_r), .out_pulse(stb_start),.busy());
timestamp_fifo timestamp_fifo_i (
.rst (rst), // input
.sclk (mclk), // input
.pre_stb (ts_pre_stb), // input
.din (ts_data), // input[7:0]
// may use stb_start @ negedge clk
.aclk (~clk), //fradv_clk), // input
.advance (stb_start), // color_first), // input
.rclk (~clk), // input
.rstb (ts_rstb), // input
.dout (ts_dout) // output[7:0] reg
);
endmodule
util_modules/cmd_frame_sequencer.v
View file @ f485624d
......@@ -19,6 +19,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
// Comments from the x353 code:
// This command sequencer is designed (together with i2c sequencer) to provide
// pipelined operation of the sensor, FPGA pre-processor and compressor, to avoid
// requirement of resetting the circuitry and loosing several frames when the sensor
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment