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Commit f4751492 authored by Andrey Filippov's avatar Andrey Filippov
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debugging, more corrections, tested block write through PIO channel 1

parent bb237119
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Showing with 324 additions and 58 deletions
ddrc_test01_testbench.tf
View file @ f4751492
...@@ -269,7 +269,7 @@ module ddrc_test01_testbench #( ...@@ -269,7 +269,7 @@ module ddrc_test01_testbench #(
reg [ 9:0] SIMUL_AXI_ADDR; reg [ 9:0] SIMUL_AXI_ADDR;
// SuppressWarnings VEditor // SuppressWarnings VEditor
reg SIMUL_AXI_FULL; // some data available reg SIMUL_AXI_FULL; // some data available
wire SIMUL_AXI_EMPTY= ~rvalid && rready && (rid==LAST_ARID); // use it to wait for?
reg [31:0] registered_rdata; reg [31:0] registered_rdata;
reg CLK; reg CLK;
...@@ -1069,7 +1069,7 @@ simul_axi_read #( ...@@ -1069,7 +1069,7 @@ simul_axi_read #(
task run_read_block; task run_read_block;
begin begin
$display("RUN WRITE BLOCK @ %t",$time); $display("RUN READ BLOCK @ %t",$time);
run_sequence(0,READ_BLOCK_OFFSET); run_sequence(0,READ_BLOCK_OFFSET);
end end
endtask endtask
......
includes/x393_parameters.vh
View file @ f4751492
...@@ -91,7 +91,7 @@ ...@@ -91,7 +91,7 @@
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter CHNBUF_READ_LATENCY = 0, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data)) parameter CHNBUF_READ_LATENCY = 1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter DFLT_DQS_PATTERN= 8'h55, parameter DFLT_DQS_PATTERN= 8'h55,
parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00 parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00
......
includes/x393_tasks01.vh
View file @ f4751492
...@@ -19,7 +19,13 @@ ...@@ -19,7 +19,13 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> . * along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/ *******************************************************************************/
// Low-level tasks // Low-level tasks
// alternative way to check for empty read queue (without a separate counter)
task wait_read_queue_empty;
begin
wait (~rvalid && rready && (rid==LAST_ARID)); // nothing left in read queue?
SIMUL_AXI_FULL<=1'b0;
end
endtask
task axi_set_rd_lag; task axi_set_rd_lag;
input [3:0] lag; input [3:0] lag;
begin begin
......
memctrl/mcntrl393.v
View file @ f4751492
...@@ -100,7 +100,7 @@ module mcntrl393 #( ...@@ -100,7 +100,7 @@ module mcntrl393 #(
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter CHNBUF_READ_LATENCY = 0, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data)) parameter CHNBUF_READ_LATENCY = 1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter DFLT_DQS_PATTERN= 8'h55, parameter DFLT_DQS_PATTERN= 8'h55,
parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00 parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00
...@@ -545,7 +545,7 @@ module mcntrl393 #( ...@@ -545,7 +545,7 @@ module mcntrl393 #(
assign select_buf3_w = ((axiwr_pre_awaddr ^ MCONTR_BUF3_WR_ADDR) & MCONTR_WR_MASK)==0; assign select_buf3_w = ((axiwr_pre_awaddr ^ MCONTR_BUF3_WR_ADDR) & MCONTR_WR_MASK)==0;
assign select_buf4_w = ((axird_pre_araddr ^ MCONTR_BUF4_RD_ADDR) & MCONTR_RD_MASK)==0; assign select_buf4_w = ((axird_pre_araddr ^ MCONTR_BUF4_RD_ADDR) & MCONTR_RD_MASK)==0;
always @ (axi_rst or axi_clk) begin always @ (posedge axi_rst or posedge axi_clk) begin
if (axi_rst) select_cmd0 <= 0; if (axi_rst) select_cmd0 <= 0;
else if (axiwr_start_burst) select_cmd0 <= select_cmd0_w; else if (axiwr_start_burst) select_cmd0 <= select_cmd0_w;
...@@ -567,7 +567,7 @@ module mcntrl393 #( ...@@ -567,7 +567,7 @@ module mcntrl393 #(
if (axi_rst) axird_selected_r <= 0; if (axi_rst) axird_selected_r <= 0;
else if (axird_start_burst) axird_selected_r <= select_buf0_w || select_buf1_w ||select_buf2_w; else if (axird_start_burst) axird_selected_r <= select_buf0_w || select_buf1_w ||select_buf2_w;
end end
always @ (axi_clk) begin always @ (posedge axi_clk) begin
if (axiwr_wen) buf_wdata <= axiwr_data; if (axiwr_wen) buf_wdata <= axiwr_data;
if (axiwr_wen) buf_waddr <= axiwr_waddr; if (axiwr_wen) buf_waddr <= axiwr_waddr;
cmd_we <= axiwr_wen && select_cmd0; cmd_we <= axiwr_wen && select_cmd0;
...@@ -1101,7 +1101,7 @@ module mcntrl393 #( ...@@ -1101,7 +1101,7 @@ module mcntrl393 #(
.channel_pgm_en1 (channel_pgm_en1), // output reg .channel_pgm_en1 (channel_pgm_en1), // output reg
.seq_data1 ({22'b0,seq_data0}), // input[31:0] // same as for channel 0 .seq_data1 ({22'b0,seq_data0}), // input[31:0] // same as for channel 0
.seq_wr1 (1'b0), // not used: seq_wr1), // input .seq_wr1 (1'b0), // not used: seq_wr1), // input
.seq_set1 (1'b0), // not used: seq_set1), // input .seq_set1 (seq_set0), // seq_set0 from channel 0 (shared in ps_pio), // input
.seq_done1 (seq_done1), // output .seq_done1 (seq_done1), // output
.rpage_nxt_chn1 (rpage_nxt_chn1), // output .rpage_nxt_chn1 (rpage_nxt_chn1), // output
.buf_rd_chn1 (buf_rd_chn1), // output .buf_rd_chn1 (buf_rd_chn1), // output
......
memctrl/memctrl16.v
View file @ f4751492
This diff is collapsed.
util_modules/mcont_from_chnbuf_reg.v
View file @ f4751492
...@@ -22,7 +22,7 @@ ...@@ -22,7 +22,7 @@
module mcont_from_chnbuf_reg #( module mcont_from_chnbuf_reg #(
parameter CHN_NUMBER=0, parameter CHN_NUMBER=0,
parameter CHN_LATENCY=0 // 0 - no extra latency in extrenal BRAM - data available next cycle after re (but prev. data) parameter CHN_LATENCY=1 // 0 - no extra latency in extrenal BRAM - data available next cycle after regen (1 extra from ren)
)( )(
input rst, input rst,
input clk, input clk,
......
x393.v
View file @ f4751492
...@@ -96,7 +96,7 @@ module x393 #( ...@@ -96,7 +96,7 @@ module x393 #(
parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller parameter MCONTR_TOP_STATUS_REG_ADDR= 'h1, // 8 or less bits: status register address to use for memory controller
parameter CHNBUF_READ_LATENCY = 0, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data)) parameter CHNBUF_READ_LATENCY = 1, // external channel buffer extra read latency ( 0 - data available next cycle after re (but prev. data))
parameter DFLT_DQS_PATTERN= 8'h55, parameter DFLT_DQS_PATTERN= 8'h55,
parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00 parameter DFLT_DQM_PATTERN= 8'h00, // 8'h00
......
x393_testbench01.sav
View file @ f4751492
[*] [*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI [*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
[*] Thu Feb 12 06:17:01 2015 [*] Fri Feb 13 00:32:14 2015
[*] [*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150211231241531.lxt" [dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150212171214320.lxt"
[dumpfile_mtime] "Thu Feb 12 06:16:34 2015" [dumpfile_mtime] "Fri Feb 13 00:16:41 2015"
[dumpfile_size] 89243462 [dumpfile_size] 226686145
[savefile] "/home/andrey/git/x393/x393_testbench01.sav" [savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 76630000 [timestart] 141310400
[size] 1823 1180 [size] 1823 1173
[pos] 1922 0 [pos] 1922 0
*-23.698503 135570000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-14.698502 141381875 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01. [treeopen] x393_testbench01.
[treeopen] x393_testbench01.x393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_deser_16bit_i.
...@@ -23,7 +24,7 @@ ...@@ -23,7 +24,7 @@
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16. [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.i_index_max_16.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i. [treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i. [treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.
[sst_width] 202 [sst_width] 328
[signals_width] 377 [signals_width] 377
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 371 [sst_vpaned_height] 371
...@@ -31,10 +32,10 @@ ...@@ -31,10 +32,10 @@
-top_simulation -top_simulation
@28 @28
x393_testbench01.CLK[0] x393_testbench01.CLK[0]
@29
x393_testbench01.WAITING_STATUS[0] x393_testbench01.WAITING_STATUS[0]
@28
x393_testbench01.AXI_RD_EMPTY[0] x393_testbench01.AXI_RD_EMPTY[0]
x393_testbench01.SIMUL_AXI_EMPTY[0]
x393_testbench01.SIMUL_AXI_FULL[0]
@22 @22
x393_testbench01.SIMUL_AXI_ADDR[15:0] x393_testbench01.SIMUL_AXI_ADDR[15:0]
x393_testbench01.SIMUL_AXI_READ[31:0] x393_testbench01.SIMUL_AXI_READ[31:0]
...@@ -48,8 +49,6 @@ x393_testbench01.rstb[0] ...@@ -48,8 +49,6 @@ x393_testbench01.rstb[0]
@22 @22
x393_testbench01.rdata[31:0] x393_testbench01.rdata[31:0]
x393_testbench01.SIMUL_AXI_ADDR_W[15:0] x393_testbench01.SIMUL_AXI_ADDR_W[15:0]
@28
x393_testbench01.SIMUL_AXI_FULL[0]
@c00022 @c00022
x393_testbench01.registered_rdata[31:0] x393_testbench01.registered_rdata[31:0]
@28 @28
...@@ -1396,6 +1395,34 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wpage_in[1:0] ...@@ -1396,6 +1395,34 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wpage_set[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn0_buf_i.wpage_set[0]
@1000200 @1000200
-PS_PIO_CHN0 -PS_PIO_CHN0
@200
-
@800200
-PS_PIO_CHN1
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.data_out[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_data_in[31:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_waddr[9:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.ext_we[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.page[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.page_next[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.page_r[1:0]
@22
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.raddr[6:0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rclk[0]
@29
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rd[0]
@28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.regen[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rpage_in[1:0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.chn1_buf_i.rpage_set[0]
@1000200
-PS_PIO_CHN1
@28 @28
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_rd_chn1[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.buf_rd_chn1[0]
@22 @22
...@@ -1493,9 +1520,38 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq0[0] ...@@ -1493,9 +1520,38 @@ x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq0[0]
x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq1[0] x393_testbench01.x393_i.mcntrl393_i.mcntrl_ps_pio_i.want_rq1[0]
@1000200 @1000200
-PS_PIO -PS_PIO
@c00200 @800200
-memcntrl16_0 -memcntrl16_0
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rchn_late[3:0]
@28 @28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rd_late[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.buf_rdata_chn1[63:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rdata1[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rpage_nxt[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rchn[3:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rdata[63:0]
@200
-
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.buf_chn_sel[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.buf_rd_chn[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.buf_rdata_chn[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.clk[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.ext_buf_rchn[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.ext_buf_rd[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.ext_buf_rdata[63:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.ext_buf_rrefresh[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcont_from_chnbuf_reg1_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.mclk[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.mclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_enabled[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_enabled[0]
@22 @22
...@@ -1526,6 +1582,30 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_done0[0] ...@@ -1526,6 +1582,30 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.seq_done0[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_addr[10:0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_addr[10:0]
@28 @28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_busy[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_busy[0]
@800200
-memcntr_sequencer
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_nop[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_addr_in[14:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_bank_in[2:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rcw_pos[2:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_odt_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cke_dis[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_sel_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_en_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_en_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dqs_toggle_en[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_dq_en_in[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_wr[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rd[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cmd_add_pause[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_buf_rst[0]
@1000200
-memcntr_sequencer
@200 @200
- -
@800200 @800200
...@@ -1549,7 +1629,6 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.we ...@@ -1549,7 +1629,6 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd0_buf_i.we
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rrefresh[0] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ext_buf_rrefresh[0]
@1000200 @1000200
-cmd0_buf -cmd0_buf
@1401200
-memcntrl16_0 -memcntrl16_0
@c00200 @c00200
-max_0001 -max_0001
......
x393_testbench01.tf
View file @ f4751492
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