Commit f20d9c9f authored by Oleg Dzhimiev's avatar Oleg Dzhimiev

init for 14MPx

parent c4bd1f1f
-d TARGET_MODE=1
-f /usr/local/verilog/system_defines.vh
-f /usr/local/verilog/x393_parameters.vh /usr/local/verilog/x393_cur_params_target.vh /usr/local/verilog/x393_localparams.vh
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c bitstream_set_path /usr/local/verilog/x393_hispi.bit
-c setupSensorsPower "HISPI"
-c measure_all "*DI"
-c setSensorClock 24.0 "2V5_LVDS"
-c set_rtc
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