starting compressor simulation

.settings/com.elphel.vdt.iverilog.prefs

-com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->
+com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_113_SaveLogsSimulator<-@\#\#@->
 eclipse.preferences.version=1
 iverilog_100_TopModulesOther=glbl<-@\#\#@->
 iverilog_101_TopModulesOther=glbl<-@\#\#@->
@@ -6,6 +6,7 @@ iverilog_102_ExtraFiles=glbl.v<-@\#\#@->
 iverilog_103_ExtraFiles=glbl.v<-@\#\#@->
 iverilog_103_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
 iverilog_104_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
+iverilog_113_SaveLogsSimulator=true
 iverilog_77_Param_Exe=/usr/local/bin/iverilog
 iverilog_78_VVP_Exe=/usr/local/bin/vvp
 iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave

sensor/sens_histogram.v

@@ -132,7 +132,7 @@ module  sens_histogram #(
 
     assign hist_rq = hist_rq_r;
     assign hist_dv = hist_re[2];
-    assign hist_xfer_done_mclk = hist_out_d && !hist_out_d && hist_en;
+    assign hist_xfer_done_mclk = hist_out_d && !hist_out && hist_en;
 
 //AF2015-new mod
     wire       line_start_w = hact && !hact_d[0];
@@ -295,7 +295,8 @@ module  sens_histogram #(
 //        else                                     inc_r <= {14'b0,inc_w[17:0]};
         
     end
-
+    // after hist_out was off, require inactive grant before sending rq
+    reg en_rq_start;
     
     always @ (posedge mclk) begin
         en_mclk <= en;
@@ -305,14 +306,20 @@ module  sens_histogram #(
         else if (&hist_raddr)    hist_out <= 0;
         
         hist_out_d <= hist_out;
-        
-        if      (!en_mclk)       hist_raddr <= 0;
-        else if (hist_re)        hist_raddr <= hist_raddr + 1;
+        // reset address each time new transfer is started
+//        if      (!en_mclk || (hist_out && !hist_out_d)) hist_raddr <= 0;
+        if      (!hist_out)  hist_raddr <= 0;
+        else if (hist_re[0]) hist_raddr <= hist_raddr + 1;
         
 //        if      (!en_mclk)             hist_rq_r <= 0;
 //        else if (hist_out && !hist_re) hist_rq_r <= 1;
 
-        hist_rq_r <= en_mclk && hist_out && !(&hist_raddr);
+//        hist_rq_r <= en_mclk && hist_out && !(&hist_raddr);
+// prevent starting rq if grant is still on (back-to-back)
+        if      (!hist_out)   en_rq_start <= 0;
+        else if (!hist_grant) en_rq_start <= 1;
+//        hist_rq_r <= en_mclk && hist_out && !(&hist_raddr) && ((|hist_raddr[9:0]) || !hist_grant);
+        hist_rq_r <= en_mclk && hist_out && !(&hist_raddr) && en_rq_start;
         
         if      (!hist_out || (&hist_raddr[7:0])) hist_re[0] <= 0;
         else if (hist_grant && hist_out)          hist_re[0] <= 1;

sensor/sens_histogram_mux.v

@@ -45,7 +45,7 @@ module  sens_histogram_mux(
     input  [31:0] din3,
 
     output        rq,
-    input         grant,
+    input         grant, // grant may stay longer, not masked by rq?
     output  [1:0] chn,
     output        dv,
     output [31:0] dout
@@ -122,7 +122,8 @@ module  sens_histogram_mux(
         else if (burst_next[3]) burst3 <= burst3 + 1;
         
         if (!en) chn_grant <= 0;
-        else     chn_grant <= {4{grant}} & chn_sel;
+        else     chn_grant <= {4{grant & rq}} & chn_sel;
+//        else     chn_grant <= {4{grant & rq}} & chn_sel;
 //        start_r <= en & start_w;
         if (!en )         rq_out <= 0;
         else if (started) rq_out <= 1;