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Commit f026775f authored by Andrey Filippov's avatar Andrey Filippov
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fixed a bug caused by a counter-intuitive CLKINSEL in MMCME2_ADV

parent 50c837f9
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Showing with 16 additions and 174 deletions
.project
View file @ f026775f
......@@ -92,7 +92,7 @@
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150719165235946.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150719200102645.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
......@@ -102,7 +102,7 @@
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150719165235946.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150719200102645.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
......@@ -112,7 +112,7 @@
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150719165235946.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150719200102645.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
......@@ -132,7 +132,7 @@
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150719165235946.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150719200102645.dcp</location>
</link>
</linkedResources>
</projectDescription>
memctrl/phy/phy_top.v
View file @ f026775f
......@@ -335,7 +335,7 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
) mmcm_phase_cntr_i (
.clkin1 (clk_in), // input
.clkin2 (1'b0), // input
.clkinsel (1'b0), // input
.sel_clk2 (1'b0), // input
.clkfbin (clk_fb), // input
// .rst (rst), // input
.rst (rst_in), // input
......
sensor/sens_parallel12.v
View file @ f026775f
......@@ -595,7 +595,7 @@ module sens_parallel12 #(
) mmcm_phase_cntr_i (
.clkin1 (pclk), // input
.clkin2 (ibpf), // input
.clkinsel (sel_ext_clk), // input
.sel_clk2 (sel_ext_clk), // input
.clkfbin (clk_fb), // input
.rst (rst_mmcm), // input
.pwrdwn (1'b0), // input
......
util_modules/clocks393.v
View file @ f026775f
......@@ -121,7 +121,6 @@ module clocks393#(
wire memclk_rst = reset_clk[4];
wire ffclk0_rst = reset_clk[5];
wire ffclk1_rst = reset_clk[6];
always @ (posedge mclk or posedge rst) begin
if (rst) reset_clk <= 0;
else if (set_ctrl_w) reset_clk <= {cmd_data[10:8], cmd_data[3:0]};
......
wrap/mmcm_phase_cntr.v
View file @ f026775f
......@@ -73,7 +73,7 @@ module mmcm_phase_cntr#(
(
input clkin1, // General clock input
input clkin2, // Alternative clock input
input clkinsel, // Clock input select
input sel_clk2, // Clock input select (inverted from MMCME2_ADV !!!)
input clkfbin, // Feedback clock input
input rst, // asynchronous reset input
input pwrdwn, // power down input
......@@ -209,7 +209,7 @@ module mmcm_phase_cntr#(
.CLKFBIN (clkfbin), // input
.CLKIN1 (clkin1), // input
.CLKIN2 (clkin2), // input
.CLKINSEL (clkinsel), // input Select CLKIN1
.CLKINSEL (~sel_clk2), // input 0: Select CLKIN2, 1: Select CLKIN1 !!!!!!!!!!!!!
.DADDR (7'b0), // Dynamic reconfiguration address (input[6:0])
.DCLK (1'b0), // Dynamic reconfiguration clock input
.DEN (1'b0), // Dynamic reconfiguration enable input
......
x393.v
View file @ f026775f
......@@ -91,7 +91,7 @@ module x393 #(
,output DUMMY_TO_KEEP
);
assign DUMMY_TO_KEEP = frst[2] && fclk[1];
assign DUMMY_TO_KEEP = frst[2] && fclk[1];
// localparam ADDRESS_NUMBER=15;
// localparam COLADDR_NUMBER=10;
......
x393.xdc
View file @ f026775f
......@@ -213,163 +213,6 @@ set_property PACKAGE_PIN T11 [get_ports {DUMMY_TO_KEEP}]
set_property PACKAGE_PIN M5 [get_ports {memclk}]
# ================= Sensor port 0 =================
# inout [7:0] sns1_dp,
# inout [7:0] sns1_dn,
set_property PACKAGE_PIN T10 [get_ports {sns1_dp[0]}]
set_property PACKAGE_PIN T9 [get_ports {sns1_dn[0]}]
set_property PACKAGE_PIN U10 [get_ports {sns1_dp[1]}]
set_property PACKAGE_PIN V10 [get_ports {sns1_dn[1]}]
set_property PACKAGE_PIN V8 [get_ports {sns1_dp[2]}]
set_property PACKAGE_PIN W8 [get_ports {sns1_dn[2]}]
set_property PACKAGE_PIN W9 [get_ports {sns1_dp[3]}]
set_property PACKAGE_PIN Y8 [get_ports {sns1_dn[3]}]
set_property PACKAGE_PIN AB9 [get_ports {sns1_dp[4]}]
set_property PACKAGE_PIN AB8 [get_ports {sns1_dn[4]}]
set_property PACKAGE_PIN AB13 [get_ports {sns1_dp[5]}]
set_property PACKAGE_PIN AB12 [get_ports {sns1_dn[5]}]
set_property PACKAGE_PIN AA12 [get_ports {sns1_dp[6]}]
set_property PACKAGE_PIN AA11 [get_ports {sns1_dn[6]}]
set_property PACKAGE_PIN W11 [get_ports {sns1_dp[7]}]
set_property PACKAGE_PIN W10 [get_ports {sns1_dn[7]}]
# inout sns1_clkp,
# inout sns1_clkn,
set_property PACKAGE_PIN AA10 [get_ports {sns1_clkp}]
set_property PACKAGE_PIN AB10 [get_ports {sns1_clkn}]
# inout sns1_scl,
# inout sns1_sda,
set_property PACKAGE_PIN Y9 [get_ports {sns1_scl}]
set_property PACKAGE_PIN AA9 [get_ports {sns1_sda}]
# inout sns1_ctl,
# inout sns1_pg,
set_property PACKAGE_PIN U9 [get_ports {sns1_ctl}]
set_property PACKAGE_PIN U8 [get_ports {sns1_pg}]
# ================= Sensor port 1 =================
# inout [7:0] sns2_dp,
# inout [7:0] sns2_dn,
set_property PACKAGE_PIN U15 [get_ports {sns2_dp[0]}]
set_property PACKAGE_PIN U14 [get_ports {sns2_dn[0]}]
set_property PACKAGE_PIN V15 [get_ports {sns2_dp[1]}]
set_property PACKAGE_PIN W15 [get_ports {sns2_dn[1]}]
set_property PACKAGE_PIN U13 [get_ports {sns2_dp[2]}]
set_property PACKAGE_PIN V13 [get_ports {sns2_dn[2]}]
set_property PACKAGE_PIN V12 [get_ports {sns2_dp[3]}]
set_property PACKAGE_PIN V11 [get_ports {sns2_dn[3]}]
set_property PACKAGE_PIN AA17 [get_ports {sns2_dp[4]}]
set_property PACKAGE_PIN AB17 [get_ports {sns2_dn[4]}]
set_property PACKAGE_PIN AA15 [get_ports {sns2_dp[5]}]
set_property PACKAGE_PIN AB15 [get_ports {sns2_dn[5]}]
set_property PACKAGE_PIN AA14 [get_ports {sns2_dp[6]}]
set_property PACKAGE_PIN AB14 [get_ports {sns2_dn[6]}]
set_property PACKAGE_PIN Y14 [get_ports {sns2_dp[7]}]
set_property PACKAGE_PIN Y13 [get_ports {sns2_dn[7]}]
# inout sns2_clkp,
# inout sns2_clkn,
set_property PACKAGE_PIN Y16 [get_ports {sns2_clkp}]
set_property PACKAGE_PIN AA16 [get_ports {sns2_clkn}]
# inout sns2_scl,
# inout sns2_sda,
set_property PACKAGE_PIN T12 [get_ports {sns2_scl}]
set_property PACKAGE_PIN U12 [get_ports {sns2_sda}]
# inout sns2_ctl,
# inout sns2_pg,
set_property PACKAGE_PIN V16 [get_ports {sns2_ctl}]
set_property PACKAGE_PIN W16 [get_ports {sns2_pg}]
# ================= Sensor port 2 =================
# inout [7:0] sns3_dp,
# inout [7:0] sns3_dn,
set_property PACKAGE_PIN AA22 [get_ports {sns3_dp[0]}]
set_property PACKAGE_PIN AB22 [get_ports {sns3_dn[0]}]
set_property PACKAGE_PIN W21 [get_ports {sns3_dp[1]}]
set_property PACKAGE_PIN Y22 [get_ports {sns3_dn[1]}]
set_property PACKAGE_PIN V21 [get_ports {sns3_dp[2]}]
set_property PACKAGE_PIN V22 [get_ports {sns3_dn[2]}]
set_property PACKAGE_PIN W19 [get_ports {sns3_dp[3]}]
set_property PACKAGE_PIN W20 [get_ports {sns3_dn[3]}]
set_property PACKAGE_PIN N21 [get_ports {sns3_dp[4]}]
set_property PACKAGE_PIN N22 [get_ports {sns3_dn[4]}]
set_property PACKAGE_PIN R22 [get_ports {sns3_dp[5]}]
set_property PACKAGE_PIN T22 [get_ports {sns3_dn[5]}]
set_property PACKAGE_PIN P21 [get_ports {sns3_dp[6]}]
set_property PACKAGE_PIN R21 [get_ports {sns3_dn[6]}]
set_property PACKAGE_PIN T20 [get_ports {sns3_dp[7]}]
set_property PACKAGE_PIN U20 [get_ports {sns3_dn[7]}]
# inout sns3_clkp,
# inout sns3_clkn,
set_property PACKAGE_PIN T21 [get_ports {sns3_clkp}]
set_property PACKAGE_PIN U22 [get_ports {sns3_clkn}]
# inout sns3_scl,
# inout sns3_sda,
set_property PACKAGE_PIN Y21 [get_ports {sns3_scl}]
set_property PACKAGE_PIN AA21 [get_ports {sns3_sda}]
# inout sns3_ctl,
# inout sns3_pg,
set_property PACKAGE_PIN AA20 [get_ports {sns3_ctl}]
set_property PACKAGE_PIN AB20 [get_ports {sns3_pg}]
# ================= Sensor port 3 =================
# inout [7:0] sns4_dp,
# inout [7:0] sns4_dn,
set_property PACKAGE_PIN V17 [get_ports {sns4_dp[0]}]
set_property PACKAGE_PIN W18 [get_ports {sns4_dn[0]}]
set_property PACKAGE_PIN Y19 [get_ports {sns4_dp[1]}]
set_property PACKAGE_PIN AA19 [get_ports {sns4_dn[1]}]
set_property PACKAGE_PIN U19 [get_ports {sns4_dp[2]}]
set_property PACKAGE_PIN V20 [get_ports {sns4_dn[2]}]
set_property PACKAGE_PIN U18 [get_ports {sns4_dp[3]}]
set_property PACKAGE_PIN V18 [get_ports {sns4_dn[3]}]
set_property PACKAGE_PIN P18 [get_ports {sns4_dp[4]}]
set_property PACKAGE_PIN P19 [get_ports {sns4_dn[4]}]
set_property PACKAGE_PIN N17 [get_ports {sns4_dp[5]}]
set_property PACKAGE_PIN N18 [get_ports {sns4_dn[5]}]
set_property PACKAGE_PIN N20 [get_ports {sns4_dp[6]}]
set_property PACKAGE_PIN P20 [get_ports {sns4_dn[6]}]
set_property PACKAGE_PIN R17 [get_ports {sns4_dp[7]}]
set_property PACKAGE_PIN R18 [get_ports {sns4_dn[7]}]
# inout sns4_clkp,
# inout sns4_clkn,
set_property PACKAGE_PIN R16 [get_ports {sns4_clkp}]
set_property PACKAGE_PIN T16 [get_ports {sns4_clkn}]
# inout sns4_scl,
# inout sns4_sda,
set_property PACKAGE_PIN AB18 [get_ports {sns4_scl}]
set_property PACKAGE_PIN AB19 [get_ports {sns4_sda}]
# inout sns4_ctl,
# inout sns4_pg,
set_property PACKAGE_PIN Y17 [get_ports {sns4_ctl}]
set_property PACKAGE_PIN Y18 [get_ports {sns4_pg}]
# ======== GPIO pins ===============
# inout [GPIO_N-1:0] gpio_pins,
set_property PACKAGE_PIN B4 [get_ports {gpio_pins[0]}]
......
x393_timing.xdc
View file @ f026775f
......@@ -69,15 +69,15 @@ create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
###create_generated_clock -name ddr3_mclk [get_nets */mclk_pre ]
###create_generated_clock -name ddr3_clk_ref [get_nets */clk_ref_pre]
####create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
####create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
####create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
####create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
####create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
####set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
# do not check timing between clk_axihp_pre and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
####set_clock_groups -name ps_async_clock_axihp -asynchronous -group {clk_axihp_pre}
set_clock_groups -name ps_async_clock_axihp -asynchronous -group {clk_axihp_pre}
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