Skip to content

X
x393
Commit effa97e5 authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

exported compressor channel status, some typo fixes

parent 066db42f
Hide whitespace changes
Inline Side-by-side
Showing with 77 additions and 15 deletions
py393/generated/x393.c
View file @ effa97e5
......@@ -290,6 +290,11 @@ void x393_cmprs_interrupts (x393_cmprs_int
void x393_cmprs_tables_data (u32 d, int cmprs_chn){writel(d, (void *) (0x40001818 + 0x40 * cmprs_chn));} // Compressor tables data
void x393_cmprs_tables_address (x393_cmprs_table_addr_t d, int cmprs_chn){writel(d.d32, (void *) (0x4000181c + 0x40 * cmprs_chn));} // Compressor tables type/address
// Compressor channel status)
x393_cmprs_status_t x393_cmprs_status (int chn) { x393_cmprs_status_t d; d.d32 = readl((void*) (0x40002040 + 0x4 * chn)); return d; } // Status of the compressor channel (incl. interrupt
u32 x393_cmprs_hifreq (int chn) { u32 d; d = readl((void*) (0x40002050 + 0x4 * chn)); return d; } // Focus helper high-frequency amount
// Compressor DMA control:
// Camera can be configured to use either 2 AXI HP channels (with 2 compressors served by each one) or to use a single AXI HP channel
......@@ -386,7 +391,7 @@ u32 get_x393_camsync_trig_delay (int sens_chn)
void x393_cmdframeseq_ctrl (x393_cmdframeseq_mode_t d, int sens_chn){writel(d.d32, (void *) (0x40001e7c + 0x80 * sens_chn));} // CMDFRAMESEQ control register
void x393_cmdframeseq_abs (u32 d, int sens_chn, int offset){writel(d, (void *) (0x40001e00 + 0x20 * sens_chn + 0x1 * offset));} // CMDFRAMESEQ absolute frame address/command
void x393_cmdframeseq_rel (u32 d, int sens_chn, int offset){writel(d, (void *) (0x40001e40 + 0x20 * sens_chn + 0x1 * offset));} // CMDFRAMESEQ relative frame address/command
// Command sequencer multiplexer, provides current frame number for each sesnor channel and interrupt status/interrupt masks for them.
// Command sequencer multiplexer, provides current frame number for each sensor channel and interrupt status/interrupt masks for them.
// Interrupts and interrupt masks are controlled through channel CMDFRAMESEQ module
void set_x393_cmdseqmux_status_ctrl (x393_status_ctrl_t d){writel(d.d32, (void *) 0x40001c08);} // CMDSEQMUX status control mode (status provides current frame numbers)
x393_status_ctrl_t get_x393_cmdseqmux_status_ctrl (void) { x393_status_ctrl_t d; d.d32 = readl((void*) 0x40001c08); return d; }
......
py393/generated/x393.h
View file @ effa97e5
......@@ -336,6 +336,11 @@ void x393_cmprs_interrupts (x393_cmprs_int
void x393_cmprs_tables_data (u32 d, int cmprs_chn); // Compressor tables data
void x393_cmprs_tables_address (x393_cmprs_table_addr_t d, int cmprs_chn); // Compressor tables type/address
// Compressor channel status)
x393_cmprs_status_t x393_cmprs_status (int chn); // Status of the compressor channel (incl. interrupt
u32 x393_cmprs_hifreq (int chn); // Focus helper high-frequency amount
// Compressor DMA control:
// Camera can be configured to use either 2 AXI HP channels (with 2 compressors served by each one) or to use a single AXI HP channel
......@@ -432,7 +437,7 @@ u32 get_x393_camsync_trig_delay (int sens_chn);
void x393_cmdframeseq_ctrl (x393_cmdframeseq_mode_t d, int sens_chn); // CMDFRAMESEQ control register
void x393_cmdframeseq_abs (u32 d, int sens_chn, int offset); // CMDFRAMESEQ absolute frame address/command
void x393_cmdframeseq_rel (u32 d, int sens_chn, int offset); // CMDFRAMESEQ relative frame address/command
// Command sequencer multiplexer, provides current frame number for each sesnor channel and interrupt status/interrupt masks for them.
// Command sequencer multiplexer, provides current frame number for each sensor channel and interrupt status/interrupt masks for them.
// Interrupts and interrupt masks are controlled through channel CMDFRAMESEQ module
void set_x393_cmdseqmux_status_ctrl (x393_status_ctrl_t d); // CMDSEQMUX status control mode (status provides current frame numbers)
x393_status_ctrl_t get_x393_cmdseqmux_status_ctrl (void);
......
py393/generated/x393_defs.h
View file @ effa97e5
......@@ -278,6 +278,11 @@
#define X393_CMPRS_TABLES_DATA(cmprs_chn) (0x40001818 + 0x40 * (cmprs_chn)) // Compressor tables data, cmprs_chn = 0..3, data type: u32 (wo)
#define X393_CMPRS_TABLES_ADDRESS(cmprs_chn) (0x4000181c + 0x40 * (cmprs_chn)) // Compressor tables type/address, cmprs_chn = 0..3, data type: x393_cmprs_table_addr_t (wo)
// Compressor channel status)
#define X393_CMPRS_STATUS(chn) (0x40002040 + 0x4 * (chn)) // Status of the compressor channel (incl. interrupt, chn = 0..3, data type: x393_cmprs_status_t (ro)
#define X393_CMPRS_HIFREQ(chn) (0x40002050 + 0x4 * (chn)) // Focus helper high-frequency amount, chn = 0..3, data type: u32 (ro)
// Compressor DMA control:
// Camera can be configured to use either 2 AXI HP channels (with 2 compressors served by each one) or to use a single AXI HP channel
......@@ -359,7 +364,7 @@
#define X393_CMDFRAMESEQ_CTRL(sens_chn) (0x40001e7c + 0x80 * (sens_chn)) // CMDFRAMESEQ control register, sens_chn = 0..3, data type: x393_cmdframeseq_mode_t (wo)
#define X393_CMDFRAMESEQ_ABS(sens_chn,offset) (0x40001e00)+ 0x20 * (sens_chn)+ 0x1 * (offset)) // CMDFRAMESEQ absolute frame address/command, sens_chn = 0..3, offset = 0..15, data type: u32 (wo)
#define X393_CMDFRAMESEQ_REL(sens_chn,offset) (0x40001e40)+ 0x20 * (sens_chn)+ 0x1 * (offset)) // CMDFRAMESEQ relative frame address/command, sens_chn = 0..3, offset = 0..14, data type: u32 (wo)
// Command sequencer multiplexer, provides current frame number for each sesnor channel and interrupt status/interrupt masks for them.
// Command sequencer multiplexer, provides current frame number for each sensor channel and interrupt status/interrupt masks for them.
// Interrupts and interrupt masks are controlled through channel CMDFRAMESEQ module
#define X393_CMDSEQMUX_STATUS_CTRL 0x40001c08 // CMDSEQMUX status control mode (status provides current frame numbers), data type: x393_status_ctrl_t (rw)
#define X393_CMDSEQMUX_STATUS 0x400020e0 // CMDSEQMUX status data (frame numbers and interrupts, data type: x393_cmdseqmux_status_t (ro)
......
py393/generated/x393_map.h
View file @ effa97e5
......@@ -772,7 +772,15 @@
#define X393_MCNTRL_CHN2_STATUS 0x40002014 // Status register for MCNTRL CHN2 (tiled), data type: x393_status_mcntrl_lintile_t (ro)
#define X393_MCNTRL_CHN3_STATUS 0x40002018 // Status register for MCNTRL CHN3 (scanline), data type: x393_status_mcntrl_lintile_t (ro)
#define X393_MCNTRL_CHN4_STATUS 0x4000201c // Status register for MCNTRL CHN4 (tiled), data type: x393_status_mcntrl_lintile_t (ro)
// RESERVED: 0x10 DWORDs
// RESERVED: 0x8 DWORDs
#define X393_CMPRS_STATUS__0 0x40002040 // Status of the compressor channel (incl. interrupt, data type: x393_cmprs_status_t (ro)
#define X393_CMPRS_STATUS__1 0x40002044 // Status of the compressor channel (incl. interrupt, data type: x393_cmprs_status_t (ro)
#define X393_CMPRS_STATUS__2 0x40002048 // Status of the compressor channel (incl. interrupt, data type: x393_cmprs_status_t (ro)
#define X393_CMPRS_STATUS__3 0x4000204c // Status of the compressor channel (incl. interrupt, data type: x393_cmprs_status_t (ro)
#define X393_CMPRS_HIFREQ__0 0x40002050 // Focus helper high-frequency amount, data type: u32 (ro)
#define X393_CMPRS_HIFREQ__1 0x40002054 // Focus helper high-frequency amount, data type: u32 (ro)
#define X393_CMPRS_HIFREQ__2 0x40002058 // Focus helper high-frequency amount, data type: u32 (ro)
#define X393_CMPRS_HIFREQ__3 0x4000205c // Focus helper high-frequency amount, data type: u32 (ro)
#define X393_AFIMUX0_STATUS__0 0x40002060 // Status of the AFI MUX 0 (including image pointer), data type: x393_afimux_status_t (ro)
#define X393_AFIMUX0_STATUS__1 0x40002064 // Status of the AFI MUX 0 (including image pointer), data type: x393_afimux_status_t (ro)
#define X393_AFIMUX0_STATUS__2 0x40002068 // Status of the AFI MUX 0 (including image pointer), data type: x393_afimux_status_t (ro)
......
py393/generated/x393_types.h
View file @ effa97e5
......@@ -613,7 +613,7 @@ typedef union {
u32 ext_clk_set: 1; // [ 9] (0) Set MMCM clock input to 'ext_clk' field
u32 ext_clk: 1; // [ 8] (0) MMCM clock input: 0: clock to the sensor, 1 - clock from the sensor
u32 mmcm_rst_set: 1; // [ 7] (0) MMCM reset set to 'mmcm_rst' field
u32 mmcm_rst: 1; // [ 6] (0) MMCM (for sesnor clock) reset signal
u32 mmcm_rst: 1; // [ 6] (0) MMCM (for sensor clock) reset signal
u32 aro_set: 1; // [ 5] (0) ARO set to the 'aro' field
u32 aro: 1; // [ 4] (0) ARO signal to the sensor
u32 arst_set: 1; // [ 3] (0) ARST set to the 'arst' field
......@@ -632,7 +632,7 @@ typedef union {
u32 ign_embed_set: 1; // [ 9] (0) Set mode to 'ign_embed' field
u32 ign_embed: 1; // [ 8] (0) Ignore embedded data (non-image pixel lines
u32 /*mmcm_rst_set*/: 1; // [ 7] (0) MMCM reset set to 'mmcm_rst' field
u32 /*mmcm_rst*/: 1; // [ 6] (0) MMCM (for sesnor clock) reset signal
u32 /*mmcm_rst*/: 1; // [ 6] (0) MMCM (for sensor clock) reset signal
u32 /*aro_set*/: 1; // [ 5] (0) ARO set to the 'aro' field
u32 /*aro*/: 1; // [ 4] (0) ARO signal to the sensor
u32 /*arst_set*/: 1; // [ 3] (0) ARST set to the 'arst' field
......@@ -960,6 +960,23 @@ typedef union {
};
} x393_cmprs_table_addr_t;
// Compressor channel status
typedef union {
struct {
u32 seq_num: 6; // [31:26] (0) Status sequence number
u32 :21;
u32 flushing_fifo: 1; // [ 4] (0) Compressor channel is flushing FIFO (debug feature)
u32 stuffer_running: 1; // [ 3] (0) Compressor channel bit stuffer is running (debug feature)
u32 reading_frame: 1; // [ 2] (0) Compressor channel is reading frame from memory (debug feature)
u32 im: 1; // [ 1] (0) Compressor channel interrupt mask
u32 is: 1; // [ 0] (0) Compressor channel interrupt status
};
struct {
u32 d32:32; // [31: 0] (0) cast to u32
};
} x393_cmprs_status_t;
// Compressor DMA buffer address (in 32-byte blocks)
typedef union {
......@@ -1181,7 +1198,7 @@ typedef union {
u32 master_chn_set: 1; // [ 9] (0) Set 'master_chn'
u32 master_chn: 2; // [ 8: 7] (0) master sensor channel (zero delay in internal trigger mode, delay used for flash output)
u32 trig_set: 1; // [ 6] (0) Set 'trig'
u32 trig: 1; // [ 5] (1) Sensor triggered mode (0 - free running sesnor)
u32 trig: 1; // [ 5] (1) Sensor triggered mode (0 - free running sensor)
u32 ext_set: 1; // [ 4] (0) Set 'ext'
u32 ext: 1; // [ 3] (1) Use external (received) timestamps, if available. O - use local timestamps
u32 en_snd_set: 1; // [ 2] (0) Set 'en_snd'
......
py393/x393_export_c.py
View file @ effa97e5
......@@ -470,6 +470,10 @@ class X393ExportC(object):
data = self._enc_cmprs_table_addr(),
name = "x393_cmprs_table_addr", typ="wo",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Compressor channel status",
data = self._enc_cmprs_status(),
name = "x393_cmprs_status", typ="ro",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Compressor DMA buffer address (in 32-byte blocks)",
data = self._enc_cmprs_afimux_sa(),
......@@ -905,6 +909,14 @@ class X393ExportC(object):
(("X393_CMPRS_TABLES_DATA", c, vrlg.CMPRS_TABLES + 0 + ba, ia, z3, "u32*", "wo", "Compressor tables data")),
(("X393_CMPRS_TABLES_ADDRESS", c, vrlg.CMPRS_TABLES + 1 + ba, ia, z3, "x393_cmprs_table_addr", "wo", "Compressor tables type/address")),
]
ba = vrlg.STATUS_ADDR
ia = vrlg.CMPRS_STATUS_REG_INC
c = "chn"
sdefines +=[
(('Compressor channel status)',)),
(("X393_CMPRS_STATUS", c, vrlg.CMPRS_STATUS_REG_BASE + ba, vrlg.CMPRS_STATUS_REG_INC, z3, "x393_cmprs_status", "ro", "Status of the compressor channel (incl. interrupt")),
(("X393_CMPRS_HIFREQ", c, vrlg.CMPRS_HIFREQ_REG_BASE + ba, vrlg.CMPRS_HIFREQ_REG_INC, z3, "u32*", "ro", "Focus helper high-frequency amount"))]
ba = vrlg.CMPRS_GROUP_ADDR + vrlg.CMPRS_AFIMUX_RADDR0
ia = 0
c = "afi_port"
......@@ -1019,7 +1031,7 @@ class X393ExportC(object):
ia = 0
c = ""
sdefines +=[
(('_Command sequencer multiplexer, provides current frame number for each sesnor channel and interrupt status/interrupt masks for them.',)),
(('_Command sequencer multiplexer, provides current frame number for each sensor channel and interrupt status/interrupt masks for them.',)),
(('_Interrupts and interrupt masks are controlled through channel CMDFRAMESEQ module',)),
(("X393_CMDSEQMUX_STATUS_CTRL", "", vrlg.CMDSEQMUX_ADDR, 0, None, "x393_status_ctrl", "rw", "CMDSEQMUX status control mode (status provides current frame numbers)")),
(("X393_CMDSEQMUX_STATUS", "", vrlg.STATUS_ADDR + vrlg.CMDSEQMUX_STATUS, 0, None, "x393_cmdseqmux_status", "ro", "CMDSEQMUX status data (frame numbers and interrupts"))]
......@@ -1833,7 +1845,7 @@ class X393ExportC(object):
dw.append(("arst_set", vrlg.SENS_CTRL_ARST + 1, 1, 0, "ARST set to the 'arst' field"))
dw.append(("aro", vrlg.SENS_CTRL_ARO, 1, 0, "ARO signal to the sensor"))
dw.append(("aro_set", vrlg.SENS_CTRL_ARO + 1, 1, 0, "ARO set to the 'aro' field"))
dw.append(("mmcm_rst", vrlg.SENS_CTRL_RST_MMCM, 1, 0, "MMCM (for sesnor clock) reset signal"))
dw.append(("mmcm_rst", vrlg.SENS_CTRL_RST_MMCM, 1, 0, "MMCM (for sensor clock) reset signal"))
dw.append(("mmcm_rst_set", vrlg.SENS_CTRL_RST_MMCM + 1, 1, 0, "MMCM reset set to 'mmcm_rst' field"))
dw.append(("ext_clk", vrlg.SENS_CTRL_EXT_CLK, 1, 0, "MMCM clock input: 0: clock to the sensor, 1 - clock from the sensor"))
dw.append(("ext_clk_set", vrlg.SENS_CTRL_EXT_CLK + 1, 1, 0, "Set MMCM clock input to 'ext_clk' field"))
......@@ -1849,7 +1861,7 @@ class X393ExportC(object):
dw.append(("arst_set", vrlg.SENS_CTRL_ARST + 1, 1, 0, "ARST set to the 'arst' field"))
dw.append(("aro", vrlg.SENS_CTRL_ARO, 1, 0, "ARO signal to the sensor"))
dw.append(("aro_set", vrlg.SENS_CTRL_ARO + 1, 1, 0, "ARO set to the 'aro' field"))
dw.append(("mmcm_rst", vrlg.SENS_CTRL_RST_MMCM, 1, 0, "MMCM (for sesnor clock) reset signal"))
dw.append(("mmcm_rst", vrlg.SENS_CTRL_RST_MMCM, 1, 0, "MMCM (for sensor clock) reset signal"))
dw.append(("mmcm_rst_set", vrlg.SENS_CTRL_RST_MMCM + 1, 1, 0, "MMCM reset set to 'mmcm_rst' field"))
dw.append(("ign_embed", vrlg.SENS_CTRL_IGNORE_EMBED, 1, 0, "Ignore embedded data (non-image pixel lines"))
dw.append(("ign_embed_set",vrlg.SENS_CTRL_IGNORE_EMBED + 1,1,0, "Set mode to 'ign_embed' field"))
......@@ -2092,6 +2104,16 @@ class X393ExportC(object):
dw.append(("type", 24, 2, 0, "0: quantization, 1: coring, 2: focus, 3: huffman"))
return dw
def _enc_cmprs_status(self):
dw=[]
dw.append(("is", 0, 1, 0, "Compressor channel interrupt status"))
dw.append(("im", 1, 1, 0, "Compressor channel interrupt mask"))
dw.append(("reading_frame", 2, 1, 0, "Compressor channel is reading frame from memory (debug feature)"))
dw.append(("stuffer_running", 3, 1, 0, "Compressor channel bit stuffer is running (debug feature)"))
dw.append(("flushing_fifo", 4, 1, 0, "Compressor channel is flushing FIFO (debug feature)"))
dw.append(("seq_num", 26, 6, 0, "Status sequence number"))
return dw
def _enc_cmprs_afimux_sa(self):
dw=[]
dw.append(("sa256", 0, 27, 0, "System memory buffer start in multiples of 32 bytes (256 bits)"))
......@@ -2210,7 +2232,7 @@ class X393ExportC(object):
dw.append(("en_snd_set", vrlg.CAMSYNC_SNDEN_BIT, 1, 0, "Set 'en_snd'"))
dw.append(("ext", vrlg.CAMSYNC_EXTERNAL_BIT - 1, 1, 1, "Use external (received) timestamps, if available. O - use local timestamps"))
dw.append(("ext_set", vrlg.CAMSYNC_EXTERNAL_BIT, 1, 0, "Set 'ext'"))
dw.append(("trig", vrlg.CAMSYNC_TRIGGERED_BIT - 1, 1, 1, "Sensor triggered mode (0 - free running sesnor)"))
dw.append(("trig", vrlg.CAMSYNC_TRIGGERED_BIT - 1, 1, 1, "Sensor triggered mode (0 - free running sensor)"))
dw.append(("trig_set", vrlg.CAMSYNC_TRIGGERED_BIT, 1, 0, "Set 'trig'"))
dw.append(("master_chn", vrlg.CAMSYNC_MASTER_BIT - 2, 2, 0, "master sensor channel (zero delay in internal trigger mode, delay used for flash output)"))
dw.append(("master_chn_set", vrlg.CAMSYNC_MASTER_BIT, 1, 0, "Set 'master_chn'"))
......
py393/x393_sensor.py
View file @ effa97e5
......@@ -500,8 +500,8 @@ class X393Sensor(object):
"""
Write i2c register in immediate mode
@param num_sensor - sensor port number (0..3), or "all" - same to all sensors
@param reg_addr16 - 16-bit register address (page+low byte, for MT9F006 high byte is an 8-bit slave address = 0x90)
@param reg_data16 - 16-bit data to write to sesnor register
@param reg_addr16 - 16-bit register address (page+low byte, for MT9P006 high byte is an 8-bit slave address = 0x90)
@param reg_data16 - 16-bit data to write to sensor register
"""
self.write_sensor_i2c (num_sensor = num_sensor,
rel_addr = True,
......
x393_testbench02.tf
View file @ effa97e5
......@@ -2562,7 +2562,7 @@ task setup_sensor_channel;
TEST_TITLE = "GAMMA_CTL";
$display("===================== TEST_%s =========================",TEST_TITLE);
set_sensor_gamma_ctl (// doing last to enable sesnor data when everything else is set up
set_sensor_gamma_ctl (// doing last to enable sensor data when everything else is set up
num_sensor, // input [1:0] num_sensor; // sensor channel number (0..3)
2'h0, // 2'h3, // input [1:0] bayer; // bayer shift (0..3)
0, // input table_page; // table page (only used if SENS_GAMMA_BUFFER)
......@@ -3649,7 +3649,7 @@ task set_camsync_mode;
input en; // 1 - enable, 0 - reset module
input [1:0] en_snd; // <2 - NOP, 2 - disable, 3 - enable sending timestamp with sync pulse
input [1:0] en_ts_external; // <2 - NOP, 2 - local timestamp in the frame header, 3 - use external timestamp
input [1:0] triggered_mode; // <2 - NOP, 2 - async sesnor mode, 3 - triggered sensor mode
input [1:0] triggered_mode; // <2 - NOP, 2 - async sensor mode, 3 - triggered sensor mode
input [2:0] master_chn; // <4 - NOP, 4..7 - set master channel
input [4:0] chn_en; // <16 - NOP, [3:0] - bit mask of enabled sensor channels
reg [31:0] data;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment