modifying memory controller buffer interface (ecd4a509) · Commits · Elphel / x393

memctrl/cmd_encod_linear_rd.v

+13 −6

Original line number	Original line	Diff line number	Diff line
	@@ -51,9 +51,10 @@ module cmd_encod_linear_rd #(
	output reg enc_wr, // write encoded command		output reg enc_wr, // write encoded command
	output reg enc_done // encoding finished		output reg enc_done // encoding finished
	);		);
	localparam ROM_WIDTH=9;		localparam ROM_WIDTH=10;
	localparam ROM_DEPTH=4;		localparam ROM_DEPTH=4;

			// localparam ENC_BUF_PGNEXT= 0;
	localparam ENC_NOP= 0;		localparam ENC_NOP= 0;
	localparam ENC_BUF_WR= 1;		localparam ENC_BUF_WR= 1;
	localparam ENC_DCI= 2;		localparam ENC_DCI= 2;
	@@ -61,6 +62,7 @@ module cmd_encod_linear_rd #(
	localparam ENC_CMD_SHIFT= 4; // [5:4] - command: 0 -= NOP, 1 - READ, 2 - PRECHARGE, 3 - ACTIVATE		localparam ENC_CMD_SHIFT= 4; // [5:4] - command: 0 -= NOP, 1 - READ, 2 - PRECHARGE, 3 - ACTIVATE
	localparam ENC_PAUSE_SHIFT=6; // [7:6] - 2- bit pause (for NOP commandes)		localparam ENC_PAUSE_SHIFT=6; // [7:6] - 2- bit pause (for NOP commandes)
	localparam ENC_PRE_DONE= 8;		localparam ENC_PRE_DONE= 8;
			localparam ENC_BUF_PGNEXT= 9;

	localparam ENC_CMD_NOP= 0; // 2-bit locally encoded commands		localparam ENC_CMD_NOP= 0; // 2-bit locally encoded commands
	localparam ENC_CMD_READ= 1;		localparam ENC_CMD_READ= 1;
	@@ -128,7 +130,7 @@ module cmd_encod_linear_rd #(
	4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) \| (1 << ENC_NOP) \| (1 << ENC_DCI) \| (1 << ENC_SEL);		4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) \| (1 << ENC_NOP) \| (1 << ENC_DCI) \| (1 << ENC_SEL);
	4'h3: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) \| (1 << ENC_NOP) \| (1 << ENC_BUF_WR) \| (1 << ENC_DCI) \| (1 << ENC_SEL);		4'h3: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) \| (1 << ENC_NOP) \| (1 << ENC_BUF_WR) \| (1 << ENC_DCI) \| (1 << ENC_SEL);
	4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_PAUSE_SHIFT) \| (1 << ENC_BUF_WR) \| (1 << ENC_DCI) \| (1 << ENC_SEL);		4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_PAUSE_SHIFT) \| (1 << ENC_BUF_WR) \| (1 << ENC_DCI) \| (1 << ENC_SEL);
	4'h5: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_DCI) \| (1 << ENC_SEL);		4'h5: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_BUF_PGNEXT) \| (1 << ENC_DCI) \| (1 << ENC_SEL);
	4'h6: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT) \| (1 << ENC_DCI);		4'h6: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT) \| (1 << ENC_DCI);
	4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (2 << ENC_PAUSE_SHIFT) \| (1 << ENC_DCI);		4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (2 << ENC_PAUSE_SHIFT) \| (1 << ENC_DCI);
	4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_PRE_DONE);		4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_PRE_DONE);
	@@ -158,7 +160,8 @@ module cmd_encod_linear_rd #(
	1'b0, // dqs_toggle; // enable toggle DQS according to the pattern		1'b0, // dqs_toggle; // enable toggle DQS according to the pattern
	rom_r[ENC_DCI], // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)		rom_r[ENC_DCI], // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
	rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)		rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)
	1'b0); // buf_rd; // connect to external buffer (but only if not paused)		1'b0, // buf_rd; // connect to external buffer (but only if not paused)
			rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
	else enc_cmd <= func_encode_cmd ( // encode non-NOP command		else enc_cmd <= func_encode_cmd ( // encode non-NOP command
	rom_cmd[1]?		rom_cmd[1]?
	row:		row:
	@@ -174,7 +177,8 @@ module cmd_encod_linear_rd #(
	rom_r[ENC_DCI], // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)		rom_r[ENC_DCI], // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
	rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)		rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)
	1'b0, // buf_rd; // connect to external buffer (but only if not paused)		1'b0, // buf_rd; // connect to external buffer (but only if not paused)
	rom_r[ENC_NOP]); // nop; // add NOP after the current command, keep other data		rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
			rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
	end		end


	@@ -193,6 +197,7 @@ module cmd_encod_linear_rd #(
	input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)		input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
	input buf_wr; // connect to external buffer (but only if not paused)		input buf_wr; // connect to external buffer (but only if not paused)
	input buf_rd; // connect to external buffer (but only if not paused)		input buf_rd; // connect to external buffer (but only if not paused)
			input buf_rst; // connect to external buffer (but only if not paused)
	begin		begin
	func_encode_skip= func_encode_cmd (		func_encode_skip= func_encode_cmd (
	{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column adderss		{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column adderss
	@@ -207,7 +212,8 @@ module cmd_encod_linear_rd #(
	dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)		dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
	buf_wr, // connect to external buffer (but only if not paused)		buf_wr, // connect to external buffer (but only if not paused)
	buf_rd, // connect to external buffer (but only if not paused)		buf_rd, // connect to external buffer (but only if not paused)
	1'b0);		1'b0, // nop
			buf_rst);
	end		end
	endfunction		endfunction

	@@ -225,6 +231,7 @@ module cmd_encod_linear_rd #(
	input buf_wr; // connect to external buffer (but only if not paused)		input buf_wr; // connect to external buffer (but only if not paused)
	input buf_rd; // connect to external buffer (but only if not paused)		input buf_rd; // connect to external buffer (but only if not paused)
	input nop; // add NOP after the current command, keep other data		input nop; // add NOP after the current command, keep other data
			input buf_rst; // connect to external buffer (but only if not paused)
	begin		begin
	func_encode_cmd={		func_encode_cmd={
	addr[14:0], // 15-bit row/column adderss		addr[14:0], // 15-bit row/column adderss
	@@ -240,7 +247,7 @@ module cmd_encod_linear_rd #(
	buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)		buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)
	buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)		buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)
	nop, // add NOP after the current command, keep other data		nop, // add NOP after the current command, keep other data
	1'b0 // Reserved for future use		buf_rst // Reserved for future use
	};		};
	end		end
	endfunction		endfunction

memctrl/cmd_encod_linear_wr.v

+13 −7

Original line number	Original line	Diff line number	Diff line
	@@ -42,7 +42,7 @@ module cmd_encod_linear_wr #(
	output reg enc_wr, // write encoded command		output reg enc_wr, // write encoded command
	output reg enc_done // encoding finished		output reg enc_done // encoding finished
	);		);
	localparam ROM_WIDTH=11;		localparam ROM_WIDTH=12;
	localparam ROM_DEPTH=4;		localparam ROM_DEPTH=4;

	localparam ENC_NOP= 0;		localparam ENC_NOP= 0;
	@@ -54,6 +54,7 @@ module cmd_encod_linear_wr #(
	localparam ENC_CMD_SHIFT= 6; // [7:6] - command: 0 -= NOP, 1 - WRITE, 2 - PRECHARGE, 3 - ACTIVATE		localparam ENC_CMD_SHIFT= 6; // [7:6] - command: 0 -= NOP, 1 - WRITE, 2 - PRECHARGE, 3 - ACTIVATE
	localparam ENC_PAUSE_SHIFT=8; // [9:8] - 2- bit pause (for NOP commandes)		localparam ENC_PAUSE_SHIFT=8; // [9:8] - 2- bit pause (for NOP commandes)
	localparam ENC_PRE_DONE= 10;		localparam ENC_PRE_DONE= 10;
			localparam ENC_BUF_PGNEXT= 11;

	localparam ENC_CMD_NOP= 0; // 2-bit locally encoded commands		localparam ENC_CMD_NOP= 0; // 2-bit locally encoded commands
	localparam ENC_CMD_WRITE= 1;		localparam ENC_CMD_WRITE= 1;
	@@ -114,6 +115,7 @@ module cmd_encod_linear_wr #(
	end		end

	// ROM-based (registered output) encoded sequence		// ROM-based (registered output) encoded sequence
			// TODO: Remove last ENC_BUF_RD
	always @ (posedge rst or posedge clk) begin		always @ (posedge rst or posedge clk) begin
	if (rst) rom_r <= 0;		if (rst) rom_r <= 0;
	else case (gen_addr)		else case (gen_addr)
	@@ -124,7 +126,7 @@ module cmd_encod_linear_wr #(
	4'h4: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) \| (1 << ENC_NOP) \| (1 << ENC_BUF_RD) \| (1 << ENC_DQS_TOGGLE) \| (1 << ENC_DQ_DQS_EN) \| (1 << ENC_ODT); // will repeet		4'h4: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) \| (1 << ENC_NOP) \| (1 << ENC_BUF_RD) \| (1 << ENC_DQS_TOGGLE) \| (1 << ENC_DQ_DQS_EN) \| (1 << ENC_ODT); // will repeet
	4'h5: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (2 << ENC_PAUSE_SHIFT) \| (1 << ENC_DQS_TOGGLE) \| (1 << ENC_DQ_DQS_EN) \| (1 << ENC_ODT);		4'h5: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (2 << ENC_PAUSE_SHIFT) \| (1 << ENC_DQS_TOGGLE) \| (1 << ENC_DQ_DQS_EN) \| (1 << ENC_ODT);
	4'h6: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (2 << ENC_PAUSE_SHIFT);		4'h6: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (2 << ENC_PAUSE_SHIFT);
	4'h7: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT);		4'h7: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT) \| (1 << ENC_BUF_PGNEXT);
	4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (2 << ENC_PAUSE_SHIFT);		4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (2 << ENC_PAUSE_SHIFT);
	4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_PRE_DONE);		4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_PRE_DONE);
	default:rom_r <= 0;		default:rom_r <= 0;
	@@ -153,7 +155,8 @@ module cmd_encod_linear_wr #(
	rom_r[ENC_DQS_TOGGLE], // dqs_toggle; // enable toggle DQS according to the pattern		rom_r[ENC_DQS_TOGGLE], // dqs_toggle; // enable toggle DQS according to the pattern
	1'b0, // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)		1'b0, // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
	1'b0, // buf_wr; // connect to external buffer (but only if not paused)		1'b0, // buf_wr; // connect to external buffer (but only if not paused)
	rom_r[ENC_BUF_RD]); // buf_rd; // connect to external buffer (but only if not paused)		rom_r[ENC_BUF_RD], // buf_rd; // connect to external buffer (but only if not paused)
			rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
	else enc_cmd <= func_encode_cmd ( // encode non-NOP command		else enc_cmd <= func_encode_cmd ( // encode non-NOP command
	rom_cmd[1]?		rom_cmd[1]?
	row:		row:
	@@ -169,8 +172,8 @@ module cmd_encod_linear_wr #(
	1'b0, // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)		1'b0, // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
	1'b0, // buf_wr; // connect to external buffer (but only if not paused)		1'b0, // buf_wr; // connect to external buffer (but only if not paused)
	rom_r[ENC_BUF_RD], // buf_rd; // connect to external buffer (but only if not paused)		rom_r[ENC_BUF_RD], // buf_rd; // connect to external buffer (but only if not paused)
	rom_r[ENC_NOP]); // nop; // add NOP after the current command, keep other data		rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
			rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
	end		end


	@@ -189,6 +192,7 @@ module cmd_encod_linear_wr #(
	input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)		input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
	input buf_wr; // connect to external buffer (but only if not paused)		input buf_wr; // connect to external buffer (but only if not paused)
	input buf_rd; // connect to external buffer (but only if not paused)		input buf_rd; // connect to external buffer (but only if not paused)
			input buf_rst; // connect to external buffer (but only if not paused)
	begin		begin
	func_encode_skip= func_encode_cmd (		func_encode_skip= func_encode_cmd (
	{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column adderss		{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column adderss
	@@ -203,7 +207,8 @@ module cmd_encod_linear_wr #(
	dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)		dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
	buf_wr, // connect to external buffer (but only if not paused)		buf_wr, // connect to external buffer (but only if not paused)
	buf_rd, // connect to external buffer (but only if not paused)		buf_rd, // connect to external buffer (but only if not paused)
	1'b0);		1'b0, // nop
			buf_rst);
	end		end
	endfunction		endfunction

	@@ -221,6 +226,7 @@ module cmd_encod_linear_wr #(
	input buf_wr; // connect to external buffer (but only if not paused)		input buf_wr; // connect to external buffer (but only if not paused)
	input buf_rd; // connect to external buffer (but only if not paused)		input buf_rd; // connect to external buffer (but only if not paused)
	input nop; // add NOP after the current command, keep other data		input nop; // add NOP after the current command, keep other data
			input buf_rst; // connect to external buffer (but only if not paused)
	begin		begin
	func_encode_cmd={		func_encode_cmd={
	addr[14:0], // 15-bit row/column adderss		addr[14:0], // 15-bit row/column adderss
	@@ -236,7 +242,7 @@ module cmd_encod_linear_wr #(
	buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)		buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)
	buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)		buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)
	nop, // add NOP after the current command, keep other data		nop, // add NOP after the current command, keep other data
	1'b0 // Reserved for future use		buf_rst // Reserved for future use
	};		};
	end		end
	endfunction		endfunction

memctrl/cmd_encod_tiled_rd.v

+17 −10

Original line number	Original line	Diff line number	Diff line
	@@ -48,13 +48,14 @@ module cmd_encod_tiled_rd #(
	input [5:0] num_rows_in_m1, // number of rows to read minus 1		input [5:0] num_rows_in_m1, // number of rows to read minus 1
	input [5:0] num_cols_in_m1, // number of 16-pixel columns to read (rows first, then columns) - 1		input [5:0] num_cols_in_m1, // number of 16-pixel columns to read (rows first, then columns) - 1
	input keep_open_in, // keep banks open (for <=8 banks only		input keep_open_in, // keep banks open (for <=8 banks only
			input skip_next_page_in, // do not reset external buffer (continue)
	input start, // start generating commands		input start, // start generating commands
	output reg [31:0] enc_cmd, // encoded commnad		output reg [31:0] enc_cmd, // encoded commnad
	output reg enc_wr, // write encoded command		output reg enc_wr, // write encoded command
	output reg enc_done // encoding finished		output reg enc_done // encoding finished
	);		);
	localparam FULL_ADDR_NUMBER=ADDRESS_NUMBER+COLADDR_NUMBER; // excluding 3 CA lsb, but adding 3 bank		localparam FULL_ADDR_NUMBER=ADDRESS_NUMBER+COLADDR_NUMBER; // excluding 3 CA lsb, but adding 3 bank
	localparam ROM_WIDTH=9;		localparam ROM_WIDTH=10;
	localparam ROM_DEPTH=4;		localparam ROM_DEPTH=4;

	localparam ENC_NOP= 0;		localparam ENC_NOP= 0;
	@@ -64,6 +65,7 @@ module cmd_encod_tiled_rd #(
	localparam ENC_CMD_SHIFT= 4; // [5:4] - command: 0 -= NOP, 1 - READ, 2 - PRECHARGE, 3 - ACTIVATE		localparam ENC_CMD_SHIFT= 4; // [5:4] - command: 0 -= NOP, 1 - READ, 2 - PRECHARGE, 3 - ACTIVATE
	localparam ENC_PAUSE_SHIFT=6; // [7:6] - 2- bit pause (for NOP commandes)		localparam ENC_PAUSE_SHIFT=6; // [7:6] - 2- bit pause (for NOP commandes)
	localparam ENC_PRE_DONE= 8;		localparam ENC_PRE_DONE= 8;
			localparam ENC_BUF_PGNEXT= 9;

	localparam ENC_CMD_NOP= 0; // 2-bit locally encoded commands		localparam ENC_CMD_NOP= 0; // 2-bit locally encoded commands
	localparam ENC_CMD_READ= 1;		localparam ENC_CMD_READ= 1;
	@@ -86,7 +88,7 @@ module cmd_encod_tiled_rd #(
	reg [FULL_ADDR_NUMBER-4:0] rowcol_inc; // increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts)		reg [FULL_ADDR_NUMBER-4:0] rowcol_inc; // increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts)

	reg keep_open;		reg keep_open;
			reg skip_next_page;
	reg gen_run;		reg gen_run;
	reg gen_run_d;		reg gen_run_d;
	reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM		reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
	@@ -219,6 +221,7 @@ module cmd_encod_tiled_rd #(
	bank <= start_bank;		bank <= start_bank;
	rowcol_inc <= rowcol_inc_in;		rowcol_inc <= rowcol_inc_in;
	keep_open <= keep_open_in && (\|num_cols_in_m1[5:3]!=0);		keep_open <= keep_open_in && (\|num_cols_in_m1[5:3]!=0);
			skip_next_page <= skip_next_page_in;
	end		end

	// ROM-based (registered output) encoded sequence		// ROM-based (registered output) encoded sequence
	@@ -235,7 +238,7 @@ module cmd_encod_tiled_rd #(
	4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_BUF_WR) \| (1 << ENC_DCI) \| (1 << ENC_SEL);		4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_BUF_WR) \| (1 << ENC_DCI) \| (1 << ENC_SEL);
	4'h8: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) \| (1 << ENC_BUF_WR) \| (1 << ENC_DCI) \| (1 << ENC_SEL);		4'h8: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) \| (1 << ENC_BUF_WR) \| (1 << ENC_DCI) \| (1 << ENC_SEL);
	4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (2 << ENC_PAUSE_SHIFT) \| (1 << ENC_BUF_WR) \| (1 << ENC_DCI) \| (1 << ENC_SEL);		4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (2 << ENC_PAUSE_SHIFT) \| (1 << ENC_BUF_WR) \| (1 << ENC_DCI) \| (1 << ENC_SEL);
	4'h10: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_DCI) \| (1 << ENC_SEL);		4'h10: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_DCI) \| (1 << ENC_SEL) \| (skip_next_page? 1'b0:(1 << ENC_BUF_PGNEXT));
	4'h11: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (3 << ENC_PAUSE_SHIFT) \| (1 << ENC_DCI);		4'h11: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (3 << ENC_PAUSE_SHIFT) \| (1 << ENC_DCI);
	4'h12: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_PRE_DONE);		4'h12: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) \| (1 << ENC_PRE_DONE);
	default:rom_r <= 0;		default:rom_r <= 0;
	@@ -264,7 +267,8 @@ module cmd_encod_tiled_rd #(
	1'b0, // dqs_toggle; // enable toggle DQS according to the pattern		1'b0, // dqs_toggle; // enable toggle DQS according to the pattern
	rom_r[ENC_DCI], // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)		rom_r[ENC_DCI], // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
	rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)		rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)
	1'b0); // buf_rd; // connect to external buffer (but only if not paused)		1'b0, // buf_rd; // connect to external buffer (but only if not paused)
			rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
	else enc_cmd <= func_encode_cmd ( // encode non-NOP command		else enc_cmd <= func_encode_cmd ( // encode non-NOP command
	rom_cmd[1]? // activate		rom_cmd[1]? // activate
	row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act		row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
	@@ -285,10 +289,10 @@ module cmd_encod_tiled_rd #(
	rom_r[ENC_DCI], // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)		rom_r[ENC_DCI], // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
	rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)		rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)
	1'b0, // buf_rd; // connect to external buffer (but only if not paused)		1'b0, // buf_rd; // connect to external buffer (but only if not paused)
	rom_r[ENC_NOP]); // nop; // add NOP after the current command, keep other data		rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
			rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
	end		end


	// move to include?		// move to include?

	function [31:0] func_encode_skip;		function [31:0] func_encode_skip;
	@@ -304,6 +308,7 @@ module cmd_encod_tiled_rd #(
	input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)		input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
	input buf_wr; // connect to external buffer (but only if not paused)		input buf_wr; // connect to external buffer (but only if not paused)
	input buf_rd; // connect to external buffer (but only if not paused)		input buf_rd; // connect to external buffer (but only if not paused)
			input buf_rst; // connect to external buffer (but only if not paused)
	begin		begin
	func_encode_skip= func_encode_cmd (		func_encode_skip= func_encode_cmd (
	{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column adderss		{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column adderss
	@@ -318,7 +323,8 @@ module cmd_encod_tiled_rd #(
	dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)		dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
	buf_wr, // connect to external buffer (but only if not paused)		buf_wr, // connect to external buffer (but only if not paused)
	buf_rd, // connect to external buffer (but only if not paused)		buf_rd, // connect to external buffer (but only if not paused)
	1'b0);		1'b0, // nop
			buf_rst);
	end		end
	endfunction		endfunction

	@@ -336,6 +342,7 @@ module cmd_encod_tiled_rd #(
	input buf_wr; // connect to external buffer (but only if not paused)		input buf_wr; // connect to external buffer (but only if not paused)
	input buf_rd; // connect to external buffer (but only if not paused)		input buf_rd; // connect to external buffer (but only if not paused)
	input nop; // add NOP after the current command, keep other data		input nop; // add NOP after the current command, keep other data
			input buf_rst; // connect to external buffer (but only if not paused)
	begin		begin
	func_encode_cmd={		func_encode_cmd={
	addr[14:0], // 15-bit row/column adderss		addr[14:0], // 15-bit row/column adderss
	@@ -351,7 +358,7 @@ module cmd_encod_tiled_rd #(
	buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)		buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)
	buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)		buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)
	nop, // add NOP after the current command, keep other data		nop, // add NOP after the current command, keep other data
	1'b0 // Reserved for future use		buf_rst // Reserved for future use
	};		};
	end		end
	endfunction		endfunction

memctrl/mcntrl393.v

+50 −74

File changed.

Preview size limit exceeded, changes collapsed.

memctrl/mcntrl_1kx32r.v

+13 −10

Original line number	Original line	Diff line number	Diff line
	@@ -29,19 +29,22 @@ module mcntrl_1kx32r(
	output [31:0] ext_data_out, // data out		output [31:0] ext_data_out, // data out

	input wclk, // !mclk (inverted)		input wclk, // !mclk (inverted)
	input [1:0] wpage, // will register to wclk, input OK with mclk		input [1:0] wpage_in, // will register to wclk, input OK with mclk
	input waddr_reset, // reset write buffer address (to page start), sync to wclk (!mclk)		input wpage_set, // set internal read page to rpage_in
	input skip_reset, // ignore waddr_reset (resync to wclk)		input page_next, // advance to next page (and reset lower bits to 0)
			output [1:0] page, // current inernal page
	input we, // write port enable (also increment write buffer address)		input we, // write port enable (also increment write buffer address)
	input [63:0] data_in // data in		input [63:0] data_in // data in
	);		);
	reg [1:0] wpage_wclk;		reg [1:0] page_r;
	reg skip_reset_wclk;
	reg [6:0] waddr;		reg [6:0] waddr;
			assign page=page_r;
	always @ (posedge wclk) begin		always @ (posedge wclk) begin
	wpage_wclk <= wpage;
	skip_reset_wclk <= skip_reset;		if (wpage_set) page_r <= wpage_in;
	if (waddr_reset && !skip_reset_wclk) waddr <= 0;		else if (page_next) page_r <= page_r+1;

			if (page_next) waddr <= 0;
	else if (we) waddr <= waddr+1;		else if (we) waddr <= waddr+1;
	end		end
	ram_512x64w_1kx32r #(		ram_512x64w_1kx32r #(
	@@ -53,7 +56,7 @@ module mcntrl_1kx32r(
	.regen (ext_regen), // input		.regen (ext_regen), // input
	.data_out (ext_data_out), // output[31:0]		.data_out (ext_data_out), // output[31:0]
	.wclk (wclk), // input - OK, negedge mclk		.wclk (wclk), // input - OK, negedge mclk
	.waddr ({wpage_wclk,waddr}), // input[8:0] @negedge mclk		.waddr ({page,waddr}), // input[8:0] @negedge mclk
	.we (we), // input @negedge mclk		.we (we), // input @negedge mclk
	.web (8'hff), // input[7:0]		.web (8'hff), // input[7:0]
	.data_in (data_in) // input[63:0] @negedge mclk		.data_in (data_in) // input[63:0] @negedge mclk

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