modifying memory controller buffer interface

memctrl/cmd_encod_linear_rd.v

@@ -51,9 +51,10 @@ module  cmd_encod_linear_rd #(
     output reg                   enc_wr,      // write encoded command
     output reg                   enc_done     // encoding finished
 );
-    localparam ROM_WIDTH=9;
+    localparam ROM_WIDTH=10;
     localparam ROM_DEPTH=4;
     
+//    localparam ENC_BUF_PGNEXT=    0;
     localparam ENC_NOP=        0;
     localparam ENC_BUF_WR=     1;
     localparam ENC_DCI=        2;
@@ -61,6 +62,7 @@ module  cmd_encod_linear_rd #(
     localparam ENC_CMD_SHIFT=  4; // [5:4] - command: 0 -= NOP, 1 - READ, 2 - PRECHARGE, 3 - ACTIVATE
     localparam ENC_PAUSE_SHIFT=6; // [7:6] - 2- bit pause (for NOP commandes)
     localparam ENC_PRE_DONE=   8;
+    localparam ENC_BUF_PGNEXT=    9;
     
     localparam ENC_CMD_NOP=      0; // 2-bit locally encoded commands
     localparam ENC_CMD_READ=     1;
@@ -128,7 +130,7 @@ module  cmd_encod_linear_rd #(
             4'h2: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT) | (1 << ENC_NOP)                             | (1 << ENC_DCI) | (1 << ENC_SEL); 
             4'h3: rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT) | (1 << ENC_NOP)         | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
             4'h4: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
-            4'h5: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT)                                              | (1 << ENC_DCI) | (1 << ENC_SEL);
+            4'h5: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT)                      | (1 << ENC_DCI) | (1 << ENC_SEL);
             4'h6: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT)                                              | (1 << ENC_DCI);
             4'h7: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT)                     | (1 << ENC_DCI);
             4'h8: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
@@ -158,7 +160,8 @@ module  cmd_encod_linear_rd #(
             1'b0,                    //   dqs_toggle; // enable toggle DQS according to the pattern
             rom_r[ENC_DCI],          //   dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
             rom_r[ENC_BUF_WR],       //   buf_wr;     // connect to external buffer (but only if not paused)
-            1'b0);                   //   buf_rd;     // connect to external buffer (but only if not paused)
+            1'b0,                    //   buf_rd;     // connect to external buffer (but only if not paused)
+            rom_r[ENC_BUF_PGNEXT]);     //   buf_rst;    // connect to external buffer (but only if not paused)
        else  enc_cmd <= func_encode_cmd ( // encode non-NOP command
             rom_cmd[1]?
                     row:
@@ -174,7 +177,8 @@ module  cmd_encod_linear_rd #(
             rom_r[ENC_DCI],          //   dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
             rom_r[ENC_BUF_WR],       //   buf_wr;     // connect to external buffer (but only if not paused)
             1'b0,                    //   buf_rd;     // connect to external buffer (but only if not paused)     
-            rom_r[ENC_NOP]);         //   nop;        // add NOP after the current command, keep other data
+            rom_r[ENC_NOP],          //   nop;        // add NOP after the current command, keep other data
+            rom_r[ENC_BUF_PGNEXT]);  //   buf_rst;    // connect to external buffer (but only if not paused)
     end    
     
 
@@ -193,6 +197,7 @@ module  cmd_encod_linear_rd #(
         input                      dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
         input                      buf_wr;     // connect to external buffer (but only if not paused)
         input                      buf_rd;     // connect to external buffer (but only if not paused)
+        input                      buf_rst;    // connect to external buffer (but only if not paused)
         begin
             func_encode_skip= func_encode_cmd (
                 {{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]},       // 15-bit row/column adderss
@@ -207,7 +212,8 @@ module  cmd_encod_linear_rd #(
                 dci,        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
                 buf_wr,     // connect to external buffer (but only if not paused)
                 buf_rd,     // connect to external buffer (but only if not paused)
-                1'b0);
+                1'b0,       // nop
+                buf_rst);
         end
     endfunction
 
@@ -225,6 +231,7 @@ module  cmd_encod_linear_rd #(
         input                      buf_wr;     // connect to external buffer (but only if not paused)
         input                      buf_rd;     // connect to external buffer (but only if not paused)
         input                      nop;        // add NOP after the current command, keep other data
+        input                      buf_rst;    // connect to external buffer (but only if not paused)
         begin
             func_encode_cmd={
             addr[14:0], // 15-bit row/column adderss
@@ -240,7 +247,7 @@ module  cmd_encod_linear_rd #(
             buf_wr,     // phy_buf_wr,   // connect to external buffer (but only if not paused)
             buf_rd,     // phy_buf_rd,    // connect to external buffer (but only if not paused)
             nop,        // add NOP after the current command, keep other data
-            1'b0        // Reserved for future use
+            buf_rst     // Reserved for future use
            };
         end
     endfunction

memctrl/cmd_encod_linear_wr.v

@@ -42,7 +42,7 @@ module  cmd_encod_linear_wr #(
     output reg                   enc_wr,      // write encoded command
     output reg                   enc_done     // encoding finished
 );
-    localparam ROM_WIDTH=11;
+    localparam ROM_WIDTH=12;
     localparam ROM_DEPTH=4;
     
     localparam ENC_NOP=        0;
@@ -54,6 +54,7 @@ module  cmd_encod_linear_wr #(
     localparam ENC_CMD_SHIFT=  6; // [7:6] - command: 0 -= NOP, 1 - WRITE, 2 - PRECHARGE, 3 - ACTIVATE
     localparam ENC_PAUSE_SHIFT=8; // [9:8] - 2- bit pause (for NOP commandes)
     localparam ENC_PRE_DONE=  10;
+    localparam ENC_BUF_PGNEXT=   11;
     
     localparam ENC_CMD_NOP=      0; // 2-bit locally encoded commands
     localparam ENC_CMD_WRITE=    1;
@@ -114,6 +115,7 @@ module  cmd_encod_linear_wr #(
     end
     
     // ROM-based (registered output) encoded sequence
+    // TODO: Remove last ENC_BUF_RD
     always @ (posedge rst or posedge clk) begin
         if (rst)           rom_r <= 0;
         else case (gen_addr)
@@ -124,7 +126,7 @@ module  cmd_encod_linear_wr #(
             4'h4: rom_r <= (ENC_CMD_WRITE <<     ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_RD) | (1 << ENC_DQS_TOGGLE)  | (1 << ENC_DQ_DQS_EN)  | (1 << ENC_ODT); // will repeet 
             4'h5: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT);
             4'h6: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT);
-            4'h7: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT);
+            4'h7: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT) |      (1 << ENC_BUF_PGNEXT);
             4'h8: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT);
             4'h9: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
             default:rom_r <= 0;
@@ -153,7 +155,8 @@ module  cmd_encod_linear_wr #(
             rom_r[ENC_DQS_TOGGLE],   //   dqs_toggle; // enable toggle DQS according to the pattern
             1'b0,                    //   dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
             1'b0,                    //   buf_wr;     // connect to external buffer (but only if not paused)
-            rom_r[ENC_BUF_RD]);      //   buf_rd;     // connect to external buffer (but only if not paused)
+            rom_r[ENC_BUF_RD],       //   buf_rd;     // connect to external buffer (but only if not paused)
+            rom_r[ENC_BUF_PGNEXT]);     //   buf_rst;    // connect to external buffer (but only if not paused)
        else  enc_cmd <= func_encode_cmd ( // encode non-NOP command
             rom_cmd[1]?
                     row:
@@ -169,8 +172,8 @@ module  cmd_encod_linear_wr #(
             1'b0,                    //   dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
             1'b0,                    //   buf_wr;     // connect to external buffer (but only if not paused)
             rom_r[ENC_BUF_RD],       //   buf_rd;     // connect to external buffer (but only if not paused)     
-            rom_r[ENC_NOP]);         //   nop;        // add NOP after the current command, keep other data
-        
+            rom_r[ENC_NOP],          //   nop;        // add NOP after the current command, keep other data
+            rom_r[ENC_BUF_PGNEXT]);     //   buf_rst;    // connect to external buffer (but only if not paused)
     end    
     
 
@@ -189,6 +192,7 @@ module  cmd_encod_linear_wr #(
         input                      dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
         input                      buf_wr;     // connect to external buffer (but only if not paused)
         input                      buf_rd;     // connect to external buffer (but only if not paused)
+        input                      buf_rst;    // connect to external buffer (but only if not paused)
         begin
             func_encode_skip= func_encode_cmd (
                 {{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]},       // 15-bit row/column adderss
@@ -203,7 +207,8 @@ module  cmd_encod_linear_wr #(
                 dci,        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
                 buf_wr,     // connect to external buffer (but only if not paused)
                 buf_rd,     // connect to external buffer (but only if not paused)
-                1'b0);
+                1'b0,       // nop
+                buf_rst);
         end
     endfunction
 
@@ -221,6 +226,7 @@ module  cmd_encod_linear_wr #(
         input                      buf_wr;     // connect to external buffer (but only if not paused)
         input                      buf_rd;     // connect to external buffer (but only if not paused)
         input                      nop;        // add NOP after the current command, keep other data
+        input                      buf_rst;    // connect to external buffer (but only if not paused)
         begin
             func_encode_cmd={
             addr[14:0], // 15-bit row/column adderss
@@ -236,7 +242,7 @@ module  cmd_encod_linear_wr #(
             buf_wr,     // phy_buf_wr,   // connect to external buffer (but only if not paused)
             buf_rd,     // phy_buf_rd,    // connect to external buffer (but only if not paused)
             nop,        // add NOP after the current command, keep other data
-            1'b0        // Reserved for future use
+            buf_rst     // Reserved for future use
            };
         end
     endfunction

memctrl/cmd_encod_tiled_rd.v

@@ -48,13 +48,14 @@ module  cmd_encod_tiled_rd #(
     input                  [5:0] num_rows_in_m1,   // number of rows to read minus 1
     input                  [5:0] num_cols_in_m1,   // number of 16-pixel columns to read (rows first, then columns) - 1
     input                        keep_open_in,  // keep banks open (for <=8 banks only
+    input                        skip_next_page_in, // do not reset external buffer (continue)    
     input                        start,       // start generating commands
     output reg            [31:0] enc_cmd,     // encoded commnad
     output reg                   enc_wr,      // write encoded command
     output reg                   enc_done     // encoding finished
 );
     localparam FULL_ADDR_NUMBER=ADDRESS_NUMBER+COLADDR_NUMBER; // excluding 3 CA lsb, but adding 3 bank
-    localparam ROM_WIDTH=9;
+    localparam ROM_WIDTH=10;
     localparam ROM_DEPTH=4;
     
     localparam ENC_NOP=        0;
@@ -64,6 +65,7 @@ module  cmd_encod_tiled_rd #(
     localparam ENC_CMD_SHIFT=  4; // [5:4] - command: 0 -= NOP, 1 - READ, 2 - PRECHARGE, 3 - ACTIVATE
     localparam ENC_PAUSE_SHIFT=6; // [7:6] - 2- bit pause (for NOP commandes)
     localparam ENC_PRE_DONE=   8;
+    localparam ENC_BUF_PGNEXT=    9;
     
     localparam ENC_CMD_NOP=      0; // 2-bit locally encoded commands
     localparam ENC_CMD_READ=     1;
@@ -86,7 +88,7 @@ module  cmd_encod_tiled_rd #(
     reg  [FULL_ADDR_NUMBER-4:0] rowcol_inc; // increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts)
     
     reg                        keep_open;                        
-    
+    reg                        skip_next_page;
     reg                        gen_run;
     reg                        gen_run_d;
     reg        [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
@@ -219,6 +221,7 @@ module  cmd_encod_tiled_rd #(
         bank <= start_bank;
         rowcol_inc <= rowcol_inc_in;
         keep_open <= keep_open_in && (|num_cols_in_m1[5:3]!=0);
+        skip_next_page <= skip_next_page_in;
     end
     
     // ROM-based (registered output) encoded sequence
@@ -235,7 +238,7 @@ module  cmd_encod_tiled_rd #(
             4'h7:  rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT)                          | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL); 
             4'h8:  rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT)                          | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL); 
             4'h9:  rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL); 
-            4'h10: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT)                                              | (1 << ENC_DCI) | (1 << ENC_SEL); 
+            4'h10: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL) | (skip_next_page? 1'b0:(1 << ENC_BUF_PGNEXT)); 
             4'h11: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT)                     | (1 << ENC_DCI);
             4'h12: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
             default:rom_r <= 0;
@@ -264,7 +267,8 @@ module  cmd_encod_tiled_rd #(
             1'b0,                    //   dqs_toggle; // enable toggle DQS according to the pattern
             rom_r[ENC_DCI],          //   dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
             rom_r[ENC_BUF_WR],       //   buf_wr;     // connect to external buffer (but only if not paused)
-            1'b0);                   //   buf_rd;     // connect to external buffer (but only if not paused)
+            1'b0,                    //   buf_rd;     // connect to external buffer (but only if not paused)
+            rom_r[ENC_BUF_PGNEXT]);     //   buf_rst;    // connect to external buffer (but only if not paused)
        else  enc_cmd <= func_encode_cmd ( // encode non-NOP command
             rom_cmd[1]? // activate
             row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
@@ -285,10 +289,10 @@ module  cmd_encod_tiled_rd #(
             rom_r[ENC_DCI],          //   dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
             rom_r[ENC_BUF_WR],       //   buf_wr;     // connect to external buffer (but only if not paused)
             1'b0,                    //   buf_rd;     // connect to external buffer (but only if not paused)     
-            rom_r[ENC_NOP]);         //   nop;        // add NOP after the current command, keep other data
+            rom_r[ENC_NOP],          //   nop;        // add NOP after the current command, keep other data
+            rom_r[ENC_BUF_PGNEXT]);     //   buf_rst;    // connect to external buffer (but only if not paused)
     end    
 
-
 // move to include?
 
     function [31:0] func_encode_skip;
@@ -304,6 +308,7 @@ module  cmd_encod_tiled_rd #(
         input                      dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
         input                      buf_wr;     // connect to external buffer (but only if not paused)
         input                      buf_rd;     // connect to external buffer (but only if not paused)
+        input                      buf_rst;    // connect to external buffer (but only if not paused)
         begin
             func_encode_skip= func_encode_cmd (
                 {{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]},       // 15-bit row/column adderss
@@ -318,7 +323,8 @@ module  cmd_encod_tiled_rd #(
                 dci,        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
                 buf_wr,     // connect to external buffer (but only if not paused)
                 buf_rd,     // connect to external buffer (but only if not paused)
-                1'b0);
+                1'b0,       // nop
+                buf_rst);
         end
     endfunction
 
@@ -336,6 +342,7 @@ module  cmd_encod_tiled_rd #(
         input                      buf_wr;     // connect to external buffer (but only if not paused)
         input                      buf_rd;     // connect to external buffer (but only if not paused)
         input                      nop;        // add NOP after the current command, keep other data
+        input                      buf_rst;    // connect to external buffer (but only if not paused)
         begin
             func_encode_cmd={
             addr[14:0], // 15-bit row/column adderss
@@ -351,7 +358,7 @@ module  cmd_encod_tiled_rd #(
             buf_wr,     // phy_buf_wr,   // connect to external buffer (but only if not paused)
             buf_rd,     // phy_buf_rd,    // connect to external buffer (but only if not paused)
             nop,        // add NOP after the current command, keep other data
-            1'b0        // Reserved for future use
+            buf_rst     // Reserved for future use
            };
         end
     endfunction

memctrl/mcntrl_1kx32r.v

@@ -29,20 +29,23 @@ module  mcntrl_1kx32r(
       output [31:0] ext_data_out, // data out
       
       input         wclk,         // !mclk (inverted)
-      input  [1:0]  wpage,        // will register to wclk, input OK with mclk
-      input         waddr_reset,  // reset write buffer address (to page start), sync to wclk (!mclk)
-      input         skip_reset,   // ignore waddr_reset (resync to wclk)   
+      input   [1:0] wpage_in,     // will register to wclk, input OK with mclk
+      input         wpage_set,    // set internal read page to rpage_in 
+      input         page_next,    // advance to next page (and reset lower bits to 0)
+      output  [1:0] page,         // current inernal page   
       input         we,           // write port enable (also increment write buffer address)
       input  [63:0] data_in       // data in
 );
-    reg  [1:0] wpage_wclk;
-    reg        skip_reset_wclk;
+    reg  [1:0] page_r;
     reg  [6:0] waddr;
+    assign page=page_r;
     always @ (posedge wclk) begin
-        wpage_wclk <= wpage;
-        skip_reset_wclk <= skip_reset;
-        if (waddr_reset && !skip_reset_wclk) waddr <= 0;
-        else if (we)                         waddr <= waddr +1;
+    
+        if      (wpage_set) page_r <= wpage_in;
+        else if (page_next) page_r <= page_r+1;
+
+        if      (page_next) waddr <= 0;
+        else if (we)        waddr <= waddr+1;
     end
     ram_512x64w_1kx32r #(
         .REGISTERS(1)
@@ -53,7 +56,7 @@ module  mcntrl_1kx32r(
         .regen    (ext_regen),            // input
         .data_out (ext_data_out),         // output[31:0] 
         .wclk     (wclk),                 // input - OK, negedge mclk
-        .waddr    ({wpage_wclk,waddr}),   // input[8:0] @negedge mclk
+        .waddr    ({page,waddr}),   // input[8:0] @negedge mclk
         .we       (we),                   // input @negedge mclk
         .web      (8'hff),                // input[7:0]
         .data_in  (data_in)        // input[63:0]  @negedge mclk

memctrl/mcntrl_1kx32w.v

@@ -28,29 +28,32 @@ module  mcntrl_1kx32w(
       input  [31:0] ext_data_in,  // data input
       
       input         rclk,         // mclk
-      input  [1:0]  rpage,        // will register to wclk, input OK with mclk
-      input         raddr_reset,  // reset buffer read address (to page start)
-      input         skip_reset,   // ignore waddr_reset (resync to wclk)   
+      input   [1:0] rpage_in,     // will register to wclk, input OK with mclk
+      input         rpage_set,    // set internal read page to rpage_in 
+      input         page_next,    // advance to next page (and reset lower bits to 0)
+      output  [1:0] page,         // current inernal page   
       input         rd,           // read buffer tomemory, increment read address (regester enable will be delayed)
       output [63:0] data_out      // data out
 
 );
-    reg        skip_reset_rclk;
+    reg  [1:0] page_r;
     reg  [6:0] raddr;
     reg        regen;
+    assign page=page_r;
     always @ (posedge rclk) begin
         regen <= rd;
         
-        skip_reset_rclk <= skip_reset;
+        if      (rpage_set) page_r <= rpage_in;
+        else if (page_next) page_r <= page_r+1;
 
-        if (raddr_reset && !skip_reset_rclk) raddr <= 0;
-        else if (rd)                         raddr <= raddr +1;
+        if      (page_next) raddr <= 0;
+        else if (rd)        raddr <= raddr+1;
     end
     ram_1kx32w_512x64r #(
         .REGISTERS(1)
     )ram_1kx32w_512x64r_i (
         .rclk     (rclk),                        // input
-        .raddr    ({rpage,raddr}), // input[8:0] 
+        .raddr    ({page_r,raddr}), // input[8:0] 
         .ren      (rd),                 // input
         .regen    (regen),                 // input
         .data_out (data_out),              // output[63:0] 
@@ -60,7 +63,5 @@ module  mcntrl_1kx32w(
         .web      (4'hf),                        // input[3:0] 
         .data_in  (ext_data_in)                    // input[31:0] 
     );
-
-
 endmodule
 

memctrl/mcntrl_linear_rw.v

@@ -71,7 +71,8 @@ module  mcntrl_linear_rw #(
     output    [COLADDR_NUMBER-4:0] xfer_col,      // start memory column in 8-bursts
     output     [NUM_XFER_BITS-1:0] xfer_num128,   // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
     input                          xfer_done,     // transfer to/from the buffer finished
-    output                   [1:0] xfer_page      // page number for transfer (goes to channel buffer memory-side adderss)   
+    output                         xfer_reset_page // reset internal buffer page to zero
+//    output                   [1:0] xfer_page      // page number for transfer (goes to channel buffer memory-side adderss)   
 
 );
     localparam NUM_RC_BURST_BITS=ADDRESS_NUMBER+COLADDR_NUMBER-3;  //to spcify row and col8 == 22
@@ -102,7 +103,8 @@ module  mcntrl_linear_rw #(
     wire                          calc_valid;   // calculated registers have valid values   
     wire                          chn_en;   // enable requests by channle (continue ones in progress)
     wire                          chn_rst; // resets command, including fifo;
-    reg                     [1:0] xfer_page_r;
+//    reg                     [1:0] xfer_page_r;
+    reg                           xfer_reset_page_r;
     reg                     [2:0] page_cntr;
     
     wire                          cmd_wrmem; // 0: read from memory, 1:write to memory
@@ -197,7 +199,8 @@ module  mcntrl_linear_rw #(
     assign xfer_num128= xfer_num128_r[NUM_XFER_BITS-1:0];
     assign xfer_start=  xfer_start_r[0];
     assign calc_valid=  par_mod_r[PAR_MOD_LATENCY-1]; // MSB, longest 0
-    assign xfer_page=   xfer_page_r;
+//    assign xfer_page=   xfer_page_r;
+    assign xfer_reset_page = xfer_reset_page_r;
     assign frame_done=  frame_done_r;
     assign pre_want=    chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend;
     assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r});
@@ -268,10 +271,15 @@ module  mcntrl_linear_rw #(
         else if ( xfer_start_r[0] && !next_page) page_cntr <= page_cntr + 1;     
         else if (!xfer_start_r[0] &&  next_page) page_cntr <= page_cntr - 1;
         
+/*
         if (rst)                         xfer_page_r <= 0;
 //        else if (chn_rst || frame_start) xfer_page_r <= 0; // TODO: Check if it is better to keep xfer_page_r on frame start?
         else if (chn_rst )               xfer_page_r <= 0; // TODO: Check if it is better to reset xfer_page_r on frame start? to zero?
         else if (xfer_done)              xfer_page_r <= xfer_page_r+1;
+*/
+//        xfer_reset_page_r <= chn_rst || frame_start ; // TODO: Check if it is better to reset page on frame start?
+        xfer_reset_page_r <= chn_rst; // || frame_start ; // TODO: Check if it is better to reset page on frame start?
+
         
 // increment x,y (two cycles)
         if (rst)                                  curr_x <= 0;

memctrl/mcntrl_ps_pio.v

@@ -61,8 +61,8 @@ module  mcntrl_ps_pio#(
     output                       seq_set0,
     input                        seq_done0,
     input                        buf_wr_chn0,
-    input                        buf_waddr_rst_chn0, 
-//    input                [6:0]   buf_waddr_chn0, 
+    input                        buf_wpage_nxt_chn0,
+//    input                        buf_waddr_rst_chn0, 
     input               [63:0]   buf_wdata_chn0,
 // write port 1
     output reg                   want_rq1,
@@ -72,9 +72,9 @@ module  mcntrl_ps_pio#(
 //    output                       seq_wr1, // never generated
 //    output                       seq_set1, // connect externally to seq_set0
     input                        seq_done1,
+    input                        rpage_nxt_chn1,
     input                        buf_rd_chn1,
-    input                        buf_raddr_rst_chn1, 
-//    input                [6:0]   buf_raddr_chn1, 
+//    input                        buf_raddr_rst_chn1, 
     output              [63:0]   buf_rdata_chn1 
 );
  localparam CMD_WIDTH=14;
@@ -106,6 +106,9 @@ module  mcntrl_ps_pio#(
  wire                     busy;
  wire                     start;
  reg                [1:0] page;
+ reg                [1:0] page_neg;
+ reg                [1:0] cmd_set_d;
+ reg                      cmd_set_d_neg;
 // reg                      chn_run; // running memory access to channel 0/1
 // command bit fields
  wire               [9:0] cmd_seq_a= cmd_out[9:0];
@@ -157,8 +160,17 @@ module  mcntrl_ps_pio#(
         if (rst)          page <= 0;
         else if (cmd_set) page <= cmd_page;
         
+        if (rst)          cmd_set_d <= 0;
+        else              cmd_set_d <= {cmd_set_d[0],cmd_set};
     end
     
+    always @ (posedge rst or negedge mclk) begin
+        if (rst)          page_neg <= 0;
+        else if (cmd_set) page_neg <= page;
+        
+        if (rst)          cmd_set_d_neg <= 0;
+        else              cmd_set_d_neg <= cmd_set_d[1];
+    end 
     
     cmd_deser #(
         .ADDR       (MCNTRL_PS_ADDR),
@@ -214,24 +226,7 @@ fifo_same_clock   #(
     );
 
 
-
 // Port 0 (read DDR to AXI) buffer
-/*
-    ram_512x64w_1kx32r #(
-        .REGISTERS(1)
-    ) port0_buf_i (
-        .rclk     (port0_clk), // input
-        .raddr    (port0_addr), // input[9:0] 
-        .ren      (port0_re), // input
-        .regen    (port0_regen), // input
-        .data_out (port0_data), // output[31:0] 
-        .wclk     (!mclk), // input
-        .waddr    ({page,buf_waddr_chn0}), // input[8:0] 
-        .we       (buf_wr_chn0), // input
-        .web      (8'hff), // input[7:0] 
-        .data_in  (buf_wdata_chn0) // input[63:0] 
-    );
-*/
     mcntrl_1kx32r chn0_buf_i (
         .ext_clk      (port0_clk), // input
         .ext_raddr    (port0_addr), // input[9:0] 
@@ -239,39 +234,25 @@ fifo_same_clock   #(
         .ext_regen    (port0_regen), // input
         .ext_data_out (port0_data), // output[31:0] 
         .wclk         (!mclk), // input
-        .wpage        (page), // input[1:0] 
-        .waddr_reset  (buf_waddr_rst_chn0), // input
-        .skip_reset   (1'b0), // input
+        .wpage_in     (page_neg), // input[1:0] 
+        .wpage_set    (cmd_set_d_neg), // input 
+        .page_next    (buf_wpage_nxt_chn0), // input
+        .page         (), // output[1:0]
         .we           (buf_wr_chn0), // input
         .data_in      (buf_wdata_chn0) // input[63:0] 
     );
     
 // Port 1 (write DDR from AXI) buffer
-/*
-    ram_1kx32w_512x64r #(
-        .REGISTERS(1)
-    ) port1_buf_i (
-        .rclk     (mclk), // input
-        .raddr    ({page,buf_raddr_chn1}), // input[8:0] 
-        .ren      (buf_rd_chn1), // input
-        .regen    (buf_rd_chn1), // input
-        .data_out (buf_rdata_chn1), // output[63:0] 
-        .wclk     (port1_clk), // input
-        .waddr    (port1_addr), // input[9:0] 
-        .we       (port1_we), // input
-        .web      (4'hf), // input[3:0] 
-        .data_in  (port1_data) // input[31:0] 
-    );
-*/    
      mcntrl_1kx32w chn1_buf_i (
         .ext_clk      (port1_clk), // input
         .ext_waddr    (port1_addr), // input[9:0] 
         .ext_we       (port1_we), // input
         .ext_data_in  (port1_data), // input[31:0] buf_wdata - from AXI
         .rclk         (mclk), // input
-        .rpage       (page), // input[1:0] 
-        .raddr_reset (buf_raddr_rst_chn1), // input
-        .skip_reset  (1'b0), // input
+        .rpage_in     (page), // input[1:0] 
+        .rpage_set    (cmd_set_d[0]), // input 
+        .page_next    (rpage_nxt_chn1), // input
+        .page         (), // output[1:0]
         .rd           (buf_rd_chn1), // input
         .data_out     (buf_rdata_chn1) // output[63:0] 
     );

phy/mcontr_sequencer.v

@@ -143,7 +143,7 @@ module  mcontr_sequencer   #(
 // There will be =1 cycle external latency in address/re and 1 cycle latency in read data (should match sequence programs)
 // Address data is sync to posedge mclk
     output                       ext_buf_rd,
-    output                       ext_buf_raddr_rst, // reset external buffer address to page start
+    output                       ext_buf_rpage_nxt, // increment external buffer read address to next page start
 //    output                 [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally
     output                 [3:0] ext_buf_rchn,   // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally
     input                 [63:0] ext_buf_rdata, // Latency of ram_1kx32w_512x64r plus 2
@@ -152,7 +152,7 @@ module  mcontr_sequencer   #(
 // Address/data sync to negedge mclk!, any latency OK - just generate DONE appropriately (through the sequencer with delay?
 // folowing a sync to negedge!
     output                       ext_buf_wr,
-    output                       ext_buf_waddr_rst, // reset external buffer address to page start
+    output                       ext_buf_wpage_nxt, // increment external buffer write address to next page start
 //    output                 [6:0] ext_buf_waddr,  // valid with ext_buf_wr
     output                 [3:0] ext_buf_wchn,   // ==run_chn_d valid 1 cycle ahead of ext_buf_wr!, maybe not needed - will be generated externally
     output                [63:0] ext_buf_wdata,   // valid with ext_buf_wr
@@ -222,8 +222,9 @@ module  mcontr_sequencer   #(
 //    wire                 [63:0]  buf1_rdata;
     wire                         buf_wr; // delayed by specified number of clock cycles
     wire                         buf_wr_ndly; // before dealy
-    wire                         buf_rd; // read next 64 bytes from the buffer, need one extra pre-read
-    
+    wire                         buf_rd; // read next 64 bits from the buffer, need one extra pre-read
+    wire                         buf_rst; // reset buffer address to 
+    wire                         buf_rst_d; //buf_rst delayed to match buf_wr 
     wire                         rst=rst_in;
   
 //    wire                 [ 9:0]  next_cmd_addr;
@@ -241,10 +242,12 @@ module  mcontr_sequencer   #(
     
  //   reg                   [1:0]  buf_page;      // one of 4 pages in the channel buffer to use for R/W
  //   reg                  [15:0]  buf_sel_1hot; // 1 hot channel buffer select
+    wire                  [3:0]  run_chn_w_d; // run chn delayed to match buf_wr delay
     
     reg                   [3:0]  run_chn_d;
-    reg                   [3:0]  run_chn_d_negedge;
-    reg                          run_seq_d; 
+    reg                   [3:0]  run_chn_w_d_negedge;
+    
+//    reg                        run_seq_d; 
     
     wire [7:0] tmp_debug_a;
     assign tmp_debug[11:0] =
@@ -266,17 +269,17 @@ module  mcontr_sequencer   #(
     
 // External buffers buffer related signals
 
-    assign buf_raddr_reset= run_seq_d;
+    assign buf_raddr_reset=  buf_rst; // run_seq_d;
     assign ext_buf_rd=       buf_rd;
-    assign ext_buf_raddr_rst=buf_raddr_reset;
+    assign ext_buf_rpage_nxt=buf_raddr_reset;
 //    assign ext_buf_raddr=    buf_raddr;
     assign ext_buf_rchn=     run_chn_d;
     assign buf_rdata[63:0] = ext_buf_rdata;
     
     assign ext_buf_wr=       buf_wr_negedge;
-    assign ext_buf_waddr_rst=buf_waddr_reset_negedge;
+    assign ext_buf_wpage_nxt=buf_waddr_reset_negedge;
 //    assign ext_buf_waddr=    buf_waddr_negedge;
-    assign ext_buf_wchn=     run_chn_d_negedge;
+    assign ext_buf_wchn=     run_chn_w_d_negedge;
     assign ext_buf_wdata=    buf_wdata_negedge;
     
 // generation of the control signals from byte-serial channel
@@ -441,18 +444,17 @@ module  mcontr_sequencer   #(
 
         if (rst)          run_chn_d <= 0;
         else if (run_seq) run_chn_d <= run_chn;
-        if (rst) run_seq_d <= 0;
-        else run_seq_d <= run_seq;
+//        if (rst) run_seq_d <= 0;
+//        else run_seq_d <= run_seq;
         
     end
     // re-register buffer write address to match DDR3 data
     always @ (negedge mclk) begin
 //        buf_waddr_negedge <= buf_raddr;
-        buf_waddr_reset_negedge <= buf_raddr_reset;
+        buf_waddr_reset_negedge <= buf_rst_d; //buf_raddr_reset;
         buf_wr_negedge <= buf_wr;
         buf_wdata_negedge <= buf_wdata;
-        run_chn_d_negedge <= run_chn_d;
-        //TODO: add write channel number?
+        run_chn_w_d_negedge <= run_chn_w_d; //run_chn_d;
         
     end
 // Command sequence memories:
@@ -568,6 +570,7 @@ module  mcontr_sequencer   #(
         .buf_rdata           (buf_rdata[63:0]), // input[63:0] 
         .buf_wr              (buf_wr_ndly), // output
         .buf_rd              (buf_rd),    // output
+        .buf_rst             (buf_rst),   // reset external buffer address to page start 
         .cmda_en             (cmda_en), // input
         .ddr_rst             (ddr_rst), // input
         .dci_rst             (dci_rst), // input
@@ -582,13 +585,21 @@ module  mcontr_sequencer   #(
         .dqs_tri_off_pattern (dqs_tri_off_pattern[3:0]) // input[3:0] 
     );
     // delay buf_wr by 1-16 cycles to compensate for DDR and HDL code latency (~7 cycles?)
-    dly01_16 buf_wr_dly_i (
+    dly_16 #(2) buf_wr_dly_i (
         .clk(mclk), // input
         .rst(1'b0), // input
         .dly(wbuf_delay[3:0]), // input[3:0] 
-        .din(buf_wr_ndly), // input
-        .dout(buf_wr) // output reg 
+        .din({buf_rst,buf_wr_ndly}), // input
+        .dout({buf_rst_d, buf_wr}) // output reg 
     );
 
+    dly_16 #(4) buf_wchn_dly_i (
+        .clk(mclk), // input
+        .rst(1'b0), // input
+        .dly(wbuf_delay[3:0]-1), // input[3:0] 
+        .din(run_chn_d), // input
+        .dout(run_chn_w_d) // output reg 
+    );
+//run_chn_w_d
 endmodule
 

phy/phy_cmd.v

@@ -105,6 +105,7 @@ module  phy_cmd#(
     input                 [63:0] buf_rdata, // data read from the buffer (to DDR3)
     output                       buf_wr,    // write buffer (next cycle!)
     output                       buf_rd,    // read buffer  (ready next cycle)
+    output                       buf_rst,   // reset external buffer address to page start 
     // extras
 //    input                        cmda_tri, // tristate command and address lines // not likely to be used
     input                        cmda_en, // tristate command and address lines // not likely to be used
@@ -140,6 +141,7 @@ module  phy_cmd#(
     wire                         phy_dqs_toggle_en;  //enable toggle DQS according to the pattern
     wire                         phy_buf_wr;   // connect to extrenal buffer
     wire                         phy_buf_rd;   // connect to extrenal buffer
+    wire                         phy_buf_rst;  // reset buffers to page start
     wire                         cmda_tri;
  
     wire                  [2:0]  phy_rcw_cur; // {ras,cas,we}
@@ -152,7 +154,7 @@ module  phy_cmd#(
     wire                         phy_dci_en_cur;    //phy_dci_in,      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
     wire                         phy_buf_wr_cur;       // connect to external buffer (but only if not paused)
     wire                         phy_buf_rd_cur;        // connect to external buffer (but only if not paused)
- 
+    wire                         phy_buf_rst_cur;
     
 //    wire                         clk;
     wire                         clk_div;
@@ -192,7 +194,8 @@ module  phy_cmd#(
     reg                  [ 2:0] phy_bank_prev;
     wire   [ADDRESS_NUMBER-1:0] phy_addr_calm;
     wire                 [ 2:0] phy_bank_calm;
-    reg                  [ 8:0] extra_prev;
+//    reg                  [ 8:0] extra_prev;
+    reg                  [ 9:0] extra_prev;
     
 //    assign     phy_locked= phy_locked_mmcm && phy_locked_pll; // no dci and dly here
     
@@ -200,7 +203,7 @@ module  phy_cmd#(
     
 //    output                [63:0] buf_wdata, // data to be written to the buffer (from DDR3)
     // SuppressWarnings VEditor 
-  (* keep = "true" *)  wire  phy_spare;
+//  (* keep = "true" *)  wire  phy_spare;
     assign {
         phy_addr_in,
         phy_bank_in,
@@ -216,20 +219,21 @@ module  phy_cmd#(
         phy_buf_wr,   // connect to external buffer (but only if not paused)
         phy_buf_rd,    // connect to external buffer (but only if not paused)
         phy_cmd_add_pause, // add nop to current command
-        phy_spare      // Reserved for future use
+        phy_buf_rst // phy_spare      // Reserved for future use
     } =  phy_cmd_word;
     
     assign {
         phy_rcw_cur[2:0],  // all set to 0 
-        phy_odt_cur,       // 8 ODT
-        phy_cke_dis_cur,   // 7 disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed)
-        phy_sel_cur,       // 6 first/second half-cycle, other will be nop (cke+odt applicable to both) - NOT USED?
-        phy_dq_en_cur,     // 5 phy_dq_tri_in,   // tristate DQ  lines (internal timing sequencer for 0->1 and 1->0)
-        phy_dqs_en_cur,    // 4 phy_dqs_tri_in,  // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
-        phy_dqs_toggle_cur,// 3 enable toggle DQS according to the pattern
-        phy_dci_en_cur,    // 2 phy_dci_in,      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
-        phy_buf_wr_cur,    // 1 connect to external buffer (but only if not paused)
-        phy_buf_rd_cur     // 0 connect to external buffer (but only if not paused)
+        phy_odt_cur,       // 9 8 ODT
+        phy_cke_dis_cur,   // 8 7 disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed)
+        phy_sel_cur,       // 7 6 first/second half-cycle, other will be nop (cke+odt applicable to both) - NOT USED?
+        phy_dq_en_cur,     // 6 5 phy_dq_tri_in,   // tristate DQ  lines (internal timing sequencer for 0->1 and 1->0)
+        phy_dqs_en_cur,    // 5 4 phy_dqs_tri_in,  // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
+        phy_dqs_toggle_cur,// 4 3 enable toggle DQS according to the pattern
+        phy_dci_en_cur,    // 3 2 phy_dci_in,      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+        phy_buf_wr_cur,    // 2 1 connect to external buffer (but only if not paused)
+        phy_buf_rd_cur,    // 1 0 connect to external buffer (but only if not paused)
+        phy_buf_rst_cur    // 0
     } =  add_pause ? {3'b0, extra_prev} : // 3'b0 for rcw (nop)
     {
         phy_rcw_pos[2:0],      // {ras,cas,we}
@@ -241,7 +245,8 @@ module  phy_cmd#(
         phy_dqs_toggle_en,   //enable toggle DQS according to the pattern
         phy_dci_en_in, //phy_dci_in,      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
         phy_buf_wr,   // connect to external buffer (but only if not paused)
-        phy_buf_rd    // connect to external buffer (but only if not paused)
+        phy_buf_rd,    // connect to external buffer (but only if not paused)
+        phy_buf_rst
     };
     assign phy_cke_in=     phy_cke_dis_cur ^ ddr_cke;
     assign phy_dq_tri_in= ~phy_dq_en_cur;
@@ -257,6 +262,7 @@ module  phy_cmd#(
 //    assign buf_addr = phy_buf_addr;
     assign buf_wr =   phy_buf_wr_cur;
     assign buf_rd =   phy_buf_rd_cur;
+    assign buf_rst=   phy_buf_rst_cur;
     
 //    assign  phy_addr=   {phy_addr_in,phy_addr_in};       // also provides pause length when the command is NOP
 //    assign  phy_bank=   {phy_bank_in,phy_bank_in};
@@ -302,15 +308,16 @@ module  phy_cmd#(
             phy_addr_prev <= phy_addr_in;
             phy_bank_prev <= phy_bank_in;
             extra_prev <=  {
-                   phy_odt_in,       // 8 may be optimized?
-                   phy_cke_dis,      // 7 disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed)
-                   phy_sel_in,       // 6 first/second half-cycle, other will be nop (cke+odt applicable to both)
-                   phy_dq_en_in,     // 5 phy_dq_tri_in,   // tristate DQ  lines (internal timing sequencer for 0->1 and 1->0)
-                   phy_dqs_en_in,    // 4 phy_dqs_tri_in,  // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
-                   phy_dqs_toggle_en,// 3 enable toggle DQS according to the pattern
-                   phy_dci_en_in,    // 2 phy_dci_in,      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
-                   phy_buf_wr,       // 1 connect to external buffer (but only if not paused)
-                   phy_buf_rd        // 0 connect to external buffer (but only if not paused)
+                   phy_odt_in,       // 9 8 may be optimized?
+                   phy_cke_dis,      // 8 7 disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed)
+                   phy_sel_in,       // 7 6 first/second half-cycle, other will be nop (cke+odt applicable to both)
+                   phy_dq_en_in,     // 6 5 phy_dq_tri_in,   // tristate DQ  lines (internal timing sequencer for 0->1 and 1->0)
+                   phy_dqs_en_in,    // 5 4 phy_dqs_tri_in,  // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
+                   phy_dqs_toggle_en,// 4 3 enable toggle DQS according to the pattern
+                   phy_dci_en_in,    // 3 2 phy_dci_in,      // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
+                   phy_buf_wr,       // 2 1 connect to external buffer (but only if not paused)
+                   phy_buf_rd,       // 1 0 connect to external buffer (but only if not paused)
+                   phy_buf_rst       // 0 connect to external buffer (but only if not paused)
             };
             
         end

util_modules/dly_16.v

+/*******************************************************************************
+ * Module: dly_16
+ * Date:2014-05-30  
+ * Author: Andrey Filippov
+ * Description: Synchronous delay by 1-16 clock cycles with reset (will map to primitives)
+ *
+ * Copyright (c) 2014 Elphel, Inc.
+ * dly_16.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  dly_16.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  dly_16 #(
+    parameter WIDTH=1
+    )(
+    input               clk,
+    input               rst,
+    input         [3:0] dly,
+    input   [WIDTH-1:0] din,
+    output  [WIDTH-1:0] dout
+);
+  generate
+    genvar i;
+    for (i=0; i < WIDTH; i=i+1) begin: bit_block
+        dly01_16 dly01_16_i (
+            .clk(clk), // input
+            .rst(rst), // input
+            .dly(dly), // input[3:0] 
+            .din(din[i]), // input
+            .dout(dout[i]) // output reg 
+        );
+    end
+  endgenerate
+endmodule
+

util_modules/mcont_common_chnbuf_reg.v

+/*******************************************************************************
+ * Module: mcont_common_chnbuf_reg
+ * Date:2015-01-19  
+ * Author: andrey     
+ * Description: Registering data from channel buffer to memory controller
+ *
+ * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ * mcont_common_chnbuf_reg.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  mcont_common_chnbuf_reg.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  mcont_common_chnbuf_reg #(
+    parameter CHN_NUMBER=0
+)(
+    input rst,
+    input clk,
+    input                 [3:0] ext_buf_rchn,  // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally
+    input                       ext_buf_rpage_nxt,
+    input                       seq_done,      // sequence done
+    output reg                  buf_done,      // sequence done for the specified channel
+    output reg                  rpage_nxt
+);
+    reg                 buf_chn_sel;
+    always @ (posedge rst or posedge clk) begin
+        if (rst) buf_chn_sel <= 0;
+        else     buf_chn_sel <= (ext_buf_rchn==CHN_NUMBER);
+        
+        if (rst) buf_done <= 0;
+        else     buf_done <= buf_chn_sel && seq_done;
+       
+    end
+    always @ (posedge clk)  rpage_nxt <= ext_buf_rpage_nxt && (ext_buf_rchn==CHN_NUMBER);
+endmodule
+

util_modules/mcont_from_chnbuf_reg.v

@@ -27,15 +27,13 @@ module  mcont_from_chnbuf_reg #(
     input rst,
     input clk,
     input                       ext_buf_rd,
-    input                       ext_buf_raddr_rst,
-//    input                 [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally
+//    input                       ext_buf_raddr_rst,
     input                 [3:0] ext_buf_rchn,  // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally
-    input                       seq_done,      // sequence done
-    output reg                  buf_done,      // sequence done for the specified channel
+//    input                       seq_done,      // sequence done
+//    output reg                  buf_done,      // sequence done for the specified channel
     output reg           [63:0] ext_buf_rdata, // Latency of ram_1kx32w_512x64r plus 2
     output reg                  buf_rd_chn,
-    output reg                  buf_raddr_rst_chn,
-//    output reg            [6:0] buf_raddr_chn,
+//    output reg                  buf_raddr_rst_chn,
     input                [63:0] buf_rdata_chn
 );
     reg                 buf_chn_sel;
@@ -53,7 +51,7 @@ module  mcont_from_chnbuf_reg #(
         if (rst) buf_done <= 0;
         else     buf_done <= buf_chn_sel && seq_done;
     end
-    always @ (posedge clk)  buf_raddr_rst_chn <= ext_buf_raddr_rst && (ext_buf_rchn==CHN_NUMBER);
+//    always @ (posedge clk)  buf_raddr_rst_chn <= ext_buf_raddr_rst && (ext_buf_rchn==CHN_NUMBER);
 //    always @ (posedge clk) if (buf_chn_sel && ext_buf_rd) buf_raddr_chn <= ext_buf_raddr;
     always @ (posedge clk) if (latency_reg[CHN_LATENCY])  ext_buf_rdata <= buf_rdata_chn;
 endmodule

util_modules/mcont_to_chnbuf_reg.v

@@ -26,15 +26,13 @@ parameter CHN_NUMBER=0
     input rst,
     input clk,
     input                       ext_buf_wr,
-    input                       ext_buf_waddr_rst,
-//    input                 [6:0] ext_buf_waddr,  // valid with ext_buf_wr
+    input                       ext_buf_wpage_nxt,
     input                 [3:0] ext_buf_wchn,     // ==run_chn_d valid 1 cycle ahead opf ext_buf_wr!, maybe not needed - will be generated externally
     input                [63:0] ext_buf_wdata,    // valid with ext_buf_wr
-    input                       seq_done,         // sequence done
-    output reg                  buf_done,         // @ posedge mclk sequence done for the specified channel
+//    input                       seq_done,         // sequence done
+//    output reg                  buf_done,         // @ posedge mclk sequence done for the specified channel
     output reg                  buf_wr_chn,       // @ negedge mclk
-    output reg                  buf_waddr_rst_chn,// @ negedge mclk
-//    output reg            [6:0] buf_waddr_chn,  // @ negedge mclk
+    output reg                  buf_wpage_nxt_chn,// @ negedge mclk
     output reg           [63:0] buf_wdata_chn     // @ negedge mclk
 );
     reg buf_chn_sel;
@@ -46,17 +44,16 @@ parameter CHN_NUMBER=0
         else     buf_wr_chn <= buf_chn_sel && ext_buf_wr;
     end
     
-    always @ (posedge rst or posedge clk) begin
-        if (rst) buf_done <= 0;
-        else     buf_done <= buf_chn_sel && seq_done;
-    end
+//    always @ (posedge rst or posedge clk) begin
+//        if (rst) buf_done <= 0;
+//        else     buf_done <= buf_chn_sel && seq_done;
+//    end
     
     always @ (negedge clk)  begin
-        buf_waddr_rst_chn <= ext_buf_waddr_rst && (ext_buf_wchn==CHN_NUMBER);
+        buf_wpage_nxt_chn <= ext_buf_wpage_nxt && (ext_buf_wchn==CHN_NUMBER);
     end
     
     always @ (negedge clk) if (buf_chn_sel && ext_buf_wr) begin
-//        buf_waddr_chn <= ext_buf_waddr;
         buf_wdata_chn <= ext_buf_wdata;
     end
 endmodule