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Commit ecd4a509 authored by Andrey Filippov's avatar Andrey Filippov
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modifying memory controller buffer interface

parent db31f7a9
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Showing with 578 additions and 388 deletions
memctrl/cmd_encod_linear_rd.v
View file @ ecd4a509
......@@ -51,9 +51,10 @@ module cmd_encod_linear_rd #(
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
localparam ROM_WIDTH=9;
localparam ROM_WIDTH=10;
localparam ROM_DEPTH=4;
// localparam ENC_BUF_PGNEXT= 0;
localparam ENC_NOP= 0;
localparam ENC_BUF_WR= 1;
localparam ENC_DCI= 2;
......@@ -61,6 +62,7 @@ module cmd_encod_linear_rd #(
localparam ENC_CMD_SHIFT= 4; // [5:4] - command: 0 -= NOP, 1 - READ, 2 - PRECHARGE, 3 - ACTIVATE
localparam ENC_PAUSE_SHIFT=6; // [7:6] - 2- bit pause (for NOP commandes)
localparam ENC_PRE_DONE= 8;
localparam ENC_BUF_PGNEXT= 9;
localparam ENC_CMD_NOP= 0; // 2-bit locally encoded commands
localparam ENC_CMD_READ= 1;
......@@ -128,7 +130,7 @@ module cmd_encod_linear_rd #(
4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PAUSE_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h5: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h5: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h6: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT) | (1 << ENC_DCI);
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI);
4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
......@@ -158,7 +160,8 @@ module cmd_encod_linear_rd #(
1'b0, // dqs_toggle; // enable toggle DQS according to the pattern
rom_r[ENC_DCI], // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)
1'b0); // buf_rd; // connect to external buffer (but only if not paused)
1'b0, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
else enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]?
row:
......@@ -174,7 +177,8 @@ module cmd_encod_linear_rd #(
rom_r[ENC_DCI], // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)
1'b0, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_NOP]); // nop; // add NOP after the current command, keep other data
rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
end
......@@ -193,6 +197,7 @@ module cmd_encod_linear_rd #(
input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_skip= func_encode_cmd (
{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column adderss
......@@ -207,7 +212,8 @@ module cmd_encod_linear_rd #(
dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // connect to external buffer (but only if not paused)
1'b0);
1'b0, // nop
buf_rst);
end
endfunction
......@@ -225,6 +231,7 @@ module cmd_encod_linear_rd #(
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input nop; // add NOP after the current command, keep other data
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_cmd={
addr[14:0], // 15-bit row/column adderss
......@@ -240,7 +247,7 @@ module cmd_encod_linear_rd #(
buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)
nop, // add NOP after the current command, keep other data
1'b0 // Reserved for future use
buf_rst // Reserved for future use
};
end
endfunction
......
memctrl/cmd_encod_linear_wr.v
View file @ ecd4a509
......@@ -42,7 +42,7 @@ module cmd_encod_linear_wr #(
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
localparam ROM_WIDTH=11;
localparam ROM_WIDTH=12;
localparam ROM_DEPTH=4;
localparam ENC_NOP= 0;
......@@ -54,6 +54,7 @@ module cmd_encod_linear_wr #(
localparam ENC_CMD_SHIFT= 6; // [7:6] - command: 0 -= NOP, 1 - WRITE, 2 - PRECHARGE, 3 - ACTIVATE
localparam ENC_PAUSE_SHIFT=8; // [9:8] - 2- bit pause (for NOP commandes)
localparam ENC_PRE_DONE= 10;
localparam ENC_BUF_PGNEXT= 11;
localparam ENC_CMD_NOP= 0; // 2-bit locally encoded commands
localparam ENC_CMD_WRITE= 1;
......@@ -114,6 +115,7 @@ module cmd_encod_linear_wr #(
end
// ROM-based (registered output) encoded sequence
// TODO: Remove last ENC_BUF_RD
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
else case (gen_addr)
......@@ -124,7 +126,7 @@ module cmd_encod_linear_wr #(
4'h4: rom_r <= (ENC_CMD_WRITE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_BUF_RD) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT); // will repeet
4'h5: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_DQS_TOGGLE) | (1 << ENC_DQ_DQS_EN) | (1 << ENC_ODT);
4'h6: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT);
4'h7: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT);
4'h7: rom_r <= (ENC_CMD_PRECHARGE << ENC_CMD_SHIFT) | (1 << ENC_BUF_PGNEXT);
4'h8: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT);
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
default:rom_r <= 0;
......@@ -153,7 +155,8 @@ module cmd_encod_linear_wr #(
rom_r[ENC_DQS_TOGGLE], // dqs_toggle; // enable toggle DQS according to the pattern
1'b0, // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // buf_wr; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD]); // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD], // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
else enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]?
row:
......@@ -169,8 +172,8 @@ module cmd_encod_linear_wr #(
1'b0, // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
1'b0, // buf_wr; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_RD], // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_NOP]); // nop; // add NOP after the current command, keep other data
rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
end
......@@ -189,6 +192,7 @@ module cmd_encod_linear_wr #(
input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_skip= func_encode_cmd (
{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column adderss
......@@ -203,7 +207,8 @@ module cmd_encod_linear_wr #(
dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // connect to external buffer (but only if not paused)
1'b0);
1'b0, // nop
buf_rst);
end
endfunction
......@@ -221,6 +226,7 @@ module cmd_encod_linear_wr #(
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input nop; // add NOP after the current command, keep other data
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_cmd={
addr[14:0], // 15-bit row/column adderss
......@@ -236,7 +242,7 @@ module cmd_encod_linear_wr #(
buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)
nop, // add NOP after the current command, keep other data
1'b0 // Reserved for future use
buf_rst // Reserved for future use
};
end
endfunction
......
memctrl/cmd_encod_tiled_rd.v
View file @ ecd4a509
......@@ -47,14 +47,15 @@ module cmd_encod_tiled_rd #(
input [ADDRESS_NUMBER+COLADDR_NUMBER-4:0] rowcol_inc_in, // increment {row.col} when bank rolls over, removed 3 LSBs (in 8-bursts)
input [5:0] num_rows_in_m1, // number of rows to read minus 1
input [5:0] num_cols_in_m1, // number of 16-pixel columns to read (rows first, then columns) - 1
input keep_open_in, // keep banks open (for <=8 banks only
input keep_open_in, // keep banks open (for <=8 banks only
input skip_next_page_in, // do not reset external buffer (continue)
input start, // start generating commands
output reg [31:0] enc_cmd, // encoded commnad
output reg enc_wr, // write encoded command
output reg enc_done // encoding finished
);
localparam FULL_ADDR_NUMBER=ADDRESS_NUMBER+COLADDR_NUMBER; // excluding 3 CA lsb, but adding 3 bank
localparam ROM_WIDTH=9;
localparam ROM_WIDTH=10;
localparam ROM_DEPTH=4;
localparam ENC_NOP= 0;
......@@ -64,6 +65,7 @@ module cmd_encod_tiled_rd #(
localparam ENC_CMD_SHIFT= 4; // [5:4] - command: 0 -= NOP, 1 - READ, 2 - PRECHARGE, 3 - ACTIVATE
localparam ENC_PAUSE_SHIFT=6; // [7:6] - 2- bit pause (for NOP commandes)
localparam ENC_PRE_DONE= 8;
localparam ENC_BUF_PGNEXT= 9;
localparam ENC_CMD_NOP= 0; // 2-bit locally encoded commands
localparam ENC_CMD_READ= 1;
......@@ -86,7 +88,7 @@ module cmd_encod_tiled_rd #(
reg [FULL_ADDR_NUMBER-4:0] rowcol_inc; // increment {row.col} when bank rolls over, remove 3 LSBs (in 8-bursts)
reg keep_open;
reg skip_next_page;
reg gen_run;
reg gen_run_d;
reg [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
......@@ -219,13 +221,14 @@ module cmd_encod_tiled_rd #(
bank <= start_bank;
rowcol_inc <= rowcol_inc_in;
keep_open <= keep_open_in && (|num_cols_in_m1[5:3]!=0);
skip_next_page <= skip_next_page_in;
end
// ROM-based (registered output) encoded sequence
always @ (posedge rst or posedge clk) begin
if (rst) rom_r <= 0;
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_NOP);
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_NOP);
4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
4'h2: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h3: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL);
......@@ -235,7 +238,7 @@ module cmd_encod_tiled_rd #(
4'h7: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h8: rom_r <= (ENC_CMD_READ << ENC_CMD_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h9: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h10: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL);
4'h10: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL) | (skip_next_page? 1'b0:(1 << ENC_BUF_PGNEXT));
4'h11: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT) | (1 << ENC_DCI);
4'h12: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
default:rom_r <= 0;
......@@ -264,7 +267,8 @@ module cmd_encod_tiled_rd #(
1'b0, // dqs_toggle; // enable toggle DQS according to the pattern
rom_r[ENC_DCI], // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)
1'b0); // buf_rd; // connect to external buffer (but only if not paused)
1'b0, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
else enc_cmd <= func_encode_cmd ( // encode non-NOP command
rom_cmd[1]? // activate
row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
......@@ -285,9 +289,9 @@ module cmd_encod_tiled_rd #(
rom_r[ENC_DCI], // dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
rom_r[ENC_BUF_WR], // buf_wr; // connect to external buffer (but only if not paused)
1'b0, // buf_rd; // connect to external buffer (but only if not paused)
rom_r[ENC_NOP]); // nop; // add NOP after the current command, keep other data
rom_r[ENC_NOP], // nop; // add NOP after the current command, keep other data
rom_r[ENC_BUF_PGNEXT]); // buf_rst; // connect to external buffer (but only if not paused)
end
// move to include?
......@@ -304,6 +308,7 @@ module cmd_encod_tiled_rd #(
input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_skip= func_encode_cmd (
{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column adderss
......@@ -318,7 +323,8 @@ module cmd_encod_tiled_rd #(
dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // connect to external buffer (but only if not paused)
1'b0);
1'b0, // nop
buf_rst);
end
endfunction
......@@ -336,6 +342,7 @@ module cmd_encod_tiled_rd #(
input buf_wr; // connect to external buffer (but only if not paused)
input buf_rd; // connect to external buffer (but only if not paused)
input nop; // add NOP after the current command, keep other data
input buf_rst; // connect to external buffer (but only if not paused)
begin
func_encode_cmd={
addr[14:0], // 15-bit row/column adderss
......@@ -351,7 +358,7 @@ module cmd_encod_tiled_rd #(
buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)
buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)
nop, // add NOP after the current command, keep other data
1'b0 // Reserved for future use
buf_rst // Reserved for future use
};
end
endfunction
......
memctrl/mcntrl393.v
View file @ ecd4a509
......@@ -296,21 +296,17 @@ module mcntrl393 #(
// wire seq_wr0; // not used
wire seq_set0;
wire seq_done0;
// wire rpage_nxt_chn0;
wire buf_wr_chn0;
wire buf_waddr_rst_chn0;
// wire [6:0] buf_waddr_chn0;
wire buf_wpage_nxt_chn0;
wire [63:0] buf_wdata_chn0;
wire want_rq1;
wire need_rq1;
wire channel_pgm_en1;
// wire [9:0] seq_data1=seq_data0; // use the same
// wire seq_wr1; // not used
// wire seq_set1; // not used
wire seq_done1;
wire rpage_nxt_chn1;
wire buf_rd_chn1;
wire buf_raddr_rst_chn1;
// wire [6:0] buf_raddr_chn1;
wire [63:0] buf_rdata_chn1;
wire want_rq2;
......@@ -320,8 +316,9 @@ module mcntrl393 #(
wire seq_wr2x; // may be shared with other channel
wire seq_set2x; // may be shared with other channel
wire seq_done2;
// wire rpage_nxt_chn2;
wire buf_wr_chn2;
wire buf_waddr_rst_chn2;
wire buf_wpage_nxt_chn2;
// wire [6:0] buf_waddr_chn2;
wire [63:0] buf_wdata_chn2;
......@@ -332,8 +329,8 @@ module mcntrl393 #(
wire seq_wr3x; // may be shared with other channel
wire seq_set3x; // may be shared with other channel
wire seq_done3;
wire rpage_nxt_chn3;
wire buf_rd_chn3;
wire buf_raddr_rst_chn3;
// wire [6:0] buf_raddr_chn3;
wire [63:0] buf_rdata_chn3;
......@@ -344,8 +341,9 @@ module mcntrl393 #(
wire seq_wr4;
wire seq_set4;
wire seq_done4;
wire rpage_nxt_chn4;
wire buf_wr_chn4;
wire buf_waddr_rst_chn4;
wire buf_wpage_nxt_chn4;
// wire [6:0] buf_waddr_chn4;
wire [63:0] buf_wdata_chn4;
......@@ -423,14 +421,18 @@ module mcntrl393 #(
wire [COLADDR_NUMBER-4:0] lin_rd_chn2_col; // start memory column in 8-bursts
wire [5:0] lin_rd_chn2_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire lin_rd_chn2_start; // start generating commands
wire [1:0] xfer_page2; // "internal" buffer page
// wire [1:0] xfer_page2; // "internal" buffer page
wire xfer_reset_page2_pos; // "internal" buffer page reset, @posedge mclk
reg xfer_reset_page2_neg; // "internal" buffer page reset, @negedge mclk
wire [2:0] lin_wr_chn3_bank; // bank address
wire [ADDRESS_NUMBER-1:0] lin_wr_chn3_row; // memory row
wire [COLADDR_NUMBER-4:0] lin_wr_chn3_col; // start memory column in 8-bursts
wire [5:0] lin_wr_chn3_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire lin_wr_chn3_start; // start generating commands
wire [1:0] xfer_page3; // "internal" buffer page
// wire [1:0] xfer_page3; // "internal" buffer page
wire xfer_reset_page3; // "internal" buffer page reset, @posedge mclk
// Command tree - insert register layer(s) if needed, now just direct assignments
......@@ -576,23 +578,10 @@ module mcntrl393 #(
// Port memory buffer (4 pages each, R/W fixed, port 0 - AXI read from DDR, port 1 - AXI write to DDR
// Port 2 (read DDR to AXI) buffer
/*
ram_512x64w_1kx32r #(
.REGISTERS(1)
) chn2_buf_i (
.rclk (axi_clk), // input
.raddr (buf_raddr), // input[9:0]
.ren (buf2_rd), // input
.regen (buf2_regen), // input
.data_out (buf2_data), // output[31:0]
.wclk (!mclk), // input - OK, negedge mclk
.waddr ({xfer_page2,buf_waddr_chn2}), // input[8:0] @negedge mclk
.we (buf_wr_chn2), // input @negedge mclk
.web (8'hff), // input[7:0]
.data_in (buf_wdata_chn2) // input[63:0] @negedge mclk
);
*/
/* Instance template for module mcntrl_1kx32r */
always @ (negedge mclk) begin
xfer_reset_page2_neg <= xfer_reset_page2_pos;
end
mcntrl_1kx32r chn2_buf_i (
.ext_clk (axi_clk), // input
.ext_raddr (buf_raddr), // input[9:0]
......@@ -600,46 +589,33 @@ module mcntrl393 #(
.ext_regen (buf2_regen), // input
.ext_data_out (buf2_data), // output[31:0]
.wclk (!mclk), // input
.wpage (xfer_page2), // input[1:0]
.waddr_reset (buf_waddr_rst_chn2), // input
.skip_reset (1'b0), // input
.wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page2_neg), // input TODO: Generate @ negedge mclk on frame start
.page_next (buf_wpage_nxt_chn2), // input
.page (), // output[1:0]
.we (buf_wr_chn2), // input
.data_in (buf_wdata_chn2) // input[63:0]
);
// Port 3 (write DDR from AXI) buffer
/*
ram_1kx32w_512x64r #(
.REGISTERS(1)
) chn3_buf_i (
.rclk (mclk), // input
.raddr ({xfer_page3,buf_raddr_chn3}), // input[8:0]
.ren (buf_rd_chn3), // input
.regen (buf_rd_chn3), // input
.data_out (buf_rdata_chn3), // output[63:0]
.wclk (axi_clk), // input
.waddr (buf_waddr), // input[9:0]
.we (buf3_we), // input
.web (4'hf), // input[3:0]
.data_in (buf_wdata) // input[31:0]
);
*/
/* Instance template for module mcntrl_1kx32w */
mcntrl_1kx32w chn3_buf_i (
.ext_clk(axi_clk), // input
.ext_waddr(buf_waddr), // input[9:0]
.ext_we(buf3_we), // input
.ext_data_in(buf_wdata), // input[31:0] buf_wdata - from AXI
.rclk(mclk), // input
.rpage(xfer_page3), // input[1:0]
.raddr_reset(buf_raddr_rst_chn3), // input
.skip_reset(1'b0), // input
.rd(buf_rd_chn3), // input
.data_out(buf_rdata_chn3) // output[63:0]
mcntrl_1kx32w chn1_buf_i (
.ext_clk (axi_clk), // input
.ext_waddr (buf_waddr), // input[9:0]
.ext_we (buf3_we), // input
.ext_data_in (buf_wdata), // input[31:0] buf_wdata - from AXI
.rclk (mclk), // input
.rpage_in (2'b0), // input[1:0]
.rpage_set (xfer_reset_page3), // input TODO: Generate @ posedge mclk on frame start
.page_next (rpage_nxt_chn3), // input
.page (), // output[1:0]
.rd (buf_rd_chn3), // input
.data_out (buf_rdata_chn3) // output[63:0]
);
/* Instance template for module mcntrl_linear_rw */
mcntrl_linear_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER),
......@@ -679,7 +655,7 @@ module mcntrl393 #(
.xfer_col (lin_rd_chn2_col), // output[6:0]
.xfer_num128 (lin_rd_chn2_num128), // output[5:0]
.xfer_done (seq_done2), // input: sequence over
.xfer_page (xfer_page2) // output[1:0]
.xfer_reset_page (xfer_reset_page2_pos) // output
);
/* Instance template for module mcntrl_linear_rw */
......@@ -722,7 +698,8 @@ module mcntrl393 #(
.xfer_col (lin_wr_chn3_col), // output[6:0]
.xfer_num128 (lin_wr_chn3_num128), // output[5:0]
.xfer_done (seq_done3), // input : sequence over
.xfer_page (xfer_page3) // output[1:0]
// .xfer_page (xfer_page3) // output[1:0]
.xfer_reset_page (xfer_reset_page3) // output
);
/* Instance template for module cmd_encod_linear_mux */
......@@ -827,15 +804,15 @@ module mcntrl393 #(
.seq_set0 (seq_set0), // output
.seq_done0 (seq_done0), // input
.buf_wr_chn0 (buf_wr_chn0), // input @negedge mclk
.buf_waddr_rst_chn0 (buf_waddr_rst_chn0), // input @negedge mclk
.buf_wpage_nxt_chn0 (buf_wpage_nxt_chn0), // input @negedge mclk
.buf_wdata_chn0 (buf_wdata_chn0), // input[63:0]@negedge mclk
.want_rq1 (want_rq1), // output reg
.need_rq1 (need_rq1), // output reg
.channel_pgm_en1 (channel_pgm_en1), // input
.seq_done1 (seq_done1), // input
.rpage_nxt_chn1 (rpage_nxt_chn1), // input
.buf_rd_chn1 (buf_rd_chn1), // input
.buf_raddr_rst_chn1 (buf_raddr_rst_chn1), // input
.buf_rdata_chn1 (buf_rdata_chn1) // output[63:0]
);
......@@ -932,8 +909,9 @@ module mcntrl393 #(
.seq_wr0 (1'b0), // not used: seq_wr0), // input
.seq_set0 (seq_set0), // input
.seq_done0 (seq_done0), // output
.rpage_nxt_chn0 (), //rpage_nxt_chn0), not used
.buf_wr_chn0 (buf_wr_chn0), // output
.buf_waddr_rst_chn0 (buf_waddr_rst_chn0), // output
.buf_wpage_nxt_chn0 (buf_wpage_nxt_chn0), // output
// .buf_waddr_chn0 (buf_waddr_chn0), // output[6:0]
.buf_wdata_chn0 (buf_wdata_chn0), // output[63:0]
......@@ -944,9 +922,8 @@ module mcntrl393 #(
.seq_wr1 (1'b0), // not used: seq_wr1), // input
.seq_set1 (1'b0), // not used: seq_set1), // input
.seq_done1 (seq_done1), // output
.rpage_nxt_chn1 (rpage_nxt_chn1), // output
.buf_rd_chn1 (buf_rd_chn1), // output
.buf_raddr_rst_chn1 (buf_raddr_rst_chn1), // output
// .buf_raddr_chn1 (buf_raddr_chn1), // output[6:0]
.buf_rdata_chn1 (buf_rdata_chn1), // input[63:0]
.want_rq2 (want_rq2), // input
......@@ -956,9 +933,9 @@ module mcntrl393 #(
.seq_wr2 (seq_wr2x), // input
.seq_set2 (seq_set2x), // input
.seq_done2 (seq_done2), // output
.rpage_nxt_chn2 (), // not used rpage_nxt_chn2), // output
.buf_wr_chn2 (buf_wr_chn2), // output
.buf_waddr_rst_chn2 (buf_waddr_rst_chn2), // output
// .buf_waddr_chn2 (buf_waddr_chn2), // output[6:0]
.buf_wpage_nxt_chn2 (buf_wpage_nxt_chn2), // output
.buf_wdata_chn2 (buf_wdata_chn2), // output[63:0]
.want_rq3 (want_rq3), // input
......@@ -968,9 +945,8 @@ module mcntrl393 #(
.seq_wr3 (seq_wr3x), // input
.seq_set3 (seq_set3x), // input
.seq_done3 (seq_done3), // output
.rpage_nxt_chn3 (rpage_nxt_chn3), // output
.buf_rd_chn3 (buf_rd_chn3), // output
.buf_raddr_rst_chn3 (buf_raddr_rst_chn3), // output
// .buf_raddr_chn3 (buf_raddr_chn3), // output[6:0]
.buf_rdata_chn3 (buf_rdata_chn3), // input[63:0]
.want_rq4 (want_rq4), // input
......@@ -980,9 +956,9 @@ module mcntrl393 #(
.seq_wr4 (seq_wr4), // input
.seq_set4 (seq_set4), // input
.seq_done4 (seq_done4), // output
.rpage_nxt_chn4 (rpage_nxt_chn4), // output
.buf_wr_chn4 (buf_wr_chn4), // output
.buf_waddr_rst_chn4 (buf_waddr_rst_chn4), // output
// .buf_waddr_chn4 (buf_waddr_chn4), // output[6:0]
.buf_wpage_nxt_chn4 (buf_wpage_nxt_chn4), // output
.buf_wdata_chn4 (buf_wdata_chn4), // output[63:0]
.SDRST (SDRST), // output
......
memctrl/mcntrl_1kx32r.v
View file @ ecd4a509
......@@ -29,20 +29,23 @@ module mcntrl_1kx32r(
output [31:0] ext_data_out, // data out
input wclk, // !mclk (inverted)
input [1:0] wpage, // will register to wclk, input OK with mclk
input waddr_reset, // reset write buffer address (to page start), sync to wclk (!mclk)
input skip_reset, // ignore waddr_reset (resync to wclk)
input [1:0] wpage_in, // will register to wclk, input OK with mclk
input wpage_set, // set internal read page to rpage_in
input page_next, // advance to next page (and reset lower bits to 0)
output [1:0] page, // current inernal page
input we, // write port enable (also increment write buffer address)
input [63:0] data_in // data in
);
reg [1:0] wpage_wclk;
reg skip_reset_wclk;
reg [1:0] page_r;
reg [6:0] waddr;
assign page=page_r;
always @ (posedge wclk) begin
wpage_wclk <= wpage;
skip_reset_wclk <= skip_reset;
if (waddr_reset && !skip_reset_wclk) waddr <= 0;
else if (we) waddr <= waddr +1;
if (wpage_set) page_r <= wpage_in;
else if (page_next) page_r <= page_r+1;
if (page_next) waddr <= 0;
else if (we) waddr <= waddr+1;
end
ram_512x64w_1kx32r #(
.REGISTERS(1)
......@@ -53,7 +56,7 @@ module mcntrl_1kx32r(
.regen (ext_regen), // input
.data_out (ext_data_out), // output[31:0]
.wclk (wclk), // input - OK, negedge mclk
.waddr ({wpage_wclk,waddr}), // input[8:0] @negedge mclk
.waddr ({page,waddr}), // input[8:0] @negedge mclk
.we (we), // input @negedge mclk
.web (8'hff), // input[7:0]
.data_in (data_in) // input[63:0] @negedge mclk
......
memctrl/mcntrl_1kx32w.v
View file @ ecd4a509
......@@ -25,32 +25,35 @@ module mcntrl_1kx32w(
input ext_clk,
input [ 9:0] ext_waddr, // external write address
input ext_we, // external write enable
input [31:0] ext_data_in, // data input
input [31:0] ext_data_in, // data input
input rclk, // mclk
input [1:0] rpage, // will register to wclk, input OK with mclk
input raddr_reset, // reset buffer read address (to page start)
input skip_reset, // ignore waddr_reset (resync to wclk)
input [1:0] rpage_in, // will register to wclk, input OK with mclk
input rpage_set, // set internal read page to rpage_in
input page_next, // advance to next page (and reset lower bits to 0)
output [1:0] page, // current inernal page
input rd, // read buffer tomemory, increment read address (regester enable will be delayed)
output [63:0] data_out // data out
);
reg skip_reset_rclk;
reg [1:0] page_r;
reg [6:0] raddr;
reg regen;
assign page=page_r;
always @ (posedge rclk) begin
regen <= rd;
skip_reset_rclk <= skip_reset;
if (raddr_reset && !skip_reset_rclk) raddr <= 0;
else if (rd) raddr <= raddr +1;
if (rpage_set) page_r <= rpage_in;
else if (page_next) page_r <= page_r+1;
if (page_next) raddr <= 0;
else if (rd) raddr <= raddr+1;
end
ram_1kx32w_512x64r #(
.REGISTERS(1)
)ram_1kx32w_512x64r_i (
.rclk (rclk), // input
.raddr ({rpage,raddr}), // input[8:0]
.raddr ({page_r,raddr}), // input[8:0]
.ren (rd), // input
.regen (regen), // input
.data_out (data_out), // output[63:0]
......@@ -60,7 +63,5 @@ module mcntrl_1kx32w(
.web (4'hf), // input[3:0]
.data_in (ext_data_in) // input[31:0]
);
endmodule
memctrl/mcntrl_linear_rw.v
View file @ ecd4a509
......@@ -71,7 +71,8 @@ module mcntrl_linear_rw #(
output [COLADDR_NUMBER-4:0] xfer_col, // start memory column in 8-bursts
output [NUM_XFER_BITS-1:0] xfer_num128, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
input xfer_done, // transfer to/from the buffer finished
output [1:0] xfer_page // page number for transfer (goes to channel buffer memory-side adderss)
output xfer_reset_page // reset internal buffer page to zero
// output [1:0] xfer_page // page number for transfer (goes to channel buffer memory-side adderss)
);
localparam NUM_RC_BURST_BITS=ADDRESS_NUMBER+COLADDR_NUMBER-3; //to spcify row and col8 == 22
......@@ -102,7 +103,8 @@ module mcntrl_linear_rw #(
wire calc_valid; // calculated registers have valid values
wire chn_en; // enable requests by channle (continue ones in progress)
wire chn_rst; // resets command, including fifo;
reg [1:0] xfer_page_r;
// reg [1:0] xfer_page_r;
reg xfer_reset_page_r;
reg [2:0] page_cntr;
wire cmd_wrmem; // 0: read from memory, 1:write to memory
......@@ -197,7 +199,8 @@ module mcntrl_linear_rw #(
assign xfer_num128= xfer_num128_r[NUM_XFER_BITS-1:0];
assign xfer_start= xfer_start_r[0];
assign calc_valid= par_mod_r[PAR_MOD_LATENCY-1]; // MSB, longest 0
assign xfer_page= xfer_page_r;
// assign xfer_page= xfer_page_r;
assign xfer_reset_page = xfer_reset_page_r;
assign frame_done= frame_done_r;
assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend;
assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r});
......@@ -268,10 +271,15 @@ module mcntrl_linear_rw #(
else if ( xfer_start_r[0] && !next_page) page_cntr <= page_cntr + 1;
else if (!xfer_start_r[0] && next_page) page_cntr <= page_cntr - 1;
/*
if (rst) xfer_page_r <= 0;
// else if (chn_rst || frame_start) xfer_page_r <= 0; // TODO: Check if it is better to keep xfer_page_r on frame start?
else if (chn_rst ) xfer_page_r <= 0; // TODO: Check if it is better to reset xfer_page_r on frame start? to zero?
else if (xfer_done) xfer_page_r <= xfer_page_r+1;
*/
// xfer_reset_page_r <= chn_rst || frame_start ; // TODO: Check if it is better to reset page on frame start?
xfer_reset_page_r <= chn_rst; // || frame_start ; // TODO: Check if it is better to reset page on frame start?
// increment x,y (two cycles)
if (rst) curr_x <= 0;
......
memctrl/mcntrl_ps_pio.v
View file @ ecd4a509
......@@ -61,8 +61,8 @@ module mcntrl_ps_pio#(
output seq_set0,
input seq_done0,
input buf_wr_chn0,
input buf_waddr_rst_chn0,
// input [6:0] buf_waddr_chn0,
input buf_wpage_nxt_chn0,
// input buf_waddr_rst_chn0,
input [63:0] buf_wdata_chn0,
// write port 1
output reg want_rq1,
......@@ -72,9 +72,9 @@ module mcntrl_ps_pio#(
// output seq_wr1, // never generated
// output seq_set1, // connect externally to seq_set0
input seq_done1,
input rpage_nxt_chn1,
input buf_rd_chn1,
input buf_raddr_rst_chn1,
// input [6:0] buf_raddr_chn1,
// input buf_raddr_rst_chn1,
output [63:0] buf_rdata_chn1
);
localparam CMD_WIDTH=14;
......@@ -106,6 +106,9 @@ module mcntrl_ps_pio#(
wire busy;
wire start;
reg [1:0] page;
reg [1:0] page_neg;
reg [1:0] cmd_set_d;
reg cmd_set_d_neg;
// reg chn_run; // running memory access to channel 0/1
// command bit fields
wire [9:0] cmd_seq_a= cmd_out[9:0];
......@@ -157,9 +160,18 @@ module mcntrl_ps_pio#(
if (rst) page <= 0;
else if (cmd_set) page <= cmd_page;
if (rst) cmd_set_d <= 0;
else cmd_set_d <= {cmd_set_d[0],cmd_set};
end
always @ (posedge rst or negedge mclk) begin
if (rst) page_neg <= 0;
else if (cmd_set) page_neg <= page;
if (rst) cmd_set_d_neg <= 0;
else cmd_set_d_neg <= cmd_set_d[1];
end
cmd_deser #(
.ADDR (MCNTRL_PS_ADDR),
.ADDR_MASK (MCNTRL_PS_MASK),
......@@ -214,24 +226,7 @@ fifo_same_clock #(
);
// Port 0 (read DDR to AXI) buffer
/*
ram_512x64w_1kx32r #(
.REGISTERS(1)
) port0_buf_i (
.rclk (port0_clk), // input
.raddr (port0_addr), // input[9:0]
.ren (port0_re), // input
.regen (port0_regen), // input
.data_out (port0_data), // output[31:0]
.wclk (!mclk), // input
.waddr ({page,buf_waddr_chn0}), // input[8:0]
.we (buf_wr_chn0), // input
.web (8'hff), // input[7:0]
.data_in (buf_wdata_chn0) // input[63:0]
);
*/
mcntrl_1kx32r chn0_buf_i (
.ext_clk (port0_clk), // input
.ext_raddr (port0_addr), // input[9:0]
......@@ -239,41 +234,27 @@ fifo_same_clock #(
.ext_regen (port0_regen), // input
.ext_data_out (port0_data), // output[31:0]
.wclk (!mclk), // input
.wpage (page), // input[1:0]
.waddr_reset (buf_waddr_rst_chn0), // input
.skip_reset (1'b0), // input
.wpage_in (page_neg), // input[1:0]
.wpage_set (cmd_set_d_neg), // input
.page_next (buf_wpage_nxt_chn0), // input
.page (), // output[1:0]
.we (buf_wr_chn0), // input
.data_in (buf_wdata_chn0) // input[63:0]
);
// Port 1 (write DDR from AXI) buffer
/*
ram_1kx32w_512x64r #(
.REGISTERS(1)
) port1_buf_i (
.rclk (mclk), // input
.raddr ({page,buf_raddr_chn1}), // input[8:0]
.ren (buf_rd_chn1), // input
.regen (buf_rd_chn1), // input
.data_out (buf_rdata_chn1), // output[63:0]
.wclk (port1_clk), // input
.waddr (port1_addr), // input[9:0]
.we (port1_we), // input
.web (4'hf), // input[3:0]
.data_in (port1_data) // input[31:0]
);
*/
mcntrl_1kx32w chn1_buf_i (
.ext_clk (port1_clk), // input
.ext_waddr (port1_addr), // input[9:0]
.ext_we (port1_we), // input
.ext_data_in (port1_data), // input[31:0] buf_wdata - from AXI
.rclk (mclk), // input
.rpage (page), // input[1:0]
.raddr_reset (buf_raddr_rst_chn1), // input
.skip_reset (1'b0), // input
.rd (buf_rd_chn1), // input
.data_out (buf_rdata_chn1) // output[63:0]
.ext_clk (port1_clk), // input
.ext_waddr (port1_addr), // input[9:0]
.ext_we (port1_we), // input
.ext_data_in (port1_data), // input[31:0] buf_wdata - from AXI
.rclk (mclk), // input
.rpage_in (page), // input[1:0]
.rpage_set (cmd_set_d[0]), // input
.page_next (rpage_nxt_chn1), // input
.page (), // output[1:0]
.rd (buf_rd_chn1), // input
.data_out (buf_rdata_chn1) // output[63:0]
);
......
memctrl/mcntrl_tiled_rw.v
View file @ ecd4a509
......@@ -27,6 +27,8 @@ module mcntrl_tiled_rw#(
parameter NUM_XFER_BITS= 6, // number of bits to specify transfer length
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64)
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter MCNTRL_TILED_ADDR= 'h120,
parameter MCNTRL_TILED_MASK= 'h3f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {extra_pages[1:0],write_mode,enable,!reset}
......@@ -39,7 +41,7 @@ module mcntrl_tiled_rw#(
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (fro debugging)?
parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (
parameter MCNTRL_TILED_TILE_WH= 'h7, // low word - 6-bit tile width in 8-bursts, high - tile height (0 - > 64)
parameter MCNTRL_TILED_STATUS_REG_ADDR= 'h5,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2 // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
......@@ -70,15 +72,18 @@ module mcntrl_tiled_rw#(
output [2:0] xfer_bank, // start bank address
output [ADDRESS_NUMBER-1:0] xfer_row, // memory row
output [COLADDR_NUMBER-4:0] xfer_col, // start memory column in 8-bursts
output [FRAME_WIDTH_BITS:0] rowcol_inc, // increment row+col (after bank) for the new scan line in 8-bursts (externally pad with 0)
// output [NUM_XFER_BITS-1:0] xfer_num128, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
output [5:0] num_rows_m1, // number of rows to read minus 1
output [5:0] num_cols_m1, // number of 16-pixel columns to read (rows first, then columns) - 1
output [MAX_TILE_WIDTH-1:0] num_rows_m1, // number of rows to read minus 1
output [MAX_TILE_HEIGHT-1:0] num_cols_m1, // number of 16-pixel columns to read (rows first, then columns) - 1
output keep_open, // (programmable bit)keep banks open (for <=8 banks only
input xfer_done, // transfer to/from the buffer finished
output [1:0] xfer_page // page number for transfer (goes to channel buffer memory-side adderss)
input xfer_buf_rst_negedge, // @negedge mclk!!! (if heppanes before xfer_done, page done, if not - continues
output [1:0] xfer_page, // page number for transfer (goes to channel buffer memory-side address)
output buf_skip_reset // do not reset buffer counter (in split tiles)
);
//MAX_TILE_WIDTH
localparam NUM_RC_BURST_BITS=ADDRESS_NUMBER+COLADDR_NUMBER-3; //to spcify row and col8 == 22
localparam MPY_WIDTH= NUM_RC_BURST_BITS; // 22
localparam PAR_MOD_LATENCY= 7; // TODO: Find actual worst-case latency for:
......@@ -99,14 +104,20 @@ module mcntrl_tiled_rw#(
reg [FRAME_WIDTH_BITS:0] row_left; // number of 8-bursts left in the current row
reg last_in_row;
reg [COLADDR_NUMBER-3:0] mem_page_left; // number of 8-bursts left in the pointed memory page
reg [NUM_XFER_BITS:0] lim_by_xfer; // number of bursts left limited by the longest transfer (currently 64)
reg [NUM_XFER_BITS:0] xfer_num128_r; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8
reg [MAX_TILE_WIDTH:0] lim_by_tile_width; // number of bursts left limited by the longest transfer (currently 64)
// reg [MAX_TILE_WIDTH:0] remainder_tile_width; // number of bursts postponed to the next partial tile (because of the page crossing)
wire [COLADDR_NUMBER-3:0] remainder_tile_width; // number of bursts postponed to the next partial tile (because of the page crossing) MSB-sign
reg continued_tile; // this is a continued tile (caused by page crossing) - only once
reg [MAX_TILE_WIDTH-1:0] leftower_cols; // valid with continued_tile, number of columns left
// reg [NUM_XFER_BITS:0] xfer_num128_r; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8
wire pgm_param_w; // program one of the parameters, invalidate calculated results for PAR_MOD_LATENCY
reg [2:0] xfer_start_r;
reg [PAR_MOD_LATENCY-1:0] par_mod_r;
reg [PAR_MOD_LATENCY-1:0] par_mod_r;
reg [PAR_MOD_LATENCY-1:0] recalc_r; // 1-hot CE for re-calculating registers
wire calc_valid; // calculated registers have valid values
wire chn_en; // enable requests by channle (continue ones in progress)
wire chn_rst; // resets command, including fifo;
reg chn_rst_d; // delayed by 1 cycle do detect turning off
reg [1:0] xfer_page_r;
reg [2:0] page_cntr;
......@@ -135,15 +146,26 @@ module mcntrl_tiled_rw#(
wire set_window_wh_w;
wire set_window_x0y0_w;
wire set_window_start_w;
wire lsw13_zero=!cmd_data[FRAME_WIDTH_BITS-1:0]; // LSW 13 (FRAME_WIDTH_BITS) low bits are all 0 - set carry bit
wire msw13_zero=!cmd_data[FRAME_WIDTH_BITS+15:16]; // MSW 13 (FRAME_WIDTH_BITS) low bits are all 0 - set carry bit
wire msw_zero= !cmd_data[31:16]; // MSW all bits are 0 - set carry bit
wire set_tile_wh_w;
wire lsw13_zero=!(|cmd_data[FRAME_WIDTH_BITS-1:0]); // LSW 13 (FRAME_WIDTH_BITS) low bits are all 0 - set carry bit
wire msw13_zero=!(|cmd_data[FRAME_WIDTH_BITS+15:16]); // MSW 13 (FRAME_WIDTH_BITS) low bits are all 0 - set carry bit
wire msw_zero= !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit
wire tile_width_zero= !(|cmd_data[MAX_TILE_WIDTH-1:0]);
wire tile_height_zero=!(|cmd_data[MAX_TILE_HEIGHT+15:16]);
reg [1:0] buf_rst_posedge;
reg [5:0] mode_reg;//mode register: {keep_open,extra_pages[1:0],write_mode,enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_addr; // (programmed) Frame start (in {row,col8} in burst8, bank ==0
// reg [FRAME_WIDTH_BITS:0] frame_width; // (programmed) 0- max
reg [MAX_TILE_WIDTH:0] tile_cols; // full number of columns in a tile
reg [MAX_TILE_HEIGHT:0] tile_rows; // full number of rows in a tile
reg [MAX_TILE_WIDTH:0] num_cols_r; // full number of columns to transfer (not minus 1)
// reg [MAX_TILE_HEIGHT:0] num_rows_r; // full number of rows to transfer (not minus 1)
wire [MAX_TILE_WIDTH:0] num_cols_m1_w; // full number of columns to transfer minus 1 with extra bit
wire [MAX_TILE_HEIGHT:0] num_rows_m1_w; // full number of columns to transfer minus 1 with extra bit
// reg buf_skip_reset_r;
//FIXME!!!!!!!!
reg [FRAME_WIDTH_BITS:0] frame_full_width; // (programmed) increment combined row/col when moving to the next line
// frame_width rounded up to max transfer (half page) if frame_width> max transfer/2,
......@@ -163,6 +185,8 @@ module mcntrl_tiled_rw#(
assign set_window_wh_w = cmd_we && (cmd_a== MCNTRL_TILED_WINDOW_WH);
assign set_window_x0y0_w = cmd_we && (cmd_a== MCNTRL_TILED_WINDOW_X0Y0);
assign set_window_start_w = cmd_we && (cmd_a== MCNTRL_TILED_WINDOW_STARTXY);
assign set_tile_wh_w = cmd_we && (cmd_a== MCNTRL_TILED_TILE_WH);
//
// Sett parameter registers
always @(posedge rst or posedge mclk) begin
if (rst) mode_reg <= 0;
......@@ -174,7 +198,7 @@ module mcntrl_tiled_rw#(
if (rst) frame_full_width <= 0;
else if (set_frame_width_w) frame_full_width <= {msw13_zero,cmd_data[FRAME_WIDTH_BITS-1:0]};
if (rst) begin
if (rst) begin
window_width <= 0;
window_height <= 0;
end else if (set_window_wh_w) begin
......@@ -182,7 +206,15 @@ module mcntrl_tiled_rw#(
window_height <= {msw_zero,cmd_data[FRAME_HEIGHT_BITS+15:16]};
end
if (rst) begin
if (rst) begin
tile_cols <= 0;
tile_rows <= 0;
end else if (set_tile_wh_w) begin
tile_cols <= {tile_width_zero, cmd_data[MAX_TILE_WIDTH-1:0]};
tile_rows <= {tile_height_zero, cmd_data[MAX_TILE_HEIGHT+15:16]};
end
if (rst) begin
window_x0 <= 0;
window_y0 <= 0;
end else if (set_window_x0y0_w) begin
......@@ -190,23 +222,27 @@ module mcntrl_tiled_rw#(
window_y0 <=cmd_data[FRAME_HEIGHT_BITS+15:16];
end
if (rst) begin
if (rst) begin
start_x <= 0;
start_y <= 0;
end else if (set_window_start_w) begin
start_x <= cmd_data[FRAME_WIDTH_BITS-1:0];
start_y <=cmd_data[FRAME_HEIGHT_BITS+15:16];
end
if (rst) buf_rst_posedge<=0;
else buf_rst_posedge <={buf_rst_posedge[0],xfer_buf_rst_negedge};
end
assign mul_rslt_w= frame_y8_r * frame_full_width_r; // 5 MSBs will be discarded
assign xfer_num128= xfer_num128_r[NUM_XFER_BITS-1:0];
// assign xfer_num128= xfer_num128_r[NUM_XFER_BITS-1:0];
assign xfer_start= xfer_start_r[0];
assign calc_valid= par_mod_r[PAR_MOD_LATENCY-1]; // MSB, longest 0
assign xfer_page= xfer_page_r;
assign frame_done= frame_done_r;
assign pre_want= chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend;
assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r});
assign last_row_w= next_y==window_height;
assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},num_cols_r}); // what if it crosses page? OK, num_cols_r & row_left know that
assign last_row_w= next_y>=window_height; // (next_y==window_height) is faster, but will not forgive software errors
assign xfer_want= want_r;
assign xfer_need= need_r;
assign xfer_bank= bank_reg[2]; // TODO: just a single reg layer
......@@ -217,29 +253,64 @@ module mcntrl_tiled_rw#(
assign chn_rst = ~mode_reg[0]; // resets command, including fifo;
assign cmd_wrmem = mode_reg[2];// 0: read from memory, 1:write to memory
assign cmd_extra_pages = mode_reg[4:3]; // external module needs more than 1 page
assign keep_open= mode_reg[4:3]; // keep banks open (will be used only if number of rows <= 8
assign keep_open= mode_reg[5]; // keep banks open (will be used only if number of rows <= 8
assign status_data= {1'b0, busy_r}; // TODO: Add second bit?
assign pgm_param_w= cmd_we;
assign rowcol_inc= frame_full_width;
assign num_cols_m1_w= num_cols_r-1;
assign num_rows_m1_w= tile_rows-1; // now number of rows == tile height
assign num_cols_m1= num_cols_m1_w[MAX_TILE_WIDTH-1:0]; // remove MSB
assign num_rows_m1= num_rows_m1_w[MAX_TILE_HEIGHT-1:0]; // remove MSB
assign remainder_tile_width = {EXTRA_BITS,lim_by_tile_width}-mem_page_left;
assign buf_skip_reset= continued_tile; // buf_skip_reset_r;
integer i;
localparam EXTRA_BITS={COLADDR_NUMBER-3-COLADDR_NUMBER-3{1'b0}};
// localparam EXTRA_BITS={COLADDR_NUMBER-3-NUM_XFER_BITS{1'b0}};
localparam [COLADDR_NUMBER-3-MAX_TILE_WIDTH-1:0] EXTRA_BITS=0;
wire xfer_limited_by_mem_page;
reg xfer_limited_by_mem_page_r;
assign xfer_limited_by_mem_page= mem_page_left < {EXTRA_BITS,lim_by_tile_width};
always @(posedge mclk) begin // TODO: Match latencies (is it needed?) Reduce consumption by CE?
frame_x <= curr_x + window_x0;
frame_y <= curr_y + window_y0;
next_y <= curr_y + 1;
row_left <= window_width - curr_x; // 14 bits - 13 bits
mem_page_left <= (1 << (COLADDR_NUMBER-3)) - frame_x[COLADDR_NUMBER-4:0];
lim_by_xfer <= (|row_left[FRAME_WIDTH_BITS:NUM_XFER_BITS])?(1<<NUM_XFER_BITS):row_left[NUM_XFER_BITS:0]; // 7 bits, max 'h40
xfer_num128_r<= (mem_page_left> {{EXTRA_BITS{1'b0}},lim_by_xfer})? mem_page_left[NUM_XFER_BITS:0]:lim_by_xfer[NUM_XFER_BITS:0];
// cycle 1
if (recalc_r[0]) begin
frame_x <= curr_x + window_x0;
frame_y <= curr_y + window_y0;
next_y <= curr_y + tile_rows;
row_left <= window_width - curr_x; // 14 bits - 13 bits
end
// cycle 2
if (recalc_r[1]) begin
mem_page_left <= (1 << (COLADDR_NUMBER-3)) - frame_x[COLADDR_NUMBER-4:0];
// lim_by_tile_width <= (|row_left[FRAME_WIDTH_BITS:MAX_TILE_WIDTH])?(1<<MAX_TILE_WIDTH):row_left[MAX_TILE_WIDTH:0]; // 7 bits, max 'h40
lim_by_tile_width <= (|row_left[FRAME_WIDTH_BITS:MAX_TILE_WIDTH] || (row_left[MAX_TILE_WIDTH:0]>= tile_cols))?
tile_cols:
row_left[MAX_TILE_WIDTH:0]; // 7 bits, max 'h40
end
// cycle 3
if (recalc_r[2]) begin
xfer_limited_by_mem_page_r <= xfer_limited_by_mem_page && !continued_tile;
num_cols_r<= continued_tile?
{EXTRA_BITS,leftower_cols}:
(xfer_limited_by_mem_page? mem_page_left[MAX_TILE_WIDTH:0]:lim_by_tile_width[MAX_TILE_WIDTH:0]);
leftower_cols <= remainder_tile_width[MAX_TILE_WIDTH-1:0];
// remainder_tile_width <= {EXTRA_BITS,lim_by_tile_width}-mem_page_left;
end
// VDT bug? next line gives a warning
// xfer_num128_r<= (mem_page_left> {{COLADDR_NUMBER-3-COLADDR_NUMBER-3{1'b0}},lim_by_xfer})?mem_page_left[NUM_XFER_BITS-1:0]:lim_by_xfer[NUM_XFER_BITS-1:0];
last_in_row <= last_in_row_w;
frame_y8_r <= frame_y[FRAME_HEIGHT_BITS-1:3]; // lat=2
frame_full_width_r <= frame_full_width;
start_addr_r <= start_addr;
mul_rslt <= mul_rslt_w[MPY_WIDTH-1:0]; // frame_y8_r * frame_width_r; // 7 bits will be discarded lat=3;
line_start_addr <= start_addr_r+mul_rslt; // lat=4
row_col_r <= line_start_addr+frame_x;
// cycle 4
if (recalc_r[3]) begin
last_in_row <= last_in_row_w;
end
// registers to be absorbed in DSP block
frame_y8_r <= frame_y[FRAME_HEIGHT_BITS-1:3]; // lat=2 // if (recalc_r[2]) begin
frame_full_width_r <= frame_full_width; //(cycle 2) // if (recalc_r[2]) begin
start_addr_r <= start_addr; // // if (recalc_r[2]) begin
mul_rslt <= mul_rslt_w[MPY_WIDTH-1:0]; // frame_y8_r * frame_width_r; // 7 bits will be discarded lat=3; if (recalc_r[3]) begin
line_start_addr <= start_addr_r+mul_rslt; // lat=4 if (recalc_r[4]) begin
// TODO: Verify MPY/register timing above
if (recalc_r[5]) begin
row_col_r <= line_start_addr+frame_x;
end
bank_reg[0] <= frame_y[2:0]; //TODO: is it needed - a pipeline for the bank? - remove!
for (i=0;i<2; i = i+1)
bank_reg[i+1] <= bank_reg[i];
......@@ -252,6 +323,13 @@ module mcntrl_tiled_rw#(
if (rst) par_mod_r<=0;
else if (pgm_param_w || xfer_start_r[0] || chn_rst) par_mod_r<=0;
else par_mod_r <= {par_mod_r[PAR_MOD_LATENCY-2:0], 1'b1};
if (rst) chn_rst_d <= 0;
else chn_rst_d <= chn_rst;
if (rst) recalc_r<=0;
else if (chn_rst) recalc_r<=0;
else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0], (xfer_grant & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)};
if (rst) busy_r <= 0;
else if (chn_rst) busy_r <= 0;
......@@ -261,6 +339,11 @@ module mcntrl_tiled_rw#(
if (rst) xfer_start_r <= 0;
else xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};
if (rst) continued_tile <= 1'b0;
else if (chn_rst) continued_tile <= 1'b0;
else if (frame_start) continued_tile <= 1'b0;
else if (xfer_start_r[0]) continued_tile <= xfer_limited_by_mem_page_r; // only set after actual start if it was partial, not after parameter change
if (rst) need_r <= 0;
else if (chn_rst || xfer_grant) need_r <= 0;
else if (pre_want && (page_cntr>=3)) need_r <= 1;
......@@ -282,7 +365,7 @@ module mcntrl_tiled_rw#(
// increment x,y (two cycles)
if (rst) curr_x <= 0;
else if (chn_rst || frame_start) curr_x <= start_x;
else if (xfer_start_r[0]) curr_x <= last_in_row?0: curr_x + xfer_num128_r;
else if (xfer_start_r[0]) curr_x <= last_in_row?0: curr_x + num_cols_r;
if (rst) curr_y <= 0;
else if (chn_rst || frame_start) curr_y <= start_y;
......
memctrl/memctrl16.v
View file @ ecd4a509
......@@ -163,13 +163,13 @@ module memctrl16 #(
input seq_wr0, // strobe for writing sequencer data (address is autoincremented)
input seq_set0, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done0, // sequencer finished executing sequence for this channel
output rpage_nxt_chn0,
`ifdef def_read_mem_chn0
output buf_wr_chn0, // @ negedge mclk
output buf_waddr_rst_chn0, // @ negedge mclk
output buf_wpage_nxt_chn0, // @ negedge mclk
output [63:0] buf_wdata_chn0, // @ negedge mclk
`else
output buf_rd_chn0,
output buf_raddr_rst_chn0,
input [63:0] buf_rdata_chn0,
`endif
`endif
......@@ -183,13 +183,13 @@ module memctrl16 #(
input seq_wr1, // strobe for writing sequencer data (address is autoincremented)
input seq_set1, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done1, // sequencer finished executing sequence for this channel
output rpage_nxt_chn1,
`ifdef def_read_mem_chn1
output buf_wr_chn1, // @ negedge mclk
output buf_waddr_rst_chn1,// @ negedge mclk
output buf_wpage_nxt_chn1,// @ negedge mclk
output [63:0] buf_wdata_chn1,// @ negedge mclk
`else
output buf_rd_chn1,
output buf_raddr_rst_chn1,
input [63:0] buf_rdata_chn1,
`endif
`endif
......@@ -203,13 +203,13 @@ module memctrl16 #(
input seq_wr2, // strobe for writing sequencer data (address is autoincremented)
input seq_set2, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done2, // sequencer finished executing sequence for this channel
output rpage_nxt_chn2,
`ifdef def_read_mem_chn2
output buf_wr_chn2,
output buf_waddr_rst_chn2,
output buf_wpage_nxt_chn2,
output [63:0] buf_wdata_chn2,
`else
output buf_rd_chn2,
output buf_raddr_rst_chn2,
input [63:0] buf_rdata_chn2,
`endif
`endif
......@@ -223,13 +223,13 @@ module memctrl16 #(
input seq_wr3, // strobe for writing sequencer data (address is autoincremented)
input seq_set3, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done3, // sequencer finished executing sequence for this channel
output rpage_nxt_chn3,
`ifdef def_read_mem_chn3
output buf_wr_chn3,
output buf_waddr_rst_chn3,
output buf_wpage_nxt_chn3,
output [63:0] buf_wdata_chn3,
`else
output buf_rd_chn3,
output buf_raddr_rst_chn3,
input [63:0] buf_rdata_chn3,
`endif
`endif
......@@ -243,13 +243,13 @@ module memctrl16 #(
input seq_wr4, // strobe for writing sequencer data (address is autoincremented)
input seq_set4, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done4, // sequencer finished executing sequence for this channel
output rpage_nxt_chn4,
`ifdef def_read_mem_chn4
output buf_wr_chn4, // @ negedge mclk
output buf_waddr_rst_chn4, // @ negedge mclk
output buf_wpage_nxt_chn4, // @ negedge mclk
output [63:0] buf_wdata_chn4, // @ negedge mclk
`else
output buf_rd_chn4,
output buf_raddr_rst_chn4,
input [63:0] buf_rdata_chn4,
`endif
`endif
......@@ -263,13 +263,13 @@ module memctrl16 #(
input seq_wr5, // strobe for writing sequencer data (address is autoincremented)
input seq_set5, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done5, // sequencer finished executing sequence for this channel
output rpage_nxt_chn5,
`ifdef def_read_mem_chn5
output buf_wr_chn5, // @ negedge mclk
output buf_waddr_rst_chn5, // @ negedge mclk
output buf_wpage_nxt_chn5, // @ negedge mclk
output [63:0] buf_wdata_chn5, // @ negedge mclk
`else
output buf_rd_chn5,
output buf_raddr_rst_chn5,
input [63:0] buf_rdata_chn5,
`endif
`endif
......@@ -283,13 +283,13 @@ module memctrl16 #(
input seq_wr6, // strobe for writing sequencer data (address is autoincremented)
input seq_set6, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done6, // sequencer finished executing sequence for this channel
output rpage_nxt_chn6,
`ifdef def_read_mem_chn6
output buf_wr_chn6, // @ negedge mclk
output buf_waddr_rst_chn6, // @ negedge mclk
output buf_wpage_nxt_chn6, // @ negedge mclk
output [63:0] buf_wdata_chn6, // @ negedge mclk
`else
output buf_rd_chn6,
output buf_raddr_rst_chn6,
input [63:0] buf_rdata_chn6,
`endif
`endif
......@@ -303,13 +303,13 @@ module memctrl16 #(
input seq_wr7, // strobe for writing sequencer data (address is autoincremented)
input seq_set7, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done7, // sequencer finished executing sequence for this channel
output rpage_nxt_chn7,
`ifdef def_read_mem_chn7
output buf_wr_chn7, // @ negedge mclk
output buf_waddr_rst_chn7, // @ negedge mclk
output buf_wpage_nxt_chn7, // @ negedge mclk
output [63:0] buf_wdata_chn7, // @ negedge mclk
`else
output buf_rd_chn7,
output buf_raddr_rst_chn7,
input [63:0] buf_rdata_chn7,
`endif
`endif
......@@ -323,13 +323,13 @@ module memctrl16 #(
input seq_wr8, // strobe for writing sequencer data (address is autoincremented)
input seq_set8, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done8, // sequencer finished executing sequence for this channel
output rpage_nxt_chn8,
`ifdef def_read_mem_chn8
output buf_wr_chn8, // @ negedge mclk
output buf_waddr_rst_chn8, // @ negedge mclk
output buf_wpage_nxt_chn8, // @ negedge mclk
output [63:0] buf_wdata_chn8, // @ negedge mclk
`else
output buf_rd_chn8,
output buf_raddr_rst_chn8,
input [63:0] buf_rdata_chn8,
`endif
`endif
......@@ -343,13 +343,13 @@ module memctrl16 #(
input seq_wr9, // strobe for writing sequencer data (address is autoincremented)
input seq_set9, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done9, // sequencer finished executing sequence for this channel
output rpage_nxt_chn9,
`ifdef def_read_mem_chn9
output buf_wr_chn9, // @ negedge mclk
output buf_waddr_rst_chn9, // @ negedge mclk
output buf_wpage_nxt_chn9, // @ negedge mclk
output [63:0] buf_wdata_chn9, // @ negedge mclk
`else
output buf_rd_chn9,
output buf_raddr_rst_chn9,
input [63:0] buf_rdata_chn9,
`endif
`endif
......@@ -363,13 +363,13 @@ module memctrl16 #(
input seq_wr10, // strobe for writing sequencer data (address is autoincremented)
input seq_set10, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done10, // sequencer finished executing sequence for this channel
output rpage_nxt_chn10,
`ifdef def_read_mem_chn10
output buf_wr_chn10, // @ negedge mclk
output buf_waddr_rst_chn10, // @ negedge mclk
output buf_wpage_nxt_chn10, // @ negedge mclk
output [63:0] buf_wdata_chn10, // @ negedge mclk
`else
output buf_rd_chn10,
output buf_raddr_rst_chn10,
input [63:0] buf_rdata_chn10,
`endif
`endif
......@@ -383,13 +383,13 @@ module memctrl16 #(
input seq_wr11, // strobe for writing sequencer data (address is autoincremented)
input seq_set11, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done11, // sequencer finished executing sequence for this channel
output rpage_nxt_chn11,
`ifdef def_read_mem_chn11
output buf_wr_chn11, // @ negedge mclk
output buf_waddr_rst_chn11, // @ negedge mclk
output buf_wpage_nxt_chn11, // @ negedge mclk
output [63:0] buf_wdata_chn11, // @ negedge mclk
`else
output buf_rd_chn11,
output buf_raddr_rst_chn11,
input [63:0] buf_rdata_chn11,
`endif
`endif
......@@ -403,13 +403,13 @@ module memctrl16 #(
input seq_wr12, // strobe for writing sequencer data (address is autoincremented)
input seq_set12, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done12, // sequencer finished executing sequence for this channel
output rpage_nxt_chn12,
`ifdef def_read_mem_chn12
output buf_wr_chn12, // @ negedge mclk
output buf_waddr_rst_chn12, // @ negedge mclk
output buf_wpage_nxt_chn12, // @ negedge mclk
output [63:0] buf_wdata_chn12, // @ negedge mclk
`else
output buf_rd_chn12,
output buf_raddr_rst_chn12,
input [63:0] buf_rdata_chn12,
`endif
`endif
......@@ -423,13 +423,13 @@ module memctrl16 #(
input seq_wr13, // strobe for writing sequencer data (address is autoincremented)
input seq_set13, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done13, // sequencer finished executing sequence for this channel
output rpage_nxt_chn13,
`ifdef def_read_mem_chn13
output buf_wr_chn13, // @ negedge mclk
output buf_waddr_rst_chn13, // @ negedge mclk
output buf_wpage_nxt_chn13, // @ negedge mclk
output [63:0] buf_wdata_chn13, // @ negedge mclk
`else
output buf_rd_chn13,
output buf_raddr_rst_chn13,
input [63:0] buf_rdata_chn13,
`endif
`endif
......@@ -443,13 +443,13 @@ module memctrl16 #(
input seq_wr14, // strobe for writing sequencer data (address is autoincremented)
input seq_set14, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done14, // sequencer finished executing sequence for this channel
output rpage_nxt_chn14,
`ifdef def_read_mem_chn14
output buf_wr_chn14, // @ negedge mclk
output buf_waddr_rst_chn14, // @ negedge mclk
output buf_wpage_nxt_chn14, // @ negedge mclk
output [63:0] buf_wdata_chn14, // @ negedge mclk
`else
output buf_rd_chn14,
output buf_raddr_rst_chn14,
input [63:0] buf_rdata_chn14,
`endif
`endif
......@@ -463,13 +463,13 @@ module memctrl16 #(
input seq_wr15, // strobe for writing sequencer data (address is autoincremented)
input seq_set15, // channel sequencer data is written. If no seq_wr pulses before seq_set, seq_data contains software sequencer start address
output seq_done15, // sequencer finished executing sequence for this channel
output rpage_nxt_chn15,
`ifdef def_read_mem_chn15
output buf_wr_chn15, // @ negedge mclk
output buf_waddr_rst_chn15, // @ negedge mclk
output buf_wpage_nxt_chn15, // @ negedge mclk
output [63:0] buf_wdata_chn15, // @ negedge mclk
`else
output buf_rd_chn15,
output buf_raddr_rst_chn15,
input [63:0] buf_rdata_chn15,
`endif
`endif
......@@ -507,12 +507,12 @@ module memctrl16 #(
wire rst=rst_in; // TODO: decide where toi generate
wire ext_buf_rd;
wire ext_buf_raddr_rst;
wire ext_buf_rpage_nxt;
// wire [6:0] ext_buf_raddr;
wire [3:0] ext_buf_rchn;
wire [63:0] ext_buf_rdata;
wire ext_buf_wr;
wire ext_buf_waddr_rst;
wire ext_buf_wpage_nxt;
// wire [6:0] ext_buf_waddr;
wire [3:0] ext_buf_wchn;
wire [63:0] ext_buf_wdata;
......@@ -912,12 +912,12 @@ end
.status_rq (status_rq_phy), // output
.status_start (status_start_phy), // input
.ext_buf_rd (ext_buf_rd), // output
.ext_buf_raddr_rst (ext_buf_raddr_rst), // output[6:0]
.ext_buf_rpage_nxt (ext_buf_rpage_nxt), // output[6:0]
// .ext_buf_raddr (ext_buf_raddr), // output[6:0]
.ext_buf_rchn (ext_buf_rchn), // output[3:0]
.ext_buf_rdata (ext_buf_rdata), // input[63:0]
.ext_buf_wr (ext_buf_wr), // output
.ext_buf_waddr_rst (ext_buf_waddr_rst), // output[6:0]
.ext_buf_wpage_nxt (ext_buf_wpage_nxt), // output[6:0]
// .ext_buf_waddr (ext_buf_waddr), // output[6:0]
.ext_buf_wchn (ext_buf_wchn), // output[3:0]
.ext_buf_wdata (ext_buf_wdata), // output[63:0]
......@@ -925,182 +925,197 @@ end
);
// Registering existing channel buffers I/Os
`ifdef def_enable_mem_chn0
`ifdef def_enable_mem_chn0
mcont_common_chnbuf_reg #( .CHN_NUMBER(0)) mcont_common_chnbuf_reg0_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done0),.rpage_nxt(rpage_nxt_chn0));
`ifdef def_read_mem_chn0
mcont_to_chnbuf_reg #(.CHN_NUMBER( 0)) mcont_to_chnbuf_reg0_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done0),.buf_wr_chn(buf_wr_chn0),.buf_waddr_rst_chn(buf_waddr_rst_chn0),.buf_wdata_chn(buf_wdata_chn0));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 0)) mcont_to_chnbuf_reg0_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn0),.buf_wpage_nxt_chn(buf_wpage_nxt_chn0),.buf_wdata_chn(buf_wdata_chn0));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 0),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg0_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done0),.buf_rd_chn(buf_rd_chn0),.buf_raddr_rst_chn(buf_raddr_rst_chn0),
.buf_rdata_chn (buf_rdata_chn0));
.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.buf_rd_chn(buf_rd_chn0),.buf_rdata_chn (buf_rdata_chn0));
`endif
`endif
`ifdef def_enable_mem_chn1
`ifdef def_enable_mem_chn1
mcont_common_chnbuf_reg #( .CHN_NUMBER(1)) mcont_common_chnbuf_reg1_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done1),.rpage_nxt(rpage_nxt_chn1));
`ifdef def_read_mem_chn1
mcont_to_chnbuf_reg #(.CHN_NUMBER( 1)) mcont_to_chnbuf_reg1_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done1),.buf_wr_chn(buf_wr_chn1),.buf_waddr_rst_chn(buf_waddr_rst_chn1),.buf_wdata_chn(buf_wdata_chn1));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 1)) mcont_to_chnbuf_reg1_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn1),.buf_wpage_nxt_chn(buf_wpage_nxt_chn1),.buf_wdata_chn(buf_wdata_chn1));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 1),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg1_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done1),.buf_rd_chn(buf_rd_chn1),.buf_raddr_rst_chn(buf_raddr_rst_chn1),
.buf_rdata_chn (buf_rdata_chn1));
.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.buf_rd_chn(buf_rd_chn1),.buf_rdata_chn(buf_rdata_chn1));
`endif
`endif
`ifdef def_enable_mem_chn2
`ifdef def_enable_mem_chn2
mcont_common_chnbuf_reg #( .CHN_NUMBER(2)) mcont_common_chnbuf_reg2_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done2),.rpage_nxt(rpage_nxt_chn2));
`ifdef def_read_mem_chn2
mcont_to_chnbuf_reg #(.CHN_NUMBER( 2)) mcont_to_chnbuf_reg2_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done2),.buf_wr_chn(buf_wr_chn2),.buf_waddr_rst_chn(buf_waddr_rst_chn2),.buf_wdata_chn(buf_wdata_chn2));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 2)) mcont_to_chnbuf_reg2_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn2),.buf_wpage_nxt_chn(buf_wpage_nxt_chn2),.buf_wdata_chn(buf_wdata_chn2));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 2),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg2_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done2),.buf_rd_chn(buf_rd_chn2),.buf_raddr_rst_chn(buf_raddr_rst_chn2),
.buf_rdata_chn (buf_rdata_chn2));
.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.buf_rd_chn(buf_rd_chn2),.buf_rdata_chn(buf_rdata_chn2));
`endif
`endif
`ifdef def_enable_mem_chn3
`ifdef def_enable_mem_chn3
mcont_common_chnbuf_reg #( .CHN_NUMBER(3)) mcont_common_chnbuf_reg3_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done3),.rpage_nxt(rpage_nxt_chn3));
`ifdef def_read_mem_chn3
mcont_to_chnbuf_reg #(.CHN_NUMBER( 3)) mcont_to_chnbuf_reg3_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done3),.buf_wr_chn(buf_wr_chn3),.buf_waddr_rst_chn(buf_waddr_rst_chn3),.buf_wdata_chn(buf_wdata_chn3));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 3)) mcont_to_chnbuf_reg3_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn3),.buf_wpage_nxt_chn(buf_wpage_nxt_chn3),.buf_wdata_chn(buf_wdata_chn3));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 3),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg3_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done3),.buf_rd_chn(buf_rd_chn3),.buf_raddr_rst_chn(buf_raddr_rst_chn3),
.buf_rdata_chn (buf_rdata_chn3));
.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.buf_rd_chn(buf_rd_chn3),.buf_rdata_chn(buf_rdata_chn3));
`endif
`endif
`ifdef def_enable_mem_chn4
`ifdef def_enable_mem_chn4
mcont_common_chnbuf_reg #( .CHN_NUMBER(4)) mcont_common_chnbuf_reg4_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done4),.rpage_nxt(rpage_nxt_chn4));
`ifdef def_read_mem_chn4
mcont_to_chnbuf_reg #(.CHN_NUMBER( 4)) mcont_to_chnbuf_reg4_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done4),.buf_wr_chn(buf_wr_chn4),.buf_waddr_rst_chn(buf_waddr_rst_chn4),.buf_wdata_chn(buf_wdata_chn4));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 4)) mcont_to_chnbuf_reg4_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn4),.buf_wpage_nxt_chn(buf_wpage_nxt_chn4),.buf_wdata_chn(buf_wdata_chn4));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 4),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg4_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done4),.buf_rd_chn(buf_rd_chn4),.buf_raddr_rst_chn(buf_raddr_rst_chn4),
.buf_rdata_chn (buf_rdata_chn4));
.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.buf_rd_chn(buf_rd_chn4),.buf_rdata_chn(buf_rdata_chn4));
`endif
`endif
`ifdef def_enable_mem_chn5
`ifdef def_enable_mem_chn5
mcont_common_chnbuf_reg #( .CHN_NUMBER(5)) mcont_common_chnbuf_reg5_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done5),.rpage_nxt(rpage_nxt_chn5));
`ifdef def_read_mem_chn5
mcont_to_chnbuf_reg #(.CHN_NUMBER( 5)) mcont_to_chnbuf_reg5_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done5),.buf_wr_chn(buf_wr_chn5),.buf_waddr_rst_chn(buf_waddr_rst_chn5),.buf_wdata_chn(buf_wdata_chn5));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 5)) mcont_to_chnbuf_reg5_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn5),.buf_wpage_nxt_chn(buf_wpage_nxt_chn5),.buf_wdata_chn(buf_wdata_chn5));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 5),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg5_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done5),.buf_rd_chn(buf_rd_chn5),.buf_raddr_rst_chn(buf_raddr_rst_chn5),
.buf_rdata_chn (buf_rdata_chn5));
.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.buf_rd_chn(buf_rd_chn5),.buf_rdata_chn(buf_rdata_chn5));
`endif
`endif
`ifdef def_enable_mem_chn6
`ifdef def_enable_mem_chn6
mcont_common_chnbuf_reg #( .CHN_NUMBER(6)) mcont_common_chnbuf_reg6_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done6),.rpage_nxt(rpage_nxt_chn6));
`ifdef def_read_mem_chn6
mcont_to_chnbuf_reg #(.CHN_NUMBER( 6)) mcont_to_chnbuf_reg6_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done6),.buf_wr_chn(buf_wr_chn6),.buf_waddr_rst_chn(buf_waddr_rst_chn6),.buf_wdata_chn(buf_wdata_chn6));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 6)) mcont_to_chnbuf_reg6_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn6),.buf_wpage_nxt_chn(buf_wpage_nxt_chn6),.buf_wdata_chn(buf_wdata_chn6));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 6),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg6_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done6),.buf_rd_chn(buf_rd_chn6),.buf_raddr_rst_chn(buf_raddr_rst_chn6),
.buf_rdata_chn (buf_rdata_chn6));
.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.buf_rd_chn(buf_rd_chn6),.buf_rdata_chn(buf_rdata_chn6));
`endif
`endif
`ifdef def_enable_mem_chn7
`ifdef def_enable_mem_chn7
mcont_common_chnbuf_reg #( .CHN_NUMBER(7)) mcont_common_chnbuf_reg7_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done7),.rpage_nxt(rpage_nxt_chn7));
`ifdef def_read_mem_chn7
mcont_to_chnbuf_reg #(.CHN_NUMBER( 7)) mcont_to_chnbuf_reg7_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done7),.buf_wr_chn(buf_wr_chn7),.buf_waddr_rst_chn(buf_waddr_rst_chn7),.buf_wdata_chn(buf_wdata_chn7));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 7)) mcont_to_chnbuf_reg7_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn7),.buf_wpage_nxt_chn(buf_wpage_nxt_chn7),.buf_wdata_chn(buf_wdata_chn7));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 7),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg7_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done7),.buf_rd_chn(buf_rd_chn7),.buf_raddr_rst_chn(buf_raddr_rst_chn7),
.buf_rdata_chn (buf_rdata_chn7));
.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.buf_rd_chn(buf_rd_chn7),.buf_rdata_chn(buf_rdata_chn7));
`endif
`endif
`ifdef def_enable_mem_chn8
`ifdef def_enable_mem_chn8
mcont_common_chnbuf_reg #( .CHN_NUMBER(8)) mcont_common_chnbuf_reg8_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done8),.rpage_nxt(rpage_nxt_chn8));
`ifdef def_read_mem_chn8
mcont_to_chnbuf_reg #(.CHN_NUMBER( 8)) mcont_to_chnbuf_reg8_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done8),.buf_wr_chn(buf_wr_chn8),.buf_waddr_rst_chn(buf_waddr_rst_chn8),.buf_wdata_chn(buf_wdata_chn8));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 8)) mcont_to_chnbuf_reg8_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn8),.buf_wpage_nxt_chn(buf_wpage_nxt_chn8),.buf_wdata_chn(buf_wdata_chn8));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 8),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg8_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done8),.buf_rd_chn(buf_rd_chn8),.buf_raddr_rst_chn(buf_raddr_rst_chn8),
.buf_rdata_chn (buf_rdata_chn8));
.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.buf_rd_chn(buf_rd_chn8),.buf_rdata_chn(buf_rdata_chn8));
`endif
`endif
`ifdef def_enable_mem_chn9
`ifdef def_enable_mem_chn9
mcont_common_chnbuf_reg #( .CHN_NUMBER(9)) mcont_common_chnbuf_reg9_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done9),.rpage_nxt(rpage_nxt_chn9));
`ifdef def_read_mem_chn9
mcont_to_chnbuf_reg #(.CHN_NUMBER( 9)) mcont_to_chnbuf_reg9_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done9),.buf_wr_chn(buf_wr_chn9),.buf_waddr_rst_chn(buf_waddr_rst_chn9),.buf_wdata_chn(buf_wdata_chn9));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 9)) mcont_to_chnbuf_reg9_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn9),.buf_wpage_nxt_chn(buf_wpage_nxt_chn9),.buf_wdata_chn(buf_wdata_chn9));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 9),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg9_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done9),.buf_rd_chn(buf_rd_chn9),.buf_raddr_rst_chn(buf_raddr_rst_chn9),
.buf_rdata_chn (buf_rdata_chn9));
.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.buf_rd_chn(buf_rd_chn9),.buf_rdata_chn(buf_rdata_chn9));
`endif
`endif
`ifdef def_enable_mem_chn10
`ifdef def_enable_mem_chn10
mcont_common_chnbuf_reg #( .CHN_NUMBER(10)) mcont_common_chnbuf_reg10_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done10),.rpage_nxt(rpage_nxt_chn10));
`ifdef def_read_mem_chn10
mcont_to_chnbuf_reg #(.CHN_NUMBER( 10)) mcont_to_chnbuf_reg10_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done10),.buf_wr_chn(buf_wr_chn10),.buf_waddr_rst_chn(buf_waddr_rst_chn10),.buf_wdata_chn(buf_wdata_chn10));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 10)) mcont_to_chnbuf_reg10_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn10),.buf_wpage_nxt_chn(buf_wpage_nxt_chn10),.buf_wdata_chn(buf_wdata_chn10));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 10),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg10_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done10),.buf_rd_chn(buf_rd_chn10),.buf_raddr_rst_chn(buf_raddr_rst_chn10),
.buf_rdata_chn (buf_rdata_chn10));
.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.buf_rd_chn(buf_rd_chn10),.buf_rdata_chn(buf_rdata_chn10));
`endif
`endif
`ifdef def_enable_mem_chn11
`ifdef def_enable_mem_chn11
mcont_common_chnbuf_reg #( .CHN_NUMBER(11)) mcont_common_chnbuf_reg11_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done11),.rpage_nxt(rpage_nxt_chn11));
`ifdef def_read_mem_chn11
mcont_to_chnbuf_reg #(.CHN_NUMBER( 11)) mcont_to_chnbuf_reg11_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done11),.buf_wr_chn(buf_wr_chn11),.buf_waddr_rst_chn(buf_waddr_rst_chn11),.buf_wdata_chn(buf_wdata_chn11));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 11)) mcont_to_chnbuf_reg11_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn11),.buf_wpage_nxt_chn(buf_wpage_nxt_chn11),.buf_wdata_chn(buf_wdata_chn11));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 11),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg11_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done11),.buf_rd_chn(buf_rd_chn11),.buf_raddr_rst_chn(buf_raddr_rst_chn11),
.buf_rdata_chn (buf_rdata_chn11));
.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.buf_rd_chn(buf_rd_chn11),.buf_rdata_chn(buf_rdata_chn11));
`endif
`endif
`ifdef def_enable_mem_chn12
`ifdef def_enable_mem_chn12
mcont_common_chnbuf_reg #( .CHN_NUMBER(12)) mcont_common_chnbuf_reg12_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done12),.rpage_nxt(rpage_nxt_chn12));
`ifdef def_read_mem_chn12
mcont_to_chnbuf_reg #(.CHN_NUMBER( 12)) mcont_to_chnbuf_reg12_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done12),.buf_wr_chn(buf_wr_chn12),.buf_waddr_rst_chn(buf_waddr_rst_chn12),.buf_wdata_chn(buf_wdata_chn12));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 12)) mcont_to_chnbuf_reg12_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn12),.buf_wpage_nxt_chn(buf_wpage_nxt_chn12),.buf_wdata_chn(buf_wdata_chn12));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 12),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg12_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done12),.buf_rd_chn(buf_rd_chn12),.buf_raddr_rst_chn(buf_raddr_rst_chn12),
.buf_rdata_chn (buf_rdata_chn12));
.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.buf_rd_chn(buf_rd_chn12),.buf_rdata_chn(buf_rdata_chn12));
`endif
`endif
`ifdef def_enable_mem_chn13
`ifdef def_enable_mem_chn13
mcont_common_chnbuf_reg #( .CHN_NUMBER(13)) mcont_common_chnbuf_reg13_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done13),.rpage_nxt(rpage_nxt_chn13));
`ifdef def_read_mem_chn13
mcont_to_chnbuf_reg #(.CHN_NUMBER( 13)) mcont_to_chnbuf_reg13_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done13),.buf_wr_chn(buf_wr_chn13),.buf_waddr_rst_chn(buf_waddr_rst_chn13),.buf_wdata_chn(buf_wdata_chn13));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 13)) mcont_to_chnbuf_reg13_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn13),.buf_wpage_nxt_chn(buf_wpage_nxt_chn13),.buf_wdata_chn(buf_wdata_chn13));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 13),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg13_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done13),.buf_rd_chn(buf_rd_chn13),.buf_raddr_rst_chn(buf_raddr_rst_chn13),
.buf_rdata_chn (buf_rdata_chn13));
.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.buf_rd_chn(buf_rd_chn13),.buf_rdata_chn(buf_rdata_chn13));
`endif
`endif
`ifdef def_enable_mem_chn14
`ifdef def_enable_mem_chn14
mcont_common_chnbuf_reg #( .CHN_NUMBER(14)) mcont_common_chnbuf_reg14_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done14),.rpage_nxt(rpage_nxt_chn14));
`ifdef def_read_mem_chn14
mcont_to_chnbuf_reg #(.CHN_NUMBER( 14)) mcont_to_chnbuf_reg14_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done14),.buf_wr_chn(buf_wr_chn14),.buf_waddr_rst_chn(buf_waddr_rst_chn14),.buf_wdata_chn(buf_wdata_chn14));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 14)) mcont_to_chnbuf_reg14_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn14),.buf_wpage_nxt_chn(buf_wpage_nxt_chn14),.buf_wdata_chn(buf_wdata_chn14));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 14),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg14_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done14),.buf_rd_chn(buf_rd_chn14),.buf_raddr_rst_chn(buf_raddr_rst_chn14),
.buf_rdata_chn (buf_rdata_chn14));
.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.buf_rd_chn(buf_rd_chn14),.buf_rdata_chn(buf_rdata_chn14));
`endif
`endif
`ifdef def_enable_mem_chn15
`ifdef def_enable_mem_chn15
mcont_common_chnbuf_reg #( .CHN_NUMBER(15)) mcont_common_chnbuf_reg15_i(.rst(rst),.clk(mclk), .ext_buf_rchn(ext_buf_rchn),
.ext_buf_rpage_nxt(ext_buf_rpage_nxt),.seq_done(sequencer_run_done),.buf_done(seq_done15),.rpage_nxt(rpage_nxt_chn15));
`ifdef def_read_mem_chn15
mcont_to_chnbuf_reg #(.CHN_NUMBER( 15)) mcont_to_chnbuf_reg15_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_waddr_rst(ext_buf_waddr_rst),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.seq_done(sequencer_run_done),.buf_done(seq_done15),.buf_wr_chn(buf_wr_chn15),.buf_waddr_rst_chn(buf_waddr_rst_chn15),.buf_wdata_chn(buf_wdata_chn15));
mcont_to_chnbuf_reg #(.CHN_NUMBER( 15)) mcont_to_chnbuf_reg15_i(.rst(rst),.clk(mclk),.ext_buf_wr(ext_buf_wr),.ext_buf_wpage_nxt(ext_buf_wpage_nxt),
.ext_buf_wchn(ext_buf_wchn),.ext_buf_wdata(ext_buf_wdata),.buf_wr_chn(buf_wr_chn15),.buf_wpage_nxt_chn(buf_wpage_nxt_chn15),.buf_wdata_chn(buf_wdata_chn15));
`else
mcont_from_chnbuf_reg #(.CHN_NUMBER( 15),.CHN_LATENCY(CHNBUF_READ_LATENCY)) mcont_from_chnbuf_reg15_i (.rst(rst),.clk(mclk),.ext_buf_rd(ext_buf_rd),
.ext_buf_raddr_rst(ext_buf_raddr_rst),.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.seq_done(sequencer_run_done),.buf_done(seq_done15),.buf_rd_chn(buf_rd_chn15),.buf_raddr_rst_chn(buf_raddr_rst_chn15),
.buf_rdata_chn (buf_rdata_chn15));
.ext_buf_rchn(ext_buf_rchn),.ext_buf_rdata(ext_buf_rdata),.buf_rd_chn(buf_rd_chn15),.buf_rdata_chn(buf_rdata_chn15));
`endif
`endif
// combining channel control signals to buses
`ifndef def_enable_mem_chn0
wire want_rq0=0, need_rq0=0;
......
phy/mcontr_sequencer.v
View file @ ecd4a509
......@@ -143,7 +143,7 @@ module mcontr_sequencer #(
// There will be =1 cycle external latency in address/re and 1 cycle latency in read data (should match sequence programs)
// Address data is sync to posedge mclk
output ext_buf_rd,
output ext_buf_raddr_rst, // reset external buffer address to page start
output ext_buf_rpage_nxt, // increment external buffer read address to next page start
// output [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally
output [3:0] ext_buf_rchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally
input [63:0] ext_buf_rdata, // Latency of ram_1kx32w_512x64r plus 2
......@@ -152,7 +152,7 @@ module mcontr_sequencer #(
// Address/data sync to negedge mclk!, any latency OK - just generate DONE appropriately (through the sequencer with delay?
// folowing a sync to negedge!
output ext_buf_wr,
output ext_buf_waddr_rst, // reset external buffer address to page start
output ext_buf_wpage_nxt, // increment external buffer write address to next page start
// output [6:0] ext_buf_waddr, // valid with ext_buf_wr
output [3:0] ext_buf_wchn, // ==run_chn_d valid 1 cycle ahead of ext_buf_wr!, maybe not needed - will be generated externally
output [63:0] ext_buf_wdata, // valid with ext_buf_wr
......@@ -222,8 +222,9 @@ module mcontr_sequencer #(
// wire [63:0] buf1_rdata;
wire buf_wr; // delayed by specified number of clock cycles
wire buf_wr_ndly; // before dealy
wire buf_rd; // read next 64 bytes from the buffer, need one extra pre-read
wire buf_rd; // read next 64 bits from the buffer, need one extra pre-read
wire buf_rst; // reset buffer address to
wire buf_rst_d; //buf_rst delayed to match buf_wr
wire rst=rst_in;
// wire [ 9:0] next_cmd_addr;
......@@ -241,10 +242,12 @@ module mcontr_sequencer #(
// reg [1:0] buf_page; // one of 4 pages in the channel buffer to use for R/W
// reg [15:0] buf_sel_1hot; // 1 hot channel buffer select
wire [3:0] run_chn_w_d; // run chn delayed to match buf_wr delay
reg [3:0] run_chn_d;
reg [3:0] run_chn_d_negedge;
reg run_seq_d;
reg [3:0] run_chn_w_d_negedge;
// reg run_seq_d;
wire [7:0] tmp_debug_a;
assign tmp_debug[11:0] =
......@@ -266,17 +269,17 @@ module mcontr_sequencer #(
// External buffers buffer related signals
assign buf_raddr_reset= run_seq_d;
assign buf_raddr_reset= buf_rst; // run_seq_d;
assign ext_buf_rd= buf_rd;
assign ext_buf_raddr_rst=buf_raddr_reset;
assign ext_buf_rpage_nxt=buf_raddr_reset;
// assign ext_buf_raddr= buf_raddr;
assign ext_buf_rchn= run_chn_d;
assign buf_rdata[63:0] = ext_buf_rdata;
assign ext_buf_wr= buf_wr_negedge;
assign ext_buf_waddr_rst=buf_waddr_reset_negedge;
assign ext_buf_wpage_nxt=buf_waddr_reset_negedge;
// assign ext_buf_waddr= buf_waddr_negedge;
assign ext_buf_wchn= run_chn_d_negedge;
assign ext_buf_wchn= run_chn_w_d_negedge;
assign ext_buf_wdata= buf_wdata_negedge;
// generation of the control signals from byte-serial channel
......@@ -441,18 +444,17 @@ module mcontr_sequencer #(
if (rst) run_chn_d <= 0;
else if (run_seq) run_chn_d <= run_chn;
if (rst) run_seq_d <= 0;
else run_seq_d <= run_seq;
// if (rst) run_seq_d <= 0;
// else run_seq_d <= run_seq;
end
// re-register buffer write address to match DDR3 data
always @ (negedge mclk) begin
// buf_waddr_negedge <= buf_raddr;
buf_waddr_reset_negedge <= buf_raddr_reset;
buf_waddr_reset_negedge <= buf_rst_d; //buf_raddr_reset;
buf_wr_negedge <= buf_wr;
buf_wdata_negedge <= buf_wdata;
run_chn_d_negedge <= run_chn_d;
//TODO: add write channel number?
run_chn_w_d_negedge <= run_chn_w_d; //run_chn_d;
end
// Command sequence memories:
......@@ -567,7 +569,8 @@ module mcontr_sequencer #(
.buf_wdata (buf_wdata[63:0]), // output[63:0]
.buf_rdata (buf_rdata[63:0]), // input[63:0]
.buf_wr (buf_wr_ndly), // output
.buf_rd (buf_rd), // output
.buf_rd (buf_rd), // output
.buf_rst (buf_rst), // reset external buffer address to page start
.cmda_en (cmda_en), // input
.ddr_rst (ddr_rst), // input
.dci_rst (dci_rst), // input
......@@ -582,13 +585,21 @@ module mcontr_sequencer #(
.dqs_tri_off_pattern (dqs_tri_off_pattern[3:0]) // input[3:0]
);
// delay buf_wr by 1-16 cycles to compensate for DDR and HDL code latency (~7 cycles?)
dly01_16 buf_wr_dly_i (
dly_16 #(2) buf_wr_dly_i (
.clk(mclk), // input
.rst(1'b0), // input
.dly(wbuf_delay[3:0]), // input[3:0]
.din(buf_wr_ndly), // input
.dout(buf_wr) // output reg
.din({buf_rst,buf_wr_ndly}), // input
.dout({buf_rst_d, buf_wr}) // output reg
);
dly_16 #(4) buf_wchn_dly_i (
.clk(mclk), // input
.rst(1'b0), // input
.dly(wbuf_delay[3:0]-1), // input[3:0]
.din(run_chn_d), // input
.dout(run_chn_w_d) // output reg
);
//run_chn_w_d
endmodule
phy/phy_cmd.v
View file @ ecd4a509
......@@ -104,7 +104,8 @@ module phy_cmd#(
output [63:0] buf_wdata, // data to be written to the buffer (from DDR3), valid @ negedge mclk
input [63:0] buf_rdata, // data read from the buffer (to DDR3)
output buf_wr, // write buffer (next cycle!)
output buf_rd, // read buffer (ready next cycle)
output buf_rd, // read buffer (ready next cycle)
output buf_rst, // reset external buffer address to page start
// extras
// input cmda_tri, // tristate command and address lines // not likely to be used
input cmda_en, // tristate command and address lines // not likely to be used
......@@ -140,6 +141,7 @@ module phy_cmd#(
wire phy_dqs_toggle_en; //enable toggle DQS according to the pattern
wire phy_buf_wr; // connect to extrenal buffer
wire phy_buf_rd; // connect to extrenal buffer
wire phy_buf_rst; // reset buffers to page start
wire cmda_tri;
wire [2:0] phy_rcw_cur; // {ras,cas,we}
......@@ -152,7 +154,7 @@ module phy_cmd#(
wire phy_dci_en_cur; //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
wire phy_buf_wr_cur; // connect to external buffer (but only if not paused)
wire phy_buf_rd_cur; // connect to external buffer (but only if not paused)
wire phy_buf_rst_cur;
// wire clk;
wire clk_div;
......@@ -192,7 +194,8 @@ module phy_cmd#(
reg [ 2:0] phy_bank_prev;
wire [ADDRESS_NUMBER-1:0] phy_addr_calm;
wire [ 2:0] phy_bank_calm;
reg [ 8:0] extra_prev;
// reg [ 8:0] extra_prev;
reg [ 9:0] extra_prev;
// assign phy_locked= phy_locked_mmcm && phy_locked_pll; // no dci and dly here
......@@ -200,7 +203,7 @@ module phy_cmd#(
// output [63:0] buf_wdata, // data to be written to the buffer (from DDR3)
// SuppressWarnings VEditor
(* keep = "true" *) wire phy_spare;
// (* keep = "true" *) wire phy_spare;
assign {
phy_addr_in,
phy_bank_in,
......@@ -216,20 +219,21 @@ module phy_cmd#(
phy_buf_wr, // connect to external buffer (but only if not paused)
phy_buf_rd, // connect to external buffer (but only if not paused)
phy_cmd_add_pause, // add nop to current command
phy_spare // Reserved for future use
phy_buf_rst // phy_spare // Reserved for future use
} = phy_cmd_word;
assign {
phy_rcw_cur[2:0], // all set to 0
phy_odt_cur, // 8 ODT
phy_cke_dis_cur, // 7 disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed)
phy_sel_cur, // 6 first/second half-cycle, other will be nop (cke+odt applicable to both) - NOT USED?
phy_dq_en_cur, // 5 phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
phy_dqs_en_cur, // 4 phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
phy_dqs_toggle_cur,// 3 enable toggle DQS according to the pattern
phy_dci_en_cur, // 2 phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
phy_buf_wr_cur, // 1 connect to external buffer (but only if not paused)
phy_buf_rd_cur // 0 connect to external buffer (but only if not paused)
phy_odt_cur, // 9 8 ODT
phy_cke_dis_cur, // 8 7 disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed)
phy_sel_cur, // 7 6 first/second half-cycle, other will be nop (cke+odt applicable to both) - NOT USED?
phy_dq_en_cur, // 6 5 phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
phy_dqs_en_cur, // 5 4 phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
phy_dqs_toggle_cur,// 4 3 enable toggle DQS according to the pattern
phy_dci_en_cur, // 3 2 phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
phy_buf_wr_cur, // 2 1 connect to external buffer (but only if not paused)
phy_buf_rd_cur, // 1 0 connect to external buffer (but only if not paused)
phy_buf_rst_cur // 0
} = add_pause ? {3'b0, extra_prev} : // 3'b0 for rcw (nop)
{
phy_rcw_pos[2:0], // {ras,cas,we}
......@@ -241,7 +245,8 @@ module phy_cmd#(
phy_dqs_toggle_en, //enable toggle DQS according to the pattern
phy_dci_en_in, //phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
phy_buf_wr, // connect to external buffer (but only if not paused)
phy_buf_rd // connect to external buffer (but only if not paused)
phy_buf_rd, // connect to external buffer (but only if not paused)
phy_buf_rst
};
assign phy_cke_in= phy_cke_dis_cur ^ ddr_cke;
assign phy_dq_tri_in= ~phy_dq_en_cur;
......@@ -257,6 +262,7 @@ module phy_cmd#(
// assign buf_addr = phy_buf_addr;
assign buf_wr = phy_buf_wr_cur;
assign buf_rd = phy_buf_rd_cur;
assign buf_rst= phy_buf_rst_cur;
// assign phy_addr= {phy_addr_in,phy_addr_in}; // also provides pause length when the command is NOP
// assign phy_bank= {phy_bank_in,phy_bank_in};
......@@ -302,15 +308,16 @@ module phy_cmd#(
phy_addr_prev <= phy_addr_in;
phy_bank_prev <= phy_bank_in;
extra_prev <= {
phy_odt_in, // 8 may be optimized?
phy_cke_dis, // 7 disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed)
phy_sel_in, // 6 first/second half-cycle, other will be nop (cke+odt applicable to both)
phy_dq_en_in, // 5 phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
phy_dqs_en_in, // 4 phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
phy_dqs_toggle_en,// 3 enable toggle DQS according to the pattern
phy_dci_en_in, // 2 phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
phy_buf_wr, // 1 connect to external buffer (but only if not paused)
phy_buf_rd // 0 connect to external buffer (but only if not paused)
phy_odt_in, // 9 8 may be optimized?
phy_cke_dis, // 8 7 disable cke (0 - enable), also controlled by a command bit ddr_cke (XOR-ed)
phy_sel_in, // 7 6 first/second half-cycle, other will be nop (cke+odt applicable to both)
phy_dq_en_in, // 6 5 phy_dq_tri_in, // tristate DQ lines (internal timing sequencer for 0->1 and 1->0)
phy_dqs_en_in, // 5 4 phy_dqs_tri_in, // tristate DQS lines (internal timing sequencer for 0->1 and 1->0)
phy_dqs_toggle_en,// 4 3 enable toggle DQS according to the pattern
phy_dci_en_in, // 3 2 phy_dci_in, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
phy_buf_wr, // 2 1 connect to external buffer (but only if not paused)
phy_buf_rd, // 1 0 connect to external buffer (but only if not paused)
phy_buf_rst // 0 connect to external buffer (but only if not paused)
};
end
......
util_modules/dly_16.v 0 → 100644
View file @ ecd4a509
/*******************************************************************************
* Module: dly_16
* Date:2014-05-30
* Author: Andrey Filippov
* Description: Synchronous delay by 1-16 clock cycles with reset (will map to primitives)
*
* Copyright (c) 2014 Elphel, Inc.
* dly_16.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dly_16.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module dly_16 #(
parameter WIDTH=1
)(
input clk,
input rst,
input [3:0] dly,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout
);
generate
genvar i;
for (i=0; i < WIDTH; i=i+1) begin: bit_block
dly01_16 dly01_16_i (
.clk(clk), // input
.rst(rst), // input
.dly(dly), // input[3:0]
.din(din[i]), // input
.dout(dout[i]) // output reg
);
end
endgenerate
endmodule
util_modules/mcont_common_chnbuf_reg.v 0 → 100644
View file @ ecd4a509
/*******************************************************************************
* Module: mcont_common_chnbuf_reg
* Date:2015-01-19
* Author: andrey
* Description: Registering data from channel buffer to memory controller
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* mcont_common_chnbuf_reg.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* mcont_common_chnbuf_reg.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module mcont_common_chnbuf_reg #(
parameter CHN_NUMBER=0
)(
input rst,
input clk,
input [3:0] ext_buf_rchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally
input ext_buf_rpage_nxt,
input seq_done, // sequence done
output reg buf_done, // sequence done for the specified channel
output reg rpage_nxt
);
reg buf_chn_sel;
always @ (posedge rst or posedge clk) begin
if (rst) buf_chn_sel <= 0;
else buf_chn_sel <= (ext_buf_rchn==CHN_NUMBER);
if (rst) buf_done <= 0;
else buf_done <= buf_chn_sel && seq_done;
end
always @ (posedge clk) rpage_nxt <= ext_buf_rpage_nxt && (ext_buf_rchn==CHN_NUMBER);
endmodule
util_modules/mcont_from_chnbuf_reg.v
View file @ ecd4a509
......@@ -27,15 +27,13 @@ module mcont_from_chnbuf_reg #(
input rst,
input clk,
input ext_buf_rd,
input ext_buf_raddr_rst,
// input [6:0] ext_buf_raddr, // valid with ext_buf_rd, 2 page MSB to be generated externally
// input ext_buf_raddr_rst,
input [3:0] ext_buf_rchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_rd!, maybe not needed - will be generated externally
input seq_done, // sequence done
output reg buf_done, // sequence done for the specified channel
// input seq_done, // sequence done
// output reg buf_done, // sequence done for the specified channel
output reg [63:0] ext_buf_rdata, // Latency of ram_1kx32w_512x64r plus 2
output reg buf_rd_chn,
output reg buf_raddr_rst_chn,
// output reg [6:0] buf_raddr_chn,
// output reg buf_raddr_rst_chn,
input [63:0] buf_rdata_chn
);
reg buf_chn_sel;
......@@ -53,7 +51,7 @@ module mcont_from_chnbuf_reg #(
if (rst) buf_done <= 0;
else buf_done <= buf_chn_sel && seq_done;
end
always @ (posedge clk) buf_raddr_rst_chn <= ext_buf_raddr_rst && (ext_buf_rchn==CHN_NUMBER);
// always @ (posedge clk) buf_raddr_rst_chn <= ext_buf_raddr_rst && (ext_buf_rchn==CHN_NUMBER);
// always @ (posedge clk) if (buf_chn_sel && ext_buf_rd) buf_raddr_chn <= ext_buf_raddr;
always @ (posedge clk) if (latency_reg[CHN_LATENCY]) ext_buf_rdata <= buf_rdata_chn;
endmodule
......
util_modules/mcont_to_chnbuf_reg.v
View file @ ecd4a509
......@@ -26,15 +26,13 @@ parameter CHN_NUMBER=0
input rst,
input clk,
input ext_buf_wr,
input ext_buf_waddr_rst,
// input [6:0] ext_buf_waddr, // valid with ext_buf_wr
input ext_buf_wpage_nxt,
input [3:0] ext_buf_wchn, // ==run_chn_d valid 1 cycle ahead opf ext_buf_wr!, maybe not needed - will be generated externally
input [63:0] ext_buf_wdata, // valid with ext_buf_wr
input seq_done, // sequence done
output reg buf_done, // @ posedge mclk sequence done for the specified channel
// input seq_done, // sequence done
// output reg buf_done, // @ posedge mclk sequence done for the specified channel
output reg buf_wr_chn, // @ negedge mclk
output reg buf_waddr_rst_chn,// @ negedge mclk
// output reg [6:0] buf_waddr_chn, // @ negedge mclk
output reg buf_wpage_nxt_chn,// @ negedge mclk
output reg [63:0] buf_wdata_chn // @ negedge mclk
);
reg buf_chn_sel;
......@@ -46,17 +44,16 @@ parameter CHN_NUMBER=0
else buf_wr_chn <= buf_chn_sel && ext_buf_wr;
end
always @ (posedge rst or posedge clk) begin
if (rst) buf_done <= 0;
else buf_done <= buf_chn_sel && seq_done;
end
// always @ (posedge rst or posedge clk) begin
// if (rst) buf_done <= 0;
// else buf_done <= buf_chn_sel && seq_done;
// end
always @ (negedge clk) begin
buf_waddr_rst_chn <= ext_buf_waddr_rst && (ext_buf_wchn==CHN_NUMBER);
buf_wpage_nxt_chn <= ext_buf_wpage_nxt && (ext_buf_wchn==CHN_NUMBER);
end
always @ (negedge clk) if (buf_chn_sel && ext_buf_wr) begin
// buf_waddr_chn <= ext_buf_waddr;
buf_wdata_chn <= ext_buf_wdata;
end
endmodule
......
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