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Commit ea63654a authored by Andrey Filippov's avatar Andrey Filippov
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Modified DDR memory calibration to reduce occasional failures

parent 18b781bc
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Showing with 81647 additions and 79481 deletions
.project
View file @ ea63654a
......@@ -62,57 +62,52 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151117233913191.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160313162251081.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151117233913191.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160313162251081.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151117233913191.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160313162251081.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151117233913191.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160313162251081.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151117233913191.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160313162251081.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151117233913191.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160313162251081.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151117233307674.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160313161825094.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151117233913191.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160313162251081.log</location>
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<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20151105233458943.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20151101221627109.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160313161825094.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150905102847882.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160313161825094.log</location>
</link>
<link>
<name>vivado_state/x393-opt-phys.dcp</name>
......@@ -132,7 +127,7 @@
<link>
<name>vivado_state/x393-synth.dcp</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150905102847882.dcp</location>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20160313161825094.dcp</location>
</link>
</linkedResources>
</projectDescription>
.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs
View file @ ea63654a
VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary=true
VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary=true
VivadoTimimgSummaryReportSynthesis_122_DisableVivadoTimingSummary=true
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary<-@\#\#@->VivadoTimimgSummaryReportSynthesis_122_DisableVivadoTimingSummary<-@\#\#@->
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs
View file @ ea63654a
VivadoTimingReportSynthesis_102_DisableVivadoTiming=true
VivadoTimingReportSynthesis_121_DisableVivadoTiming=true
VivadoTimingReportSynthesis_122_DisableVivadoTiming=true
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_102_DisableVivadoTiming<-@\#\#@->VivadoTimingReportSynthesis_121_DisableVivadoTiming<-@\#\#@->VivadoTimingReportSynthesis_122_DisableVivadoTiming<-@\#\#@->
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_102_DisableVivadoTiming<-@\#\#@->VivadoTimingReportSynthesis_121_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1
.settings/org.eclipse.core.resources.prefs
View file @ ea63654a
......@@ -2,3 +2,4 @@ eclipse.preferences.version=1
encoding//helpers/convert_data_to_params.py=utf-8
encoding//helpers/convert_pass_init_params.py=utf-8
encoding//helpers/convert_zigzag_rom.py=utf-8
encoding//py393/test_mcntrl.py=utf-8
py393/dbg/x393_mcntrl.pickle 100755 → 100644
View file @ ea63654a
This source diff could not be displayed because it is too large. You can view the blob instead.
py393/x393_axi_control_status.py
View file @ ea63654a
......@@ -163,22 +163,44 @@ class X393AxiControlStatus(object):
"""
Read current temperature and supply voltages
"""
HWMON_PATH = "/sys/devices/amba.0/f8007100.ps7-xadc/"
# HWMON_PATH = "/sys/devices/amba.0/f8007100.ps7-xadc/"
HWMON_PATH = '/sys/devices/soc0/amba@0/f8007100.ps7-xadc/iio:device0/'
FILE = "file"
ITEM = "item"
UNITS = "units"
SCALE = "scale"
HWMON_ITEMS= [{FILE:"temp", ITEM:"Temperature", UNITS:"C", SCALE: 1.0},
{FILE:"vccaux", ITEM:"VCCaux", UNITS:"V", SCALE: 0.001},
{FILE:"vccint", ITEM:"VCCint", UNITS:"V", SCALE: 0.001},
{FILE:"vccbram", ITEM:"VCCbram", UNITS:"V", SCALE: 0.001}]
HWMON_ITEMS= [{FILE:"in_temp0", ITEM:"Temperature", UNITS:"C", SCALE: 0.001},
{FILE:"in_voltage0_vccint", ITEM:"VCCint", UNITS:"V", SCALE: 0.001},
{FILE:"in_voltage1_vccaux", ITEM:"VCCaux", UNITS:"V", SCALE: 0.001},
{FILE:"in_voltage2_vccbram", ITEM:"VCCbram", UNITS:"V", SCALE: 0.001},
{FILE:"in_voltage3_vccpint", ITEM:"VCCPint", UNITS:"V", SCALE: 0.001},
{FILE:"in_voltage4_vccpaux", ITEM:"VCCPaux", UNITS:"V", SCALE: 0.001},
{FILE:"in_voltage5_vccoddr", ITEM:"VCCOddr", UNITS:"V", SCALE: 0.001},
{FILE:"in_voltage6_vrefp", ITEM:"VREFp", UNITS:"V", SCALE: 0.001},
{FILE:"in_voltage7_vrefn", ITEM:"VREFn", UNITS:"V", SCALE: 0.001},
]
print("hwmon:")
if self.DRY_MODE:
print ("Not defined for simulation mode")
return
for par in HWMON_ITEMS:
with open(HWMON_PATH + par[FILE]) as f:
d=int(f.read())
# with open(HWMON_PATH + par[FILE]) as f:
# d=int(f.read())
with open(HWMON_PATH + par[FILE]+"_raw") as f:
raw=float(f.read().strip())
with open(HWMON_PATH + par[FILE]+"_scale") as f:
scale=float(f.read().strip())
try:
with open(HWMON_PATH + par[FILE]+"_offset") as f:
offset=float(f.read().strip())
except:
offset = 0
#(guess)
# if (raw>2047) and (par[UNITS] == 'V'):
if (raw > 4000):
raw -= 4096
d= (raw + offset)*scale
num_digits=0
s = par[SCALE]
while s < 1:
......@@ -187,6 +209,7 @@ class X393AxiControlStatus(object):
w = 2+num_digits + (0,1)[num_digits > 0]
frmt = "%%12s = %%%d.%df %%s"%(w,num_digits)
print(frmt%(par[ITEM],(d*par[SCALE]),par[UNITS]))
def write_control_register(self, reg_addr, data):
"""
Write 32-bit word to the control register
......
py393/x393_mcntrl_adjust.py
View file @ ea63654a
......@@ -2868,13 +2868,11 @@ class X393McntrlAdjust(object):
phase_ok=self.set_phase_with_refresh( # check result for not None
phase,
quiet)
if not phase_ok:
print ("Failed to set phase=%d for dly=%d- that should not happen (phase_dqso)- "%(phase,dqs_lin))
# See if it was meant "not phase_ok", not "phase_ok is None":
print ("phase_ok = ",phase_ok)
if phase_ok is None:
print (self.adjustment_state['cmda_bspe'])
return None # no valid CMDA ODELAY exists for this phase
# if not phase_ok:
# print('0',end="") # just checking if something else depends on non-0
#set DQS IDELAY and DQ IDELAY matching phase
dqs_idelay=dqsi_dqi_for_phase[phase][DQSI_KEY] # 2-element list
dq_idelay= dqsi_dqi_for_phase[phase][DQI_KEY] # 16-element list
......@@ -3026,6 +3024,12 @@ class X393McntrlAdjust(object):
dly_prev= max(0,dly-(1,NUM_FINE_STEPS)[compare_prim_steps])
patt_prev=measure_block(dly_prev,invert_patt) # ,force_meas=False) - will be stored in cache
patt= measure_block(dly,invert_patt) # ,force_meas=False) - will be stored in cache
if patt_prev is None:
print ("patt_prev is None for dly= %d !"%(dly))
continue
if patt is None:
print ("patt is None for dly= %d !"%(dly))
continue
for b in range(32):
positiveJump=((not inPhase) and (b<16)) or (inPhase and (b >= 16)) # may be 0, False, True
signs=((-1,1)[patt_prev[b]>0.5],(-1,1)[patt[b]>0.5])
......@@ -3199,6 +3203,11 @@ class X393McntrlAdjust(object):
rdict={"write_prim_steps": compare_prim_steps,
"write_meas_data": meas_data} # TODO: May delete after LMA fitting
self.adjustment_state.update(rdict)
def hex_list(self,lst):
rslt='['
for i in lst:
rslt+="0x%x,"%(i)
return rslt[:-1]+"]"
def measure_addr_odelay(self,
safe_phase=0.25, # 0 strictly follow cmda_odelay, >0 -program with this fraction of clk period from the margin
......@@ -3366,8 +3375,11 @@ class X393McntrlAdjust(object):
wdata32_good=convert_mem16_to_w32(wdata16_good)
wdata16_bad=(bad_patt,)*(8*(nbursts+3))
wdata32_bad=convert_mem16_to_w32(wdata16_bad)
comp32_good= wdata32_good[4:(nbursts*4)+4] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32
comp32_bad= wdata32_bad[4:(nbursts*4)+4] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32
# comp32_good= wdata32_good[4:(nbursts*4)+4] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32
# comp32_bad= wdata32_bad[4:(nbursts*4)+4] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32
comp32_good= wdata32_good[4:(nbursts*4)+2] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32
comp32_bad= wdata32_bad[4:(nbursts*4)+2] # data to compare with read buffer - discard first 4*32-bit words and the "tail" after nrep*4 words32
self.x393_mcntrl_buffers.write_block_buf_chn(0,0,wdata32_good,quiet) # fill block memory (channel, page, number)
self.x393_pio_sequences.set_write_block(ba,ra,ca,nbursts+3,extraTgl,sel_wr) # set sequence to write 'correct' block
......@@ -3392,7 +3404,6 @@ class X393McntrlAdjust(object):
# if got for one bit - try other bits in vicinity
# check that the particular phase is valid for all parameters
# To increase valid range it is possible to ignore write delays as they are not used here
def addr_phase_step(phase):
def measure_block(dly,
addr_bit,
......@@ -3413,16 +3424,21 @@ class X393McntrlAdjust(object):
buf=self.x393_pio_sequences.read_block(4 * (nbursts+1) +2,
(0,1)[quiet<1], #show_rslt,
1) # wait_complete=1)
buf= buf[4:(nbursts*4)+4] # discard first 4*32-bit words and the "tail" after nrep*4 words32
# buf= buf[4:(nbursts*4)+4] # discard first 4*32-bit words and the "tail" after nrep*4 words32
buf= buf[4:(nbursts*4)+2] # discard first 4*32-bit words and the "tail" after nrep*4 words32
if buf==comp32_good:
meas=True
elif buf==comp32_bad:
meas=False
else:
print ("Inconclusive result for comparing read data for phase=%d, addr_bit=%s, bank_bit=%s dly=%d"%(phase,str(addr_bit),str(bank_bit),dly))
print ("Data read from memory=",buf, "(",convert_w32_to_mem16(buf),")")
print ("Expected 'good' data=",comp32_good, "(",convert_w32_to_mem16(comp32_good),")")
print ("Expected 'bad' data=", comp32_bad, "(",convert_w32_to_mem16(comp32_bad),")")
# print ("Data read from memory=",buf, "(",convert_w32_to_mem16(buf),")")
print ("Data read from memory=%s(%s)"%(self.hex_list(buf),self.hex_list(convert_w32_to_mem16(buf))))
#hex_list
# print ("Expected 'good' data=",comp32_good, "(",convert_w32_to_mem16(comp32_good),")")
print ("Expected 'good' data=%s(%s)"%(self.hex_list(comp32_good),self.hex_list(convert_w32_to_mem16(comp32_good))))
# print ("Expected 'bad' data=", comp32_bad, "(",convert_w32_to_mem16(comp32_bad),")")
print ("Expected 'bad' data=%s(%s)"%(self.hex_list(comp32_bad),self.hex_list(convert_w32_to_mem16(comp32_bad))))
meas=None
meas_cache[dly]=meas
if not meas is None:
......@@ -4074,7 +4090,7 @@ class X393McntrlAdjust(object):
"""
Try read mode branches and find sel (early/late read command) and wbuf delay,
if possible
Detect shift by 1/2 clock cycle (should not happen), if it does proq_dqi_dqsi with duifferent prim_set (^2) is needed
Detect shift by 1/2 clock cycle (should not happen), if it does proq_dqi_dqsi with different prim_set (^2) is needed
delay vs. phase should be already calibrated
@param wbuf_dly - initial wbuf delay to try
@quiet reduce output
......@@ -4082,8 +4098,12 @@ class X393McntrlAdjust(object):
optionally result may contain key 'odd' with a list of varinats that resulted in odd number of wrong words
if the remaining number of errors is odd
"""
#temporarily:
# self.load_mcntrl('dbg/x393_mcntrl.pickle')
#Seems that memory can be in mis-aligned state after previous adjustments, and is reading some junk before real block
#Try re-initialize memory here (maybe mov it to after doing dangerous things that caused mis-alignement?)
if quiet < 3:
print ("=== Re-initializing DDR3 before adjusting reads ===")
self.x393_pio_sequences.init_ddr3()
if wbuf_dly is None:
wbuf_dly=vrlg.DFLT_WBUF_DELAY
......@@ -4137,7 +4157,8 @@ class X393McntrlAdjust(object):
# print ("rv is not - it is ",rv)
else:
read_phase_variants.append(None)
# print ("Some are not: phase=",phase,', cmda=',cmda,', dqsi=',dqsi,', dqi=',dqi)
if quiet < 3:
print ("Some are not: phase=",phase,', cmda=',cmda,', dqsi=',dqsi,', dqi=',dqi)
if quiet < 3:
# print("all_read_variants=",all_read_variants)
......@@ -4244,8 +4265,8 @@ class X393McntrlAdjust(object):
forgive_missing = False,
maxPhaseErrorsPS = None,
# quiet=quiet+1)
quiet=quiet+1)
# quiet= 1)
if used_delays is None:
raise Exception("set_read_branch(): failed to set phase = %d"%(phase))
wbuf_dly_max=12
......@@ -4254,7 +4275,7 @@ class X393McntrlAdjust(object):
#set_and_read_inc 8 16 0 0 1 1
last_wstep=0
read_problems=None
for _ in range(20): # limit numer of repetiotions - just in case
for _ in range(20): # limit numer of repetitions - just in case
self.x393_mcntrl_timing.axi_set_wbuf_delay(wdly)
read_results = self.x393_pio_sequences. set_and_read_inc(num8=8, # max 512 16-bit words
ca=ca+16,
......@@ -4262,6 +4283,7 @@ class X393McntrlAdjust(object):
ba=ba,
sel=rsel,
quiet=quiet+1)
read_problems=read_results[:2]
if (read_problems[0]>=4) or ((rsel==0) and (read_problems[0]>=2)):
if last_wstep < 0:
......@@ -4317,11 +4339,11 @@ class X393McntrlAdjust(object):
phase,
sel ^ rsel,
wdly+dw,
shft,
str(read_problems)))
if quiet < 3:
measured_shift= 4*(wdly+dw) - shft - 2* (sel ^ rsel)
#variant=(-1, (0, 0)), calculated shift=1, measured shift=34, cal-meas=-32 shift=0 sel=1 wdly=9 sw=17
print ("variant=%s, calculated shift=%d (clocks), measured shift=%d(words), cal-meas=%d(words), problems=%s"%(
str(variant),
data_shifts[variant],
......@@ -5016,7 +5038,9 @@ write_settings= {
rsel=None, # None (any) or 0/1
wsel=None, # None (any) or 0/1 # Seems wsel=0 has a better fit - consider changing
extraTgl=0,
quiet=3):
quiet=3,
wbuf_dly=9): # just a hint, start value can be different
"""
@param tasks - "*" - load bitfile
"D" - set defaults
......@@ -5055,7 +5079,7 @@ write_settings= {
prim_steps_in=prim_steps
prim_steps_wl=prim_steps
prim_steps_out=prim_steps
wbuf_dly=9 # just a hint, start value can be different
# wbuf_dly=9 # just a hint, start value can be different
# primary_set_in=2
# primary_set_out=2
write_sel=1 # set DDR3 command in the second cycle of two (0 - during the first one)
......@@ -5472,8 +5496,8 @@ write_settings= {
dqs_phase[k.replace('dqs_','dqsi_')]=dqs_phase.pop(k)
if quiet < 3:
print ("dqsi_phase=",dqs_phase)
numLanes= len(dqs_phase)
numPhases=len(dqs_phase[0])
numLanes= len(dqs_phase['dqsi_phase'])
numPhases=len(dqs_phase['dqsi_phase'][0])
print ("\nphase", end=" ")
for lane in range (numLanes):
print("dqsi%d"%(lane),end=" ")
......@@ -5482,7 +5506,7 @@ write_settings= {
print ("%d"%(phase),end=" ")
for lane in range (numLanes):
try:
print("%d"%(dqs_phase[lane][phase]),end=" ")
print("%d"%(dqs_phase['dqsi_phase'][lane][phase]),end=" ")
except:
print("?")
print
......
py393/x393_mcntrl_membridge.py
View file @ ea63654a
......@@ -38,7 +38,8 @@ import x393_mcntrl_timing
import x393_mcntrl_buffers
#import verilog_utils
import x393_mcntrl
MEM_PATH='/sys/devices/elphel393-mem.2/'
#MEM_PATH='/sys/devices/elphel393-mem.2/'
MEM_PATH='/sys/devices/soc0/elphel393-mem@0/'
BUFFER_ADDRESS_NAME='buffer_address'
BUFFER_PAGES_NAME='buffer_pages'
BUFFER_ADDRESS=None
......
py393/x393_mem.py
View file @ ea63654a
......@@ -57,8 +57,8 @@ class X393Mem(object):
with open("/dev/mem", "r+b") as f:
page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
# if (page_addr>=0x80000000):
# page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
packedData=struct.pack(self.ENDIAN+"L",data)
d=struct.unpack(self.ENDIAN+"L",packedData)[0]
......@@ -87,8 +87,8 @@ class X393Mem(object):
with open("/dev/mem", "r+b") as f:
page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
# if (page_addr>=0x80000000):
# page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
data=struct.unpack(self.ENDIAN+"L",mm[page_offs:page_offs+4])
d=data[0]
......@@ -128,8 +128,8 @@ class X393Mem(object):
for addr in range (start_addr,end_addr+byte_mode,byte_mode):
page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
# if (page_addr>=0x80000000):
# page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
data=struct.unpack_from(self.ENDIAN+frmt_bytes[byte_mode],mm, page_offs)
rslt.append(data[0])
......@@ -181,8 +181,8 @@ class X393Mem(object):
if page_num == last_page:
end_offset = start_addr + length - self.PAGE_SIZE * page_num
page_addr = page_num * self.PAGE_SIZE
if (page_addr>=0x80000000):
page_addr-= (1<<32)
# if (page_addr>=0x80000000):
# page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
bf.write(mm[start_offset:end_offset])
......@@ -208,8 +208,8 @@ class X393Mem(object):
if page_num == last_page:
end_offset = start_addr + length - self.PAGE_SIZE * page_num
page_addr = page_num * self.PAGE_SIZE
if (page_addr>=0x80000000):
page_addr-= (1<<32)
# if (page_addr>=0x80000000):
# page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
mm[start_offset:end_offset] = patt[start_offset:end_offset]
......@@ -243,8 +243,8 @@ class X393Mem(object):
data = (start_data + ((addr-start_addr) // byte_mode)*inc_data) & data_mask
page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
# if (page_addr>=0x80000000):
# page_addr-= (1<<32)
print (("0x%08x: "+ data_frmt)%(addr,data))
else:
with open("/dev/mem", "r+b") as f:
......@@ -252,8 +252,8 @@ class X393Mem(object):
data = (start_data + ((addr-start_addr) // byte_mode)*inc_data) & data_mask
page_addr=addr & (~(self.PAGE_SIZE-1))
page_offs=addr-page_addr
if (page_addr>=0x80000000):
page_addr-= (1<<32)
# if (page_addr>=0x80000000):
# page_addr-= (1<<32)
mm = mmap.mmap(f.fileno(), self.PAGE_SIZE, offset=page_addr)
struct.pack_into(self.ENDIAN+frmt_bytes[byte_mode],mm, page_offs, data)
......
py393/x393_pio_sequences.py
View file @ ea63654a
......@@ -88,7 +88,7 @@ class X393PIOSequences(object):
((page & 3) << 10) |
(seq_addr & 0x3ff))
def wait_ps_pio_ready(self, #; // wait PS PIO module can accept comamnds (fifo half empty)
def wait_ps_pio_ready(self, #; // wait PS PIO module can accept commands (fifo half empty)
mode, # input [1:0] mode;
sync_seq, # input sync_seq; // synchronize sequences
timeout=2.0): # maximal timeout in seconds
......@@ -860,7 +860,8 @@ class X393PIOSequences(object):
0, # 1'h0, # mpr; # MPR mode: 0 - normal, 1 - dataflow from MPR
0) # 2'h0); # [1:0] mpr_rf; # MPR read function: 2'b00: predefined pattern 0101...
cmd_addr = vrlg.MCONTR_CMD_WR_ADDR + vrlg.INITIALIZE_OFFSET;
if self.DEBUG_MODE > 1:
# if self.DEBUG_MODE > 1:
if self.DEBUG_MODE > -1:
print("mr0=0x%05x"%mr0);
print("mr1=0x%05x"%mr1);
print("mr2=0x%05x"%mr2);
......@@ -1121,6 +1122,7 @@ class X393PIOSequences(object):
rslt=(first_bad, last_bad, data16[mid_index],mid_index)
if quiet < 3:
print ("non_consecutive leading/trailing: %d /%d, middle data=0x%x, index=0x%x"%rslt)
print(data16)
return rslt
......
py393/x393_sens_cmprs.py
View file @ ea63654a
......@@ -52,9 +52,14 @@ from verilog_utils import hx
PAGE_SIZE = 4096
SI5338_PATH = '/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070'
POWER393_PATH = '/sys/devices/elphel393-pwr.1'
MEM_PATH = '/sys/devices/elphel393-mem.2/'
#SI5338_PATH = '/sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070'
#POWER393_PATH = '/sys/devices/elphel393-pwr.1'
#MEM_PATH = '/sys/devices/elphel393-mem.2/'
SI5338_PATH = '/sys/devices/soc0/amba@0/e0004000.ps7-i2c/i2c-0/0-0070'
POWER393_PATH = '/sys/devices/soc0/elphel393-pwr@0'
MEM_PATH = '/sys/devices/soc0/elphel393-mem@0/'
BUFFER_ADDRESS_NAME = 'buffer_address'
BUFFER_PAGES_NAME = 'buffer_pages'
BUFFER_ADDRESS = None # in bytes
......@@ -148,7 +153,7 @@ class X393SensCmprs(object):
Currently required clock frequency is 1/4 of the sensor clock, so it is 24MHz for 96MHz sensor
@param freq_MHz - input clock frequency (MHz). Currently for 96MHZ sensor clock it should be 24.0
@param iface - one of the supported interfaces
(see ls /sys/devices/amba.0/e0004000.ps7-i2c/i2c-0/0-0070/output_drivers)
(see ls /sys/devices/soc0/amba@0/e0004000.ps7-i2c/i2c-0/0-0070/output_drivers)
@param quiet - reduce output
"""
if self.DRY_MODE:
......
py393/x393_utils.py
View file @ ea63654a
......@@ -97,7 +97,9 @@ class X393Utils(object):
if bitfile is None:
bitfile=DEFAULT_BITFILE
print ("Sensor ports power off")
POWER393_PATH = '/sys/devices/elphel393-pwr.1'
# POWER393_PATH = '/sys/devices/elphel393-pwr.1'
POWER393_PATH = '/sys/devices/soc0/elphel393-pwr@0'
with open (POWER393_PATH + "/channels_dis","w") as f:
print("vcc_sens01 vp33sens01 vcc_sens23 vp33sens23", file = f)
print ("FPGA clock OFF")
......
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