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Elphel
x393
Commits
ea56e79d
Commit
ea56e79d
authored
Oct 22, 2015
by
Andrey Filippov
Browse files
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Plain Diff
Implemented global switching between old/new histograms
parent
12f27fa3
Changes
6
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Showing
6 changed files
with
411 additions
and
401 deletions
+411
-401
sensor_channel.v
sensor/sensor_channel.v
+225
-87
sensors393.v
sensor/sensors393.v
+4
-0
system_defines.vh
system_defines.vh
+2
-0
clocks393.v
util_modules/clocks393.v
+15
-4
x393.v
x393.v
+10
-2
x393_testbench03.sav
x393_testbench03.sav
+155
-308
No files found.
sensor/sensor_channel.v
View file @
ea56e79d
...
@@ -259,8 +259,9 @@ module sensor_channel#(
...
@@ -259,8 +259,9 @@ module sensor_channel#(
// TODO: get rid of pclk2x in histograms by doubling memories (making 1 write port and 2 read ones)
// TODO: get rid of pclk2x in histograms by doubling memories (making 1 write port and 2 read ones)
// How to erase?
// How to erase?
// Alternative: copy/erase to a separate buffer in the beginning/end of a frame?
// Alternative: copy/erase to a separate buffer in the beginning/end of a frame?
`ifdef
USE_PCLK2X
input
pclk2x
,
// global clock input, double pixel rate (192MHz for MT9P006)
input
pclk2x
,
// global clock input, double pixel rate (192MHz for MT9P006)
`endif
input
mrst
,
// @posedge mclk, sync reset
input
mrst
,
// @posedge mclk, sync reset
input
prst
,
// @posedge pclk, sync reset
input
prst
,
// @posedge pclk, sync reset
...
@@ -323,9 +324,11 @@ module sensor_channel#(
...
@@ -323,9 +324,11 @@ module sensor_channel#(
assign
debug_ring
[
DEBUG_RING_LENGTH
]
=
debug_di
;
assign
debug_ring
[
DEBUG_RING_LENGTH
]
=
debug_di
;
`endif
`endif
`ifdef
USE_PCLK2X
localparam
HIST_MONOCHROME
=
1'b0
;
// TODO:make it configurable (at expense of extra hardware)
localparam
HIST_MONOCHROME
=
1'b0
;
// TODO:make it configurable (at expense of extra hardware).
// No, will not use it - monochrome is rare, can combine
// 4 (color) histograms by the software.
`endif
localparam
SENSOR_BASE_ADDR
=
(
SENSOR_GROUP_ADDR
+
SENSOR_NUMBER
*
SENSOR_BASE_INC
)
;
localparam
SENSOR_BASE_ADDR
=
(
SENSOR_GROUP_ADDR
+
SENSOR_NUMBER
*
SENSOR_BASE_INC
)
;
localparam
SENSI2C_STATUS_REG
=
(
SENSI2C_STATUS_REG_BASE
+
SENSOR_NUMBER
*
SENSI2C_STATUS_REG_INC
+
SENSI2C_STATUS_REG_REL
)
;
localparam
SENSI2C_STATUS_REG
=
(
SENSI2C_STATUS_REG_BASE
+
SENSOR_NUMBER
*
SENSI2C_STATUS_REG_INC
+
SENSI2C_STATUS_REG_REL
)
;
...
@@ -993,57 +996,22 @@ module sensor_channel#(
...
@@ -993,57 +996,22 @@ module sensor_channel#(
.
bayer_out
(
gamma_bayer
)
// output [1:0]
.
bayer_out
(
gamma_bayer
)
// output [1:0]
)
;
)
;
// Debugging - adding a parallel to 0:0 module
wire
hist_rq_debug
;
wire
[
31
:
0
]
hist_do_debug
;
wire
hist_dv_debug
;
sens_histogram_snglclk
#(
.
HISTOGRAM_RAM_MODE
(
"BUF32"
)
,
// .HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.
HISTOGRAM_ADDR
(
HISTOGRAM_ADDR0
)
,
.
HISTOGRAM_ADDR_MASK
(
HISTOGRAM_ADDR_MASK
)
,
.
HISTOGRAM_LEFT_TOP
(
HISTOGRAM_LEFT_TOP
)
,
.
HISTOGRAM_WIDTH_HEIGHT
(
HISTOGRAM_WIDTH_HEIGHT
)
`ifdef
DEBUG_RING
,.
DEBUG_CMD_LATENCY
(
DEBUG_CMD_LATENCY
)
`endif
)
sens_histogram_snglclk_chn0_0_i
(
.
mrst
(
mrst
)
,
// input
.
prst
(
prsts
)
,
// input
.
pclk
(
pclk
)
,
// input
.
sof
(
gamma_sof_out
)
,
// input
.
eof
(
gamma_eof_out
)
,
// input
.
hact
(
gamma_hact_out
)
,
// input
.
hist_di
(
gamma_pxd_out
)
,
// input[7:0]
.
mclk
(
mclk
)
,
// input
.
hist_en
(
hist_en
[
0
])
,
// input
.
hist_rst
(
!
hist_nrst
[
0
])
,
// input
.
hist_rq
(
hist_rq_debug
)
,
// output
.
hist_grant
(
hist_gr
[
0
])
,
// input
.
hist_do
(
hist_do_debug
)
,
// output[31:0]
.
hist_dv
(
hist_dv_debug
)
,
// output reg
.
cmd_ad
(
cmd_ad
)
,
// input[7:0]
.
cmd_stb
(
cmd_stb
)
// input
)
;
// TODO: Use generate to generate 1-4 histogram modules
// TODO: Use generate to generate 1-4 histogram modules
generate
generate
if
(
HISTOGRAM_ADDR0
>=
0
)
if
(
HISTOGRAM_ADDR0
>=
0
)
`ifdef
USE_PCLK2X
sens_histogram
#(
sens_histogram
#(
.
HISTOGRAM_RAM_MODE
(
HISTOGRAM_RAM_MODE
)
,
.
HISTOGRAM_RAM_MODE
(
HISTOGRAM_RAM_MODE
)
,
.
HISTOGRAM_ADDR
(
HISTOGRAM_ADDR0
)
,
.
HISTOGRAM_ADDR
(
HISTOGRAM_ADDR0
)
,
.
HISTOGRAM_ADDR_MASK
(
HISTOGRAM_ADDR_MASK
)
,
.
HISTOGRAM_ADDR_MASK
(
HISTOGRAM_ADDR_MASK
)
,
.
HISTOGRAM_LEFT_TOP
(
HISTOGRAM_LEFT_TOP
)
,
.
HISTOGRAM_LEFT_TOP
(
HISTOGRAM_LEFT_TOP
)
,
.
HISTOGRAM_WIDTH_HEIGHT
(
HISTOGRAM_WIDTH_HEIGHT
)
.
HISTOGRAM_WIDTH_HEIGHT
(
HISTOGRAM_WIDTH_HEIGHT
)
`ifdef
DEBUG_RING
`ifdef
DEBUG_RING
,.
DEBUG_CMD_LATENCY
(
DEBUG_CMD_LATENCY
)
,.
DEBUG_CMD_LATENCY
(
DEBUG_CMD_LATENCY
)
`endif
`endif
)
sens_histogram_i
(
)
sens_histogram_0_i
(
// .rst (rst), // input
.
mrst
(
mrst
)
,
// input
.
mrst
(
mrst
)
,
// input
.
prst
(
prsts
)
,
// input extended to include sensor reset and rst_mmcm
// .prst (prst), // input
.
prst
(
prsts
)
,
// input extended to include sensor reset and rst_mmcm
.
pclk
(
pclk
)
,
// input
.
pclk
(
pclk
)
,
// input
.
pclk2x
(
pclk2x
)
,
// input
.
pclk2x
(
pclk2x
)
,
// input
.
sof
(
gamma_sof_out
)
,
// input
.
sof
(
gamma_sof_out
)
,
// input
...
@@ -1061,42 +1029,87 @@ module sensor_channel#(
...
@@ -1061,42 +1029,87 @@ module sensor_channel#(
.
cmd_stb
(
cmd_stb
)
,
// input
.
cmd_stb
(
cmd_stb
)
,
// input
.
monochrome
(
HIST_MONOCHROME
)
// input
.
monochrome
(
HIST_MONOCHROME
)
// input
// ,.debug_mclk(debug_hist_mclk[0])
// ,.debug_mclk(debug_hist_mclk[0])
`ifdef
DEBUG_RING
`ifdef
DEBUG_RING
,.
debug_do
(
debug_ring
[
0
])
,
// output
,.
debug_do
(
debug_ring
[
0
])
,
// output
.
debug_sl
(
debug_sl
)
,
// input
.
debug_sl
(
debug_sl
)
,
// input
.
debug_di
(
debug_ring
[
1
])
// input
.
debug_di
(
debug_ring
[
1
])
// input
`endif
`endif
)
;
)
;
else
else
sens_histogram_dummy
sens_histogram_
dummy
_i
(
sens_histogram_dummy
sens_histogram_
0
_i
(
.
hist_rq
(
hist_rq
[
0
])
,
// output
.
hist_rq
(
hist_rq
[
0
])
,
// output
.
hist_do
(
hist_do0
)
,
// output[31:0]
.
hist_do
(
hist_do0
)
,
// output[31:0]
.
hist_dv
(
hist_dv
[
0
])
// output
.
hist_dv
(
hist_dv
[
0
])
// output
`ifdef
DEBUG_RING
`ifdef
DEBUG_RING
,.
debug_do
(
debug_ring
[
0
])
,
// output
,.
debug_do
(
debug_ring
[
0
])
,
// output
.
debug_di
(
debug_ring
[
1
])
// input
.
debug_di
(
debug_ring
[
1
])
// input
`endif
`endif
)
;
)
;
// `ifdef USE_PCLK2X
`else
sens_histogram_snglclk
#(
.
HISTOGRAM_RAM_MODE
(
HISTOGRAM_RAM_MODE
)
,
.
HISTOGRAM_ADDR
(
HISTOGRAM_ADDR0
)
,
.
HISTOGRAM_ADDR_MASK
(
HISTOGRAM_ADDR_MASK
)
,
.
HISTOGRAM_LEFT_TOP
(
HISTOGRAM_LEFT_TOP
)
,
.
HISTOGRAM_WIDTH_HEIGHT
(
HISTOGRAM_WIDTH_HEIGHT
)
`ifdef
DEBUG_RING
,.
DEBUG_CMD_LATENCY
(
DEBUG_CMD_LATENCY
)
`endif
)
sens_histogram_0_i
(
.
mrst
(
mrst
)
,
// input
.
prst
(
prsts
)
,
// input extended to include sensor reset and rst_mmcm
.
pclk
(
pclk
)
,
// input
.
sof
(
gamma_sof_out
)
,
// input
.
eof
(
gamma_eof_out
)
,
// input
.
hact
(
gamma_hact_out
)
,
// input
.
hist_di
(
gamma_pxd_out
)
,
// input[7:0]
.
mclk
(
mclk
)
,
// input
.
hist_en
(
hist_en
[
0
])
,
// input
.
hist_rst
(
!
hist_nrst
[
0
])
,
// input
.
hist_rq
(
hist_rq
[
0
])
,
// output
.
hist_grant
(
hist_gr
[
0
])
,
// input
.
hist_do
(
hist_do0
)
,
// output[31:0]
.
hist_dv
(
hist_dv
[
0
])
,
// output
.
cmd_ad
(
cmd_ad
)
,
// input[7:0]
.
cmd_stb
(
cmd_stb
)
// input
`ifdef
DEBUG_RING
,.
debug_do
(
debug_ring
[
0
])
,
// output
.
debug_sl
(
debug_sl
)
,
// input
.
debug_di
(
debug_ring
[
1
])
// input
`endif
)
;
else
sens_histogram_snglclk_dummy
sens_histogram_0_i
(
.
hist_rq
(
hist_rq
[
0
])
,
// output
.
hist_do
(
hist_do0
)
,
// output[31:0]
.
hist_dv
(
hist_dv
[
0
])
// output
`ifdef
DEBUG_RING
,.
debug_do
(
debug_ring
[
0
])
,
// output
.
debug_di
(
debug_ring
[
1
])
// input
`endif
)
;
// `ifdef USE_PCLK2X
`endif
endgenerate
endgenerate
generate
generate
if
(
HISTOGRAM_ADDR1
>=
0
)
if
(
HISTOGRAM_ADDR1
>=
0
)
`ifdef
USE_PCLK2X
sens_histogram
#(
sens_histogram
#(
.
HISTOGRAM_RAM_MODE
(
HISTOGRAM_RAM_MODE
)
,
.
HISTOGRAM_RAM_MODE
(
HISTOGRAM_RAM_MODE
)
,
.
HISTOGRAM_ADDR
(
HISTOGRAM_ADDR1
)
,
.
HISTOGRAM_ADDR
(
HISTOGRAM_ADDR1
)
,
.
HISTOGRAM_ADDR_MASK
(
HISTOGRAM_ADDR_MASK
)
,
.
HISTOGRAM_ADDR_MASK
(
HISTOGRAM_ADDR_MASK
)
,
.
HISTOGRAM_LEFT_TOP
(
HISTOGRAM_LEFT_TOP
)
,
.
HISTOGRAM_LEFT_TOP
(
HISTOGRAM_LEFT_TOP
)
,
.
HISTOGRAM_WIDTH_HEIGHT
(
HISTOGRAM_WIDTH_HEIGHT
)
.
HISTOGRAM_WIDTH_HEIGHT
(
HISTOGRAM_WIDTH_HEIGHT
)
`ifdef
DEBUG_RING
`ifdef
DEBUG_RING
,.
DEBUG_CMD_LATENCY
(
DEBUG_CMD_LATENCY
)
,.
DEBUG_CMD_LATENCY
(
DEBUG_CMD_LATENCY
)
`endif
`endif
)
sens_histogram_i
(
)
sens_histogram_1_i
(
// .rst (rst), // input
.
mrst
(
mrst
)
,
// input
.
mrst
(
mrst
)
,
// input
// .prst (prst), // input
.
prst
(
prsts
)
,
// input extended to include sensor reset and rst_mmcm
.
prst
(
prsts
)
,
// input extended to include sensor reset and rst_mmcm
.
pclk
(
pclk
)
,
// input
.
pclk
(
pclk
)
,
// input
.
pclk2x
(
pclk2x
)
,
// input
.
pclk2x
(
pclk2x
)
,
// input
...
@@ -1114,30 +1127,73 @@ module sensor_channel#(
...
@@ -1114,30 +1127,73 @@ module sensor_channel#(
.
cmd_ad
(
cmd_ad
)
,
// input[7:0]
.
cmd_ad
(
cmd_ad
)
,
// input[7:0]
.
cmd_stb
(
cmd_stb
)
,
// input
.
cmd_stb
(
cmd_stb
)
,
// input
.
monochrome
(
HIST_MONOCHROME
)
// input
.
monochrome
(
HIST_MONOCHROME
)
// input
// ,.debug_mclk(debug_hist_mclk[1])
`ifdef
DEBUG_RING
`ifdef
DEBUG_RING
,.
debug_do
(
debug_ring
[
1
])
,
// output
,.
debug_do
(
debug_ring
[
1
])
,
// output
.
debug_sl
(
debug_sl
)
,
// input
.
debug_sl
(
debug_sl
)
,
// input
.
debug_di
(
debug_ring
[
2
])
// input
.
debug_di
(
debug_ring
[
2
])
// input
`endif
`endif
)
;
)
;
else
else
sens_histogram_dummy
sens_histogram_
dummy
_i
(
sens_histogram_dummy
sens_histogram_
1
_i
(
.
hist_rq
(
hist_rq
[
1
])
,
// output
.
hist_rq
(
hist_rq
[
1
])
,
// output
.
hist_do
(
hist_do1
)
,
// output[31:0]
.
hist_do
(
hist_do1
)
,
// output[31:0]
.
hist_dv
(
hist_dv
[
1
])
// output
.
hist_dv
(
hist_dv
[
1
])
// output
`ifdef
DEBUG_RING
`ifdef
DEBUG_RING
,.
debug_do
(
debug_ring
[
1
])
,
// output
,.
debug_do
(
debug_ring
[
1
])
,
// output
.
debug_di
(
debug_ring
[
2
])
// input
.
debug_di
(
debug_ring
[
2
])
// input
`endif
`endif
)
;
)
;
//`ifdef DEBUG_RING
// `ifdef USE_PCLK2X
// assign debug_ring[1] = debug_ring[2]; // just bypass
`else
//`endif
sens_histogram_snglclk
#(
.
HISTOGRAM_RAM_MODE
(
HISTOGRAM_RAM_MODE
)
,
.
HISTOGRAM_ADDR
(
HISTOGRAM_ADDR1
)
,
.
HISTOGRAM_ADDR_MASK
(
HISTOGRAM_ADDR_MASK
)
,
.
HISTOGRAM_LEFT_TOP
(
HISTOGRAM_LEFT_TOP
)
,
.
HISTOGRAM_WIDTH_HEIGHT
(
HISTOGRAM_WIDTH_HEIGHT
)
`ifdef
DEBUG_RING
,.
DEBUG_CMD_LATENCY
(
DEBUG_CMD_LATENCY
)
`endif
)
sens_histogram_1_i
(
.
mrst
(
mrst
)
,
// input
.
prst
(
prsts
)
,
// input extended to include sensor reset and rst_mmcm
.
pclk
(
pclk
)
,
// input
.
sof
(
gamma_sof_out
)
,
// input
.
eof
(
gamma_eof_out
)
,
// input
.
hact
(
gamma_hact_out
)
,
// input
.
hist_di
(
gamma_pxd_out
)
,
// input[7:0]
.
mclk
(
mclk
)
,
// input
.
hist_en
(
hist_en
[
1
])
,
// input
.
hist_rst
(
!
hist_nrst
[
1
])
,
// input
.
hist_rq
(
hist_rq
[
1
])
,
// output
.
hist_grant
(
hist_gr
[
1
])
,
// input
.
hist_do
(
hist_do1
)
,
// output[31:0]
.
hist_dv
(
hist_dv
[
1
])
,
// output
.
cmd_ad
(
cmd_ad
)
,
// input[7:0]
.
cmd_stb
(
cmd_stb
)
// input
`ifdef
DEBUG_RING
,.
debug_do
(
debug_ring
[
1
])
,
// output
.
debug_sl
(
debug_sl
)
,
// input
.
debug_di
(
debug_ring
[
2
])
// input
`endif
)
;
else
sens_histogram_snglclk_dummy
sens_histogram_1_i
(
.
hist_rq
(
hist_rq
[
1
])
,
// output
.
hist_do
(
hist_do1
)
,
// output[31:0]
.
hist_dv
(
hist_dv
[
1
])
// output
`ifdef
DEBUG_RING
,.
debug_do
(
debug_ring
[
1
])
,
// output
.
debug_di
(
debug_ring
[
2
])
// input
`endif
)
;
// `ifdef USE_PCLK2X
`endif
endgenerate
endgenerate
generate
generate
if
(
HISTOGRAM_ADDR2
>=
0
)
if
(
HISTOGRAM_ADDR2
>=
0
)
`ifdef
USE_PCLK2X
sens_histogram
#(
sens_histogram
#(
.
HISTOGRAM_RAM_MODE
(
HISTOGRAM_RAM_MODE
)
,
.
HISTOGRAM_RAM_MODE
(
HISTOGRAM_RAM_MODE
)
,
.
HISTOGRAM_ADDR
(
HISTOGRAM_ADDR2
)
,
.
HISTOGRAM_ADDR
(
HISTOGRAM_ADDR2
)
,
...
@@ -1147,10 +1203,8 @@ module sensor_channel#(
...
@@ -1147,10 +1203,8 @@ module sensor_channel#(
`ifdef
DEBUG_RING
`ifdef
DEBUG_RING
,.
DEBUG_CMD_LATENCY
(
DEBUG_CMD_LATENCY
)
,.
DEBUG_CMD_LATENCY
(
DEBUG_CMD_LATENCY
)
`endif
`endif
)
sens_histogram_i
(
)
sens_histogram_2_i
(
// .rst (rst), // input
.
mrst
(
mrst
)
,
// input
.
mrst
(
mrst
)
,
// input
// .prst (prst), // input
.
prst
(
prsts
)
,
// input extended to include sensor reset and rst_mmcm
.
prst
(
prsts
)
,
// input extended to include sensor reset and rst_mmcm
.
pclk
(
pclk
)
,
// input
.
pclk
(
pclk
)
,
// input
.
pclk2x
(
pclk2x
)
,
// input
.
pclk2x
(
pclk2x
)
,
// input
...
@@ -1168,7 +1222,6 @@ module sensor_channel#(
...
@@ -1168,7 +1222,6 @@ module sensor_channel#(
.
cmd_ad
(
cmd_ad
)
,
// input[7:0]
.
cmd_ad
(
cmd_ad
)
,
// input[7:0]
.
cmd_stb
(
cmd_stb
)
,
// input
.
cmd_stb
(
cmd_stb
)
,
// input
.
monochrome
(
HIST_MONOCHROME
)
// input
.
monochrome
(
HIST_MONOCHROME
)
// input
// ,.debug_mclk(debug_hist_mclk[2])
`ifdef
DEBUG_RING
`ifdef
DEBUG_RING
,.
debug_do
(
debug_ring
[
2
])
,
// output
,.
debug_do
(
debug_ring
[
2
])
,
// output
.
debug_sl
(
debug_sl
)
,
// input
.
debug_sl
(
debug_sl
)
,
// input
...
@@ -1176,7 +1229,7 @@ module sensor_channel#(
...
@@ -1176,7 +1229,7 @@ module sensor_channel#(
`endif
`endif
)
;
)
;
else
else
sens_histogram_dummy
sens_histogram_
dummy
_i
(
sens_histogram_dummy
sens_histogram_
2
_i
(
.
hist_rq
(
hist_rq
[
2
])
,
// output
.
hist_rq
(
hist_rq
[
2
])
,
// output
.
hist_do
(
hist_do2
)
,
// output[31:0]
.
hist_do
(
hist_do2
)
,
// output[31:0]
.
hist_dv
(
hist_dv
[
2
])
// output
.
hist_dv
(
hist_dv
[
2
])
// output
...
@@ -1185,25 +1238,68 @@ module sensor_channel#(
...
@@ -1185,25 +1238,68 @@ module sensor_channel#(
.
debug_di
(
debug_ring
[
3
])
// input
.
debug_di
(
debug_ring
[
3
])
// input
`endif
`endif
)
;
)
;
//`ifdef DEBUG_RING
// `ifdef USE_PCLK2X
// assign debug_ring[2] = debug_ring[3]; // just bypass
`else
//`endif
sens_histogram_snglclk
#(
.
HISTOGRAM_RAM_MODE
(
HISTOGRAM_RAM_MODE
)
,
.
HISTOGRAM_ADDR
(
HISTOGRAM_ADDR2
)
,
.
HISTOGRAM_ADDR_MASK
(
HISTOGRAM_ADDR_MASK
)
,
.
HISTOGRAM_LEFT_TOP
(
HISTOGRAM_LEFT_TOP
)
,
.
HISTOGRAM_WIDTH_HEIGHT
(
HISTOGRAM_WIDTH_HEIGHT
)
`ifdef
DEBUG_RING
,.
DEBUG_CMD_LATENCY
(
DEBUG_CMD_LATENCY
)
`endif
)
sens_histogram_2_i
(
.
mrst
(
mrst
)
,
// input
.
prst
(
prsts
)
,
// input extended to include sensor reset and rst_mmcm
.
pclk
(
pclk
)
,
// input
.
sof
(
gamma_sof_out
)
,
// input
.
eof
(
gamma_eof_out
)
,
// input
.
hact
(
gamma_hact_out
)
,
// input
.
hist_di
(
gamma_pxd_out
)
,
// input[7:0]
.
mclk
(
mclk
)
,
// input
.
hist_en
(
hist_en
[
2
])
,
// input
.
hist_rst
(
!
hist_nrst
[
2
])
,
// input
.
hist_rq
(
hist_rq
[
2
])
,
// output
.
hist_grant
(
hist_gr
[
2
])
,
// input
.
hist_do
(
hist_do2
)
,
// output[31:0]
.
hist_dv
(
hist_dv
[
2
])
,
// output
.
cmd_ad
(
cmd_ad
)
,
// input[7:0]
.
cmd_stb
(
cmd_stb
)
// input
`ifdef
DEBUG_RING
,.
debug_do
(
debug_ring
[
2
])
,
// output
.
debug_sl
(
debug_sl
)
,
// input
.
debug_di
(
debug_ring
[
3
])
// input
`endif
)
;
else
sens_histogram_snglclk_dummy
sens_histogram_2_i
(
.
hist_rq
(
hist_rq
[
2
])
,
// output
.
hist_do
(
hist_do2
)
,
// output[31:0]
.
hist_dv
(
hist_dv
[
2
])
// output
`ifdef
DEBUG_RING
,.
debug_do
(
debug_ring
[
2
])
,
// output
.
debug_di
(
debug_ring
[
3
])
// input
`endif
)
;
// `ifdef USE_PCLK2X
`endif
endgenerate
endgenerate
generate
generate
if
(
HISTOGRAM_ADDR3
>=
0
)
if
(
HISTOGRAM_ADDR3
>=
0
)
`ifdef
USE_PCLK2X
sens_histogram
#(
sens_histogram
#(
.
HISTOGRAM_RAM_MODE
(
HISTOGRAM_RAM_MODE
)
,
.
HISTOGRAM_RAM_MODE
(
HISTOGRAM_RAM_MODE
)
,
.
HISTOGRAM_ADDR
(
HISTOGRAM_ADDR3
)
,
.
HISTOGRAM_ADDR
(
HISTOGRAM_ADDR3
)
,
.
HISTOGRAM_ADDR_MASK
(
HISTOGRAM_ADDR_MASK
)
,
.
HISTOGRAM_ADDR_MASK
(
HISTOGRAM_ADDR_MASK
)
,
.
HISTOGRAM_LEFT_TOP
(
HISTOGRAM_LEFT_TOP
)
,
.
HISTOGRAM_LEFT_TOP
(
HISTOGRAM_LEFT_TOP
)
,
.
HISTOGRAM_WIDTH_HEIGHT
(
HISTOGRAM_WIDTH_HEIGHT
)
.
HISTOGRAM_WIDTH_HEIGHT
(
HISTOGRAM_WIDTH_HEIGHT
)
`ifdef
DEBUG_RING
`ifdef
DEBUG_RING
,.
DEBUG_CMD_LATENCY
(
DEBUG_CMD_LATENCY
)
,.
DEBUG_CMD_LATENCY
(
DEBUG_CMD_LATENCY
)
`endif
`endif
)
sens_histogram_i
(
)
sens_histogram_3_i
(
// .rst (rst), // input
.
mrst
(
mrst
)
,
// input
.
mrst
(
mrst
)
,
// input
// .prst (prst), // input
.
prst
(
prsts
)
,
// input extended to include sensor reset and rst_mmcm
.
prst
(
prsts
)
,
// input extended to include sensor reset and rst_mmcm
.
pclk
(
pclk
)
,
// input
.
pclk
(
pclk
)
,
// input
.
pclk2x
(
pclk2x
)
,
// input
.
pclk2x
(
pclk2x
)
,
// input
...
@@ -1221,26 +1317,68 @@ module sensor_channel#(
...
@@ -1221,26 +1317,68 @@ module sensor_channel#(
.
cmd_ad
(
cmd_ad
)
,
// input[7:0]
.
cmd_ad
(
cmd_ad
)
,
// input[7:0]
.
cmd_stb
(
cmd_stb
)
,
// input
.
cmd_stb
(
cmd_stb
)
,
// input
.
monochrome
(
HIST_MONOCHROME
)
// input
.
monochrome
(
HIST_MONOCHROME
)
// input
// ,.debug_mclk(debug_hist_mclk[3])
`ifdef
DEBUG_RING
`ifdef
DEBUG_RING
,.
debug_do
(
debug_ring
[
3
])
,
// output
,.
debug_do
(
debug_ring
[
3
])
,
// output
.
debug_sl
(
debug_sl
)
,
// input
.
debug_sl
(
debug_sl
)
,
// input
.
debug_di
(
debug_ring
[
4
])
// input
.
debug_di
(
debug_ring
[
4
])
// input
`endif
`endif
)
;
)
;
else
else
sens_histogram_dummy
sens_histogram_
dummy
_i
(
sens_histogram_dummy
sens_histogram_
3
_i
(
.
hist_rq
(
hist_rq
[
3
])
,
// output
.
hist_rq
(
hist_rq
[
3
])
,
// output
.
hist_do
(
hist_do3
)
,
// output[31:0]
.
hist_do
(
hist_do3
)
,
// output[31:0]
.
hist_dv
(
hist_dv
[
3
])
// output
.
hist_dv
(
hist_dv
[
3
])
// output
`ifdef
DEBUG_RING
`ifdef
DEBUG_RING
,.
debug_do
(
debug_ring
[
3
])
,
// output
,.
debug_do
(
debug_ring
[
3
])
,
// output
.
debug_di
(
debug_ring
[
4
])
// input
.
debug_di
(
debug_ring
[
4
])
// input
`endif
`endif
)
;
// `ifdef USE_PCLK2X
`else
// `ifdef USE_PCLK2X
sens_histogram_snglclk
#(
.
HISTOGRAM_RAM_MODE
(
HISTOGRAM_RAM_MODE
)
,
.
HISTOGRAM_ADDR
(
HISTOGRAM_ADDR3
)
,
.
HISTOGRAM_ADDR_MASK
(
HISTOGRAM_ADDR_MASK
)
,
.
HISTOGRAM_LEFT_TOP
(
HISTOGRAM_LEFT_TOP
)
,
.
HISTOGRAM_WIDTH_HEIGHT
(
HISTOGRAM_WIDTH_HEIGHT
)
`ifdef
DEBUG_RING
,.
DEBUG_CMD_LATENCY
(
DEBUG_CMD_LATENCY
)
`endif
)
sens_histogram_3_i
(
.
mrst
(
mrst
)
,
// input
.
prst
(
prsts
)
,
// input extended to include sensor reset and rst_mmcm
.
pclk
(
pclk
)
,
// input
.
sof
(
gamma_sof_out
)
,
// input
.
eof
(
gamma_eof_out
)
,
// input
.
hact
(
gamma_hact_out
)
,
// input
.
hist_di
(
gamma_pxd_out
)
,
// input[7:0]
.
mclk
(
mclk
)
,
// input
.
hist_en
(
hist_en
[
3
])
,
// input
.
hist_rst
(
!
hist_nrst
[
3
])
,
// input
.
hist_rq
(
hist_rq
[
3
])
,
// output
.
hist_grant
(
hist_gr
[
3
])
,
// input
.
hist_do
(
hist_do3
)
,
// output[31:0]
.
hist_dv
(
hist_dv
[
3
])
,
// output
.
cmd_ad
(
cmd_ad
)
,
// input[7:0]
.
cmd_stb
(
cmd_stb
)
// input
`ifdef
DEBUG_RING
,.
debug_do
(
debug_ring
[
3
])
,
// output
.
debug_sl
(
debug_sl
)
,
// input
.
debug_di
(
debug_ring
[
4
])
// input
`endif
)
;
)
;
//`ifdef DEBUG_RING
else
// assign debug_ring[3] = debug_ring[4]; // just bypass
sens_histogram_snglclk_dummy
sens_histogram_3_i
(
//`endif
.
hist_rq
(
hist_rq
[
3
])
,
// output
.
hist_do
(
hist_do3
)
,
// output[31:0]
.
hist_dv
(
hist_dv
[
3
])
// output
`ifdef
DEBUG_RING
,.
debug_do
(
debug_ring
[
3
])
,
// output
.
debug_di
(
debug_ring
[
4
])
// input
`endif
)
;
`endif
endgenerate
endgenerate
sens_histogram_mux
sens_histogram_mux_i
(
sens_histogram_mux
sens_histogram_mux_i
(
...
...
sensor/sensors393.v
View file @
ea56e79d
...
@@ -283,7 +283,9 @@ module sensors393 #(
...
@@ -283,7 +283,9 @@ module sensors393 #(
// input rst,
// input rst,
// will generate it here
// will generate it here
input
pclk
,
// global clock input, pixel rate (96MHz for MT9P006)
input
pclk
,
// global clock input, pixel rate (96MHz for MT9P006)
`ifdef
USE_PCLK2X
input
pclk2x
,
// global clock input, double pixel rate (192MHz for MT9P006)
input
pclk2x
,
// global clock input, double pixel rate (192MHz for MT9P006)
`endif
input
ref_clk
,
// IODELAY calibration
input
ref_clk
,
// IODELAY calibration
input
dly_rst
,
input
dly_rst
,
input
mrst
,
// @posedge mclk, sync reset
input
mrst
,
// @posedge mclk, sync reset
...
@@ -592,7 +594,9 @@ module sensors393 #(
...
@@ -592,7 +594,9 @@ module sensors393 #(
`endif
`endif
)
sensor_channel_i
(
)
sensor_channel_i
(
.
pclk
(
pclk
)
,
// input
.
pclk
(
pclk
)
,
// input
`ifdef
USE_PCLK2X
.
pclk2x
(
pclk2x
)
,
// input
.
pclk2x
(
pclk2x
)
,
// input
`endif
.
mrst
(
mrst
)
,
// input
.
mrst
(
mrst
)
,
// input
.
prst
(
prst
)
,
// input
.
prst
(
prst
)
,
// input
...
...
system_defines.vh
View file @
ea56e79d
...
@@ -4,6 +4,8 @@
...
@@ -4,6 +4,8 @@
`define PRELOAD_BRAMS
`define PRELOAD_BRAMS
// if HISPI is not defined, parallel sensor interface is used for all channels
// if HISPI is not defined, parallel sensor interface is used for all channels
`define HISPI
`define HISPI
// `define USE_PCLK2X
// `define DEBUG_RING 1
// `define DEBUG_RING 1
`define MEMBRIDGE_DEBUG_WRITE 1
`define MEMBRIDGE_DEBUG_WRITE 1
// Enviroment-dependent options
// Enviroment-dependent options
...
...
util_modules/clocks393.v
View file @
ea56e79d
...
@@ -40,11 +40,12 @@ module clocks393#(
...
@@ -40,11 +40,12 @@ module clocks393#(
parameter
DIVCLK_DIVIDE_PCLK
=
1
,
parameter
DIVCLK_DIVIDE_PCLK
=
1
,
parameter
CLKFBOUT_MULT_PCLK
=
40
,
// 960 MHz
parameter
CLKFBOUT_MULT_PCLK
=
40
,
// 960 MHz
parameter
CLKOUT_DIV_PCLK
=
10
,
// 96MHz
parameter
CLKOUT_DIV_PCLK
=
10
,
// 96MHz
parameter
BUF_CLK1X_PCLK
=
"BUFG"
,
`ifdef
USE_PCLK2X
parameter
CLKOUT_DIV_PCLK2X
=
5
,
// 192 MHz
parameter
CLKOUT_DIV_PCLK2X
=
5
,
// 192 MHz
parameter
PHASE_CLK2X_PCLK
=
0.000
,
parameter
PHASE_CLK2X_PCLK
=
0.000
,
parameter
BUF_CLK1X_PCLK
=
"BUFG"
,
parameter
BUF_CLK1X_PCLK2X
=
"BUFG"
,
parameter
BUF_CLK1X_PCLK2X
=
"BUFG"
,
`endif
parameter
CLKIN_PERIOD_XCLK
=
20
,
// 50MHz
parameter
CLKIN_PERIOD_XCLK
=
20
,
// 50MHz
parameter
DIVCLK_DIVIDE_XCLK
=
1
,
parameter
DIVCLK_DIVIDE_XCLK
=
1
,
parameter
CLKFBOUT_MULT_XCLK
=
20
,
// 50*20=1000 MHz
parameter
CLKFBOUT_MULT_XCLK
=
20
,
// 50*20=1000 MHz
...
@@ -101,7 +102,9 @@ module clocks393#(
...
@@ -101,7 +102,9 @@ module clocks393#(
output
aclk
,
// global clock 50 MHz (used for maxi0)
output
aclk
,
// global clock 50 MHz (used for maxi0)
output
hclk
,
// global clock 150MHz (used for afi*, saxi*)
output
hclk
,
// global clock 150MHz (used for afi*, saxi*)
output
pclk
,
// global clock for sensors (now 96MHz), based on external clock generator
output
pclk
,
// global clock for sensors (now 96MHz), based on external clock generator
`ifdef
USE_PCLK2X
output
pclk2x
,
// global clock for sennors, 2x frequency (now 192MHz)
output
pclk2x
,
// global clock for sennors, 2x frequency (now 192MHz)
`endif
output
xclk
,
// global clock for compressor (now 100MHz)
output
xclk
,
// global clock for compressor (now 100MHz)
output
xclk2x
,
// global clock for compressor, 2x frequency (now 200MHz)
output
xclk2x
,
// global clock for compressor, 2x frequency (now 200MHz)
output
sync_clk
,
// global clock for camsync module (96 MHz for 353 compatibility - switch to 100MHz)?
output
sync_clk
,
// global clock for camsync module (96 MHz for 353 compatibility - switch to 100MHz)?
...
@@ -203,16 +206,24 @@ module clocks393#(
...
@@ -203,16 +206,24 @@ module clocks393#(
.
DIVCLK_DIVIDE
(
DIVCLK_DIVIDE_PCLK
)
,
.
DIVCLK_DIVIDE
(
DIVCLK_DIVIDE_PCLK
)
,
.
CLKFBOUT_MULT
(
CLKFBOUT_MULT_PCLK
)
,
.
CLKFBOUT_MULT
(
CLKFBOUT_MULT_PCLK
)
,
.
CLKOUT_DIV_CLK1X
(
CLKOUT_DIV_PCLK
)
,
.
CLKOUT_DIV_CLK1X
(
CLKOUT_DIV_PCLK
)
,
.
CLKOUT_DIV_CLK2X
(
CLKOUT_DIV_PCLK2X
)
,
.
BUF_CLK1X
(
BUF_CLK1X_PCLK
)
`ifdef
USE_PCLK2X
,.
CLKOUT_DIV_CLK2X
(
CLKOUT_DIV_PCLK2X
)
,
.
PHASE_CLK2X
(
PHASE_CLK2X_PCLK
)
,
.
PHASE_CLK2X
(
PHASE_CLK2X_PCLK
)
,
.
BUF_CLK1X
(
BUF_CLK1X_PCLK
)
,
.
BUF_CLK2X
(
BUF_CLK1X_PCLK2X
)
.
BUF_CLK2X
(
BUF_CLK1X_PCLK2X
)
`else
,.
BUF_CLK2X
(
"NONE"
)
`endif
)
dual_clock_pclk_i
(
)
dual_clock_pclk_i
(
.
rst
(
async_rst
||
reset_clk
[
1
])
,
// input
.
rst
(
async_rst
||
reset_clk
[
1
])
,
// input
.
clk_in
(
ffclk0
)
,
// input
.
clk_in
(
ffclk0
)
,
// input
.
pwrdwn
(
pwrdwn_clk
[
1
])
,
// input
.
pwrdwn
(
pwrdwn_clk
[
1
])
,
// input
.
clk1x
(
pclk
)
,
// output
.
clk1x
(
pclk
)
,
// output
`ifdef
USE_PCLK2X
.
clk2x
(
pclk2x
)
,
// output
.
clk2x
(
pclk2x
)
,
// output
`else
.
clk2x
()
,
// output not connected
`endif
.
locked
(
locked
[
1
])
// output
.
locked
(
locked
[
1
])
// output
)
;
)
;
...
...
x393.v
View file @
ea56e79d
...
@@ -196,8 +196,9 @@ module x393 #(
...
@@ -196,8 +196,9 @@ module x393 #(
//TODO: Create missing clocks
//TODO: Create missing clocks
wire
pclk
;
// global clock, sensor pixel rate (96 MHz)
wire
pclk
;
// global clock, sensor pixel rate (96 MHz)
`ifdef
USE_PCLK2X
wire
pclk2x
;
// global clock, sensor double pixel rate (192 MHz)
wire
pclk2x
;
// global clock, sensor double pixel rate (192 MHz)
`endif
// compressor pixel rate can be adjusted independently
// compressor pixel rate can be adjusted independently
wire
xclk
;
// global clock, compressor pixel rate (100 MHz)?
wire
xclk
;
// global clock, compressor pixel rate (100 MHz)?
wire
xclk2x
;
// global clock, compressor double pixel rate (200 MHz)
wire
xclk2x
;
// global clock, compressor double pixel rate (200 MHz)
...
@@ -413,6 +414,7 @@ module x393 #(
...
@@ -413,6 +414,7 @@ module x393 #(
wire
[
3
:
0
]
sens_buf_rd
;
// (), // input
wire
[
3
:
0
]
sens_buf_rd
;
// (), // input
wire
[
255
:
0
]
sens_buf_dout
;
// (), // output[63:0]
wire
[
255
:
0
]
sens_buf_dout
;
// (), // output[63:0]
wire
[
3
:
0
]
sens_page_written
;
// single mclk pulse: buffer page (full or partial) is written to the memory buffer
wire
[
3
:
0
]
sens_page_written
;
// single mclk pulse: buffer page (full or partial) is written to the memory buffer
// TODO: Add counter(s) to count sens_xfer_skipped pulses
wire
[
3
:
0
]
sens_xfer_skipped
;
// single mclk pulse on every skipped (not written) block to record error statistics
wire
[
3
:
0
]
sens_xfer_skipped
;
// single mclk pulse on every skipped (not written) block to record error statistics
wire
trigger_mode
;
// (), // input
wire
trigger_mode
;
// (), // input
wire
[
3
:
0
]
trig_in
;
// input[3:0]
wire
[
3
:
0
]
trig_in
;
// input[3:0]
...
@@ -1597,7 +1599,9 @@ assign axi_grst = axi_rst_pre;
...
@@ -1597,7 +1599,9 @@ assign axi_grst = axi_rst_pre;
)
sensors393_i
(
)
sensors393_i
(
// .rst (axi_rst), // input
// .rst (axi_rst), // input
.
pclk
(
pclk
)
,
// input
.
pclk
(
pclk
)
,
// input
`ifdef
USE_PCLK2X
.
pclk2x
(
pclk2x
)
,
// input
.
pclk2x
(
pclk2x
)
,
// input
`endif
.
ref_clk
(
ref_clk
)
,
// input
.
ref_clk
(
ref_clk
)
,
// input
.
dly_rst
(
idelay_ctrl_reset
)
,
// input
.
dly_rst
(
idelay_ctrl_reset
)
,
// input
.
mrst
(
mrst
)
,
// input
.
mrst
(
mrst
)
,
// input
...
@@ -2164,10 +2168,12 @@ assign axi_grst = axi_rst_pre;
...
@@ -2164,10 +2168,12 @@ assign axi_grst = axi_rst_pre;
.
DIVCLK_DIVIDE_PCLK
(
DIVCLK_DIVIDE_PCLK
)
,
.
DIVCLK_DIVIDE_PCLK
(
DIVCLK_DIVIDE_PCLK
)
,
.
CLKFBOUT_MULT_PCLK
(
CLKFBOUT_MULT_PCLK
)
,
.
CLKFBOUT_MULT_PCLK
(
CLKFBOUT_MULT_PCLK
)
,
.
CLKOUT_DIV_PCLK
(
CLKOUT_DIV_PCLK
)
,
.
CLKOUT_DIV_PCLK
(
CLKOUT_DIV_PCLK
)
,
.
BUF_CLK1X_PCLK
(
BUF_CLK1X_PCLK
)
,
`ifdef
USE_PCLK2X
.
CLKOUT_DIV_PCLK2X
(
CLKOUT_DIV_PCLK2X
)
,
.
CLKOUT_DIV_PCLK2X
(
CLKOUT_DIV_PCLK2X
)
,
.
PHASE_CLK2X_PCLK
(
PHASE_CLK2X_PCLK
)
,
.
PHASE_CLK2X_PCLK
(
PHASE_CLK2X_PCLK
)
,
.
BUF_CLK1X_PCLK
(
BUF_CLK1X_PCLK
)
,
.
BUF_CLK1X_PCLK2X
(
BUF_CLK1X_PCLK2X
)
,
.
BUF_CLK1X_PCLK2X
(
BUF_CLK1X_PCLK2X
)
,
`endif
.
CLKIN_PERIOD_XCLK
(
CLKIN_PERIOD_XCLK
)
,
.
CLKIN_PERIOD_XCLK
(
CLKIN_PERIOD_XCLK
)
,
.
DIVCLK_DIVIDE_XCLK
(
DIVCLK_DIVIDE_XCLK
)
,
.
DIVCLK_DIVIDE_XCLK
(
DIVCLK_DIVIDE_XCLK
)
,
.
CLKFBOUT_MULT_XCLK
(
CLKFBOUT_MULT_XCLK
)
,
.
CLKFBOUT_MULT_XCLK
(
CLKFBOUT_MULT_XCLK
)
,
...
@@ -2218,7 +2224,9 @@ assign axi_grst = axi_rst_pre;
...
@@ -2218,7 +2224,9 @@ assign axi_grst = axi_rst_pre;
.
aclk
(
axi_aclk
)
,
// output
.
aclk
(
axi_aclk
)
,
// output
.
hclk
(
hclk
)
,
// output
.
hclk
(
hclk
)
,
// output
.
pclk
(
pclk
)
,
// output
.
pclk
(
pclk
)
,
// output
`ifdef
USE_PCLK2X
.
pclk2x
(
pclk2x
)
,
// output
.
pclk2x
(
pclk2x
)
,
// output
`endif
.
xclk
(
xclk
)
,
// output
.
xclk
(
xclk
)
,
// output
.
xclk2x
(
xclk2x
)
,
// output
.
xclk2x
(
xclk2x
)
,
// output
.
sync_clk
(
camsync_clk
)
,
// output
.
sync_clk
(
camsync_clk
)
,
// output
...
...
x393_testbench03.sav
View file @
ea56e79d
[*]
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Thu Oct 22
19:01:31
2015
[*] Thu Oct 22
21:56:23
2015
[*]
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151022
091046904
.fst"
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151022
145451521
.fst"
[dumpfile_mtime] "Thu Oct 22
15:49:46
2015"
[dumpfile_mtime] "Thu Oct 22
21:32:59
2015"
[dumpfile_size] 27
7840396
[dumpfile_size] 27
4609443
[savefile] "/home/andrey/git/x393/x393_testbench03.sav"
[savefile] "/home/andrey/git/x393/x393_testbench03.sav"
[timestart]
3184000
0
[timestart] 0
[size] 1
823
1180
[size] 1
920
1180
[pos]
1917
0
[pos]
0
0
*-2
4.043108 75747300
178682388 184032388 75106570 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-2
5.223515 83887388
178682388 184032388 75106570 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03.
[treeopen] x393_testbench03.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].
...
@@ -28,8 +28,10 @@
...
@@ -28,8 +28,10 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[0].sens_hispi_fifo_i.
...
@@ -40,19 +42,20 @@
...
@@ -40,19 +42,20 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.hispi_lane[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_10398_i.sens_hispi12l4_i.sens_hispi_din_i.din_block[0].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_0_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[sst_width]
441
[sst_width]
346
[signals_width] 3
2
2
[signals_width] 3
6
2
[sst_expanded] 1
[sst_expanded] 1
[sst_vpaned_height] 670
[sst_vpaned_height] 670
@820
@820
...
@@ -629,7 +632,7 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
...
@@ -629,7 +632,7 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.se
-
-
@1000200
@1000200
-sens_10398
-sens_10398
@
c
00200
@
8
00200
-sensor_channel_0
-sensor_channel_0
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.mclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.mclk
...
@@ -712,31 +715,16 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hi
...
@@ -712,31 +715,16 @@ x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hi
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_dvalid
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_dvalid
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_data[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.hist_data[31:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
@200
@200
-hist_debug
-hist_debug
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.en_rq_start
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@1401200
-group_end
@800200
@800200
-channels_1_3
-channels_1_3
@c00028
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@1401200
-group_end
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
@1000200
@1000200
-channels_1_3
-channels_1_3
@28
@28
...
@@ -908,7 +896,6 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i
...
@@ -908,7 +896,6 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i
-
-
@1000200
@1000200
-mcntr_linear_rw_sensor0
-mcntr_linear_rw_sensor0
@1401200
-sensor_channel_0
-sensor_channel_0
@800200
@800200
-DDR3
-DDR3
...
@@ -977,7 +964,7 @@ x393_testbench03.simul_sensor12bits_2_i.stopped
...
@@ -977,7 +964,7 @@ x393_testbench03.simul_sensor12bits_2_i.stopped
x393_testbench03.simul_sensor12bits_2_i.stoppedd
x393_testbench03.simul_sensor12bits_2_i.stoppedd
@1401200
@1401200
-simul_sensor_0
-simul_sensor_0
@
8
00200
@
c
00200
-PX1
-PX1
@28
@28
x393_testbench03.PX1_MCLK_PRE
x393_testbench03.PX1_MCLK_PRE
...
@@ -1011,9 +998,9 @@ x393_testbench03.PX1_MRST
...
@@ -1011,9 +998,9 @@ x393_testbench03.PX1_MRST
x393_testbench03.PX1_OFST
x393_testbench03.PX1_OFST
x393_testbench03.PX1_SHUTTER
x393_testbench03.PX1_SHUTTER
x393_testbench03.PX1_VACT
x393_testbench03.PX1_VACT
@1
000
200
@1
401
200
-PX1
-PX1
@
c
00200
@
8
00200
-par_hispi_sel
-par_hispi_sel
@28
@28
x393_testbench03.par12_hispi_psp4l0_i.pclk
x393_testbench03.par12_hispi_psp4l0_i.pclk
...
@@ -1073,8 +1060,9 @@ x393_testbench03.par12_hispi_psp4l0_i.simul_clk_div_mult_i.clk_out
...
@@ -1073,8 +1060,9 @@ x393_testbench03.par12_hispi_psp4l0_i.simul_clk_div_mult_i.clk_out
x393_testbench03.par12_hispi_psp4l0_i.simul_clk_div_mult_i.en
x393_testbench03.par12_hispi_psp4l0_i.simul_clk_div_mult_i.en
@1401200
@1401200
-clk_mult_div
-clk_mult_div
@1000200
-par_hispi_sel
-par_hispi_sel
@
c
00200
@
8
00200
-par_hspi_0
-par_hspi_0
@28
@28
x393_testbench03.par12_hispi_psp4l0_i.clk_n
x393_testbench03.par12_hispi_psp4l0_i.clk_n
...
@@ -1182,7 +1170,7 @@ x393_testbench03.par12_hispi_psp4l0_i.sdata_dly[3:0]
...
@@ -1182,7 +1170,7 @@ x393_testbench03.par12_hispi_psp4l0_i.sdata_dly[3:0]
x393_testbench03.par12_hispi_psp4l0_i.sof_sol_sent
x393_testbench03.par12_hispi_psp4l0_i.sof_sol_sent
x393_testbench03.par12_hispi_psp4l0_i.vact
x393_testbench03.par12_hispi_psp4l0_i.vact
x393_testbench03.par12_hispi_psp4l0_i.vact_d
x393_testbench03.par12_hispi_psp4l0_i.vact_d
@1
401
200
@1
000
200
-par_hspi_0
-par_hspi_0
@800200
@800200
-scheduler16
-scheduler16
...
@@ -1582,315 +1570,174 @@ x393_testbench03.x393_i.membridge_i.start_mclk
...
@@ -1582,315 +1570,174 @@ x393_testbench03.x393_i.membridge_i.start_mclk
@1000200
@1000200
-membridge
-membridge
-mcntr_linear_rw_chn1
-mcntr_linear_rw_chn1
@200
-
@800200
@800200
-sens_hist_sngl0
-hisogram_channel00
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.bayer_pclk[1:0]
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.cmd_ad[7:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.cmd_stb
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.en
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.en_mclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.en_new
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.en_rq_start
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.eof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.eq_prev
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.eq_prev_d3
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.eq_prev_prev
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.eq_prev_prev_d2
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.frame_active
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hact
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hact_d[1:0]
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hcntr[15:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hcntr_zero_w
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_bank_mclk
@22
@29
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.height_m1[15:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_bank_pclk
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_bank_mclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_bank_pclk
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_do[31:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_done
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_done_mclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.en_a_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_dv
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_en
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_en_pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_grant
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_new_even[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.addr_a_even[9:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_new_odd[31:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_out
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.en_a_odd
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_out_d
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.addr_a_odd[9:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.data_out_a_even[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.data_out_a_odd[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.data_in_a[31:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_re[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.we_a_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rq
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.genblk1.sens_hist_ram_snglclk_32_i.we_a_odd
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rq_r
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev_d3
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev_prev_d2
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rst_pclk
@200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_xfer_busy
-
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_xfer_done
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_xfer_done_mclk
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hor_woi[6:0]
@1401200
-group_end
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.left[15:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.left_margin
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rq
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.line_start_w
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_grant
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_out
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.lt_mclk[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_raddr[9:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_do[31:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.mclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_dv
@c00022
@1000200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
-hisogram_channel00
@28
@c00200
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
-histogram_chn0_all
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_even[6:0]
@1401200
-group_end
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.memen_odd[6:0]
@1401200
-group_end
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.mrst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.bayer_pclk[1:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.odd_pix
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.pio_addr[1:0]
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
sens_histogram_snglclk_chn0_0_i.pio_data[31
:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
genblk1.sens_histogram_0_i.cmd_ad[7
:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.pio_stb
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.cmd_stb
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.pre_first_line
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.en
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.prst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.en_mclk
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.en_new
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_di[7:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.en_rq_start
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.px_d0[7:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.px_d2[7:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.px_d4[7:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev_d3
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.px_d5[7:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev_prev
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.eq_prev_prev_d2
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.frame_active
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hact
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hact_d[1:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
(7)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
(8)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
@1401200
-group_end
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_odd[8:0]
@800028
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.bayer_pclk[1:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.bayer_pclk[1:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.bayer_pclk[1:0]
@1001200
-group_end
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
sens_histogram_snglclk_chn0_0_i.r0[31
:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
genblk1.sens_histogram_0_i.hcntr[15
:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
sens_histogram_snglclk_chn0_0_i.r0_sel
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
genblk1.sens_histogram_0_i.hcntr_zero_w
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
sens_histogram_snglclk_chn0_0_i.r1[31
:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
genblk1.sens_histogram_0_i.height_m1[15
:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.r1_sat
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_bank_mclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_bank_pclk
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.r2[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_di[7:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.r3[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_do[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.r_load[3:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.regen_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_done
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.regen_odd
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_done_mclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.rwen_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_dv
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.rwen_odd
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_en
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.set_left_top_pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_en_pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.set_left_top_w
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_grant
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.set_ra_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.set_ra_odd
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.set_wa_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.set_wa_odd
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.set_width_height_pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.set_width_height_w
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.sof
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.top[15:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_new_even[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_new_odd[31:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.top_margin
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_out
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_out_d
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
sens_histogram_snglclk_chn0_0_i.vcntr[15
:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
genblk1.sens_histogram_0_i.hist_raddr[9
:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.vcntr_zero_w
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.vert_woi
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.wait_readout
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_re_odd
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rq
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rq_r
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rst_pclk
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_even[8:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_even[8:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rwaddr_odd[8:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_rwaddr_odd[8:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.r2[31:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.we_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_xfer_busy
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.we_odd
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_xfer_done
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.hist_xfer_done_mclk
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
sens_histogram_snglclk_chn0_0_i.wh_mclk[31
:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
genblk1.sens_histogram_0_i.hor_woi[6
:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
sens_histogram_snglclk_chn0_0_i.width_m1
[15:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
genblk1.sens_histogram_0_i.left
[15:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.eq_prev_d3
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.left_margin
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.eq_prev_prev_d2
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.line_start_w
@200
-
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_bank_pclk
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.addr_a_even[9
:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
genblk1.sens_histogram_0_i.lt_mclk[31
:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.en_a_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
genblk1.sens_histogram_0_i.mclk
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.addr_a_odd[9:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_even[6:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.memen_odd[6:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.en_a_odd
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.mrst
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.regen_a_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.odd_pix
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.regen_a_odd
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.we_a_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.pio_addr[1:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.we_a_odd
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.data_out_a_even[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.pio_data[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.data_out_a_odd[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.genblk1.sens_hist_ram_snglclk_32_i.data_in_a[31:0]
@200
-
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_out
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_re[2:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_re[2:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_re[2:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_re[2:0]
@1401200
-group_end
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(3)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(4)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(5)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(6)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(7)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(8)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
(9)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_raddr[9:0]
@1401200
-group_end
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_rq
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.pio_stb
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_grant
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.pre_first_line
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.prst
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_do[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.px_d0[7:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.px_d2[7:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_snglclk_chn0_0_i.hist_dv
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.px_d4[7:0]
@1000200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.px_d5[7:0]
-sens_hist_sngl0
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r0[31:0]
@800200
-histogram_chn0
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_bank_pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.r0_sel
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pclk2x
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_
i.inc_sat
[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_
0_i.r1
[31:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_
i.hist_we
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_
0_i.r1_sat
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_
i.hist_rwaddr[9
:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_
0_i.r2[31
:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_
i.hist_di[7
:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_
0_i.r3[31
:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_
i.left[15
:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_
0_i.r_load[3
:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.left_margin
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.regen_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hcntr_zero_w
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.regen_odd
@800028
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.rwen_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact_d[1:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.rwen_odd
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.set_left_top_pclk
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact_d[1:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.set_left_top_w
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hact_d[1:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.set_ra_even
@1001200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.set_ra_odd
-group_end
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.set_wa_even
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.set_wa_odd
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hor_woi
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.set_width_height_pclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.pulse_cross_clock_hlstart_start_i.in_pulse
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.set_width_height_w
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hlstart
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.sof
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hor_woi_2x
@800022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_
i.pxd_2x[7
:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_
0_i.top[15
:0]
@28
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.top_margin
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.woi[2:0]
@29
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.bayer_pclk[1:0]
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.mclk
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_out
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_rq
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_grant
@c00022
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@28
(0)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(1)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
(2)x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_re[2:0]
@1401202
-group_end
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_
i.hist_raddr[9
:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_
0_i.vcntr[15
:0]
@28
@28
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_dv
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.vcntr_zero_w
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.vert_woi
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.wait_readout
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.we_even
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.we_odd
@22
@22
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_i.hist_do[31:0]
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.wh_mclk[31:0]
@1001200
x393_testbench03.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.width_m1[15:0]
-group_end
@1401200
@1000200
-histogram_chn0_all
-histogram_chn0
@200
-
[pattern_trace] 1
[pattern_trace] 1
[pattern_trace] 0
[pattern_trace] 0
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