Commit ea4d0389 authored by Andrey Filippov's avatar Andrey Filippov

code formatting

parent ef24a9b6
...@@ -228,13 +228,12 @@ module dct2d8x8_chen#( ...@@ -228,13 +228,12 @@ module dct2d8x8_chen#(
// Just for debugging/comparing with old 1-d DCT: // Just for debugging/comparing with old 1-d DCT:
`ifdef SIMULATION // no sense to synthesize it `ifdef SIMULATION // no sense to synthesize it
`ifdef DEBUG_DCT1D `ifdef DEBUG_DCT1D
wire [TRANSPOSE_WIDTH-1:0] dbg_d_out; wire [TRANSPOSE_WIDTH-1:0] dbg_d_out;
//wire [15:0] dbg_d_out13=dbg_d_out[7 +: 16] ; //wire [15:0] dbg_d_out13=dbg_d_out[7 +: 16] ;
wire dbg_dv; wire dbg_dv;
wire dbg_en_out; wire dbg_en_out;
wire dbg_pre_first_out; wire dbg_pre_first_out;
dct1d_chen_reorder_out #( dct1d_chen_reorder_out #(
.WIDTH (TRANSPOSE_WIDTH) .WIDTH (TRANSPOSE_WIDTH)
) dct1d_chen_reorder_out_dbg_i ( ) dct1d_chen_reorder_out_dbg_i (
...@@ -248,7 +247,7 @@ wire dbg_pre_first_out; ...@@ -248,7 +247,7 @@ wire dbg_pre_first_out;
.dv (dbg_dv), // output reg .dv (dbg_dv), // output reg
.en_out (dbg_en_out) // output reg .en_out (dbg_en_out) // output reg
); );
`endif `endif
`endif `endif
endmodule endmodule
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