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Commit e9862dab authored by Andrey Filippov's avatar Andrey Filippov
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Converting event_logger to use serial timestamps and 4 sesnor channels

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logger/buf_xclk_mclk16_393.v
View file @ e9862dab
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: move data from xclk to mclk domain
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* buf_xclk_mclk16_393.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -21,63 +21,46 @@
`timescale 1ns/1ps
module buf_xclk_mclk16_393(
xclk, // posedge
mclk, // posedge
rst, // @posedge xclk
din,
din_stb,
dout,
dout_stb);
input mclk, // system clock, posedge
input xclk, // half frequency (80 MHz nominal)
input rst, // @posedge xclk reset module
input [15:0] din,
input din_stb,
output reg [15:0] dout,
output reg dout_stb);
input xclk; // half frequency (80 MHz nominal)
input mclk; // system clock - frequency (160 MHz nominal)
input rst; // reset module
input [15:0] din;
input din_stb;
output [15:0] dout;
output dout_stb;
reg [1:0] wa;
reg [1:0] wa_mclk;
reg [1:0] wa_mclk_d;
reg rst_mclk;
reg [1:0] ra;
reg [1:0] ra_next;
reg inc_ra;
wire [15:0] pre_dout;
reg [1:0] wa;
reg [1:0] wa_mclk;
reg [1:0] wa_mclk_d;
reg rst_mclk;
reg [1:0] ra;
reg [1:0] ra_next;
reg inc_ra;
wire [15:0] pre_dout;
reg [15:0] dout;
reg dout_stb;
always @ (posedge xclk) begin
if (rst) wa[1:0] <= 2'h0;
else if (din_stb) wa[1:0] <={wa[0],~wa[1]};
end
always @ (posedge mclk) begin
wa_mclk[1:0] <= wa[1:0];
wa_mclk_d[1:0] <= wa_mclk[1:0];
rst_mclk<= rst;
if (rst_mclk) ra[1:0] <= 2'h0;
else ra[1:0] <= inc_ra?{ra[0],~ra[1]}:{ra[1],ra[0]};
if (rst_mclk) ra_next[1:0] <= 2'h1;
else ra_next[1:0] <= inc_ra?{~ra[1],~ra[0]}:{ra[0],~ra[1]};
inc_ra <= !rst && (ra[1:0]!=wa_mclk_d[1:0]) && (!inc_ra || (ra_next[1:0]!=wa_mclk_d[1:0]));
dout_stb <= inc_ra;
if (inc_ra) dout[15:0] <= pre_dout[15:0];
end
myRAM_WxD_D #( .DATA_WIDTH(16),.DATA_DEPTH(2))
i_fifo_4x16 (.D(din[15:0]),
.WE(din_stb),
.clk(xclk),
.AW(wa[1:0]),
.AR(ra[1:0]),
.QW(),
.QR(pre_dout[15:0]));
endmodule
always @ (posedge xclk) begin
if (rst) wa[1:0] <= 2'h0;
else if (din_stb) wa[1:0] <={wa[0],~wa[1]};
end
always @ (posedge mclk) begin
wa_mclk[1:0] <= wa[1:0];
wa_mclk_d[1:0] <= wa_mclk[1:0];
rst_mclk<= rst;
if (rst_mclk) ra[1:0] <= 2'h0;
else ra[1:0] <= inc_ra?{ra[0],~ra[1]}:{ra[1],ra[0]};
if (rst_mclk) ra_next[1:0] <= 2'h1;
else ra_next[1:0] <= inc_ra?{~ra[1],~ra[0]}:{ra[0],~ra[1]};
inc_ra <= !rst && (ra[1:0]!=wa_mclk_d[1:0]) && (!inc_ra || (ra_next[1:0]!=wa_mclk_d[1:0]));
dout_stb <= inc_ra;
if (inc_ra) dout[15:0] <= pre_dout[15:0];
end
reg [15:0] fifo_4x16_ram[0:3];
always @ (posedge xclk) if (din_stb) fifo_4x16_ram[wa[1:0]] <= din[15:0];
assign pre_dout[15:0] = fifo_4x16_ram[ra[1:0]];
endmodule
logger/event_logger.v
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logger/imu_exttime393.v
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logger/imu_message393.v
View file @ e9862dab
......@@ -4,7 +4,7 @@
* Author: andrey
* Description:
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* imu_message393.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......@@ -27,73 +27,58 @@ de-assert the trig input - message with the timestamp will be logged
fixed-length de-noise circuitry with latency 256*T(xclk) (~3usec)
*/
module imu_message393 ( sclk, // system clock, negedge
xclk, // half frequency (80 MHz nominal)
we, // write enable for registers to log (@negedge sclk), with lower data half
wa, // write address for register (4 bits, @negedge sclk)
di, // 16-bit data in multiplexed
en, // enable module operation, if 0 - reset
trig, // leading edge - sample time, trailing set rdy
ts, // timestamop request
rdy, // data ready
rd_stb, // data read strobe (increment address)
rdata); // data out (16 bits)
module imu_message393 (
input mclk, // system clock, negedge TODO:COnvert to posedge!
input xclk, // half frequency (80 MHz nominal)
input we, // write enable for registers to log (@negedge mclk), with lower data half
input [3:0] wa, // write address for register (4 bits, @negedge mclk)
// input [15:0] di, // 16-bit data in multiplexed
input [31:0] din, // 32-bit data in, non-multiplexed
input en, // enable module operation, if 0 - reset
input trig, // leading edge - sample time, trailing set rdy
output ts, // timestamop request
output rdy, // data ready
input rd_stb, // data read strobe (increment address)
output [15:0] rdata); // data out (16 bits)
input sclk; // system clock, negedge
input xclk; // half frequency (80 MHz nominal)
input we; // write enable for registers to log (@negedge sclk)
input [3:0] wa; // write address for register (4 bits, @negedge sclk)
input [15:0] di; // 16-bit data in (32 multiplexed)
input en; // enable
input trig; // leading edge - sample time, trailing set rdy
output ts; // timestamp request
output rdy; // encoded nmea data ready
input rd_stb; // encoded nmea data read strobe (increment address)
output [15:0] rdata; // encoded data (16 bits)
reg [ 4:0] raddr;
reg rdy=1'b0;
reg we_d;
reg [ 4:1] waddr;
reg [ 2:0] trig_d;
reg [ 7:0] denoise_count;
reg [ 1:0] trig_denoise;
reg ts;
reg [15:0] di_d;
always @ (negedge sclk) begin
di_d[15:0] <= di[15:0];
waddr[4:1] <= wa[3:0];
we_d <=we;
end
always @ (posedge xclk) begin
if (!en) trig_d[2:0] <= 3'h0;
else trig_d[2:0] <= {trig_d[1:0], trig};
if (!en) trig_denoise[0] <= 1'b0;
else if (denoise_count[7:0]==8'h0) trig_denoise[0] <= trig_d[2];
if (trig_d[2]==trig_denoise[0]) denoise_count[7:0] <= 8'hff;
else denoise_count[7:0] <= denoise_count[7:0] - 1;
trig_denoise[1] <= trig_denoise[0];
ts <= !trig_denoise[1] && trig_denoise[0];
if (!en || ts) raddr[4:0] <= 5'h0;
else if (rd_stb) raddr[4:0] <= raddr[4:0] + 1;
if (ts || (rd_stb && (raddr[4:0]==5'h1b)) || !en) rdy <= 1'b0;
else if (trig_denoise[1] && !trig_denoise[0]) rdy <= 1'b1;
end
myRAM_WxD_D #( .DATA_WIDTH(16),.DATA_DEPTH(5))
i_odbuf (.D(di_d[15:0]),
.WE(we | we_d),
.clk(~sclk),
.AW({waddr[4:1],we_d}),
.AR(raddr[4:0]),
.QW(),
.QR(rdata[15:0]));
endmodule
reg [ 4:0] raddr;
reg rdy_r=1'b0;
reg [ 2:0] trig_d;
reg [ 7:0] denoise_count;
reg [ 1:0] trig_denoise;
reg ts_r;
assign rdy = rdy_r;
assign ts = ts_r;
always @ (posedge xclk) begin
if (!en) trig_d[2:0] <= 3'h0;
else trig_d[2:0] <= {trig_d[1:0], trig};
if (!en) trig_denoise[0] <= 1'b0;
else if (denoise_count[7:0]==8'h0) trig_denoise[0] <= trig_d[2];
if (trig_d[2]==trig_denoise[0]) denoise_count[7:0] <= 8'hff;
else denoise_count[7:0] <= denoise_count[7:0] - 1;
trig_denoise[1] <= trig_denoise[0];
ts_r <= !trig_denoise[1] && trig_denoise[0];
if (!en || ts_r) raddr[4:0] <= 5'h0;
else if (rd_stb) raddr[4:0] <= raddr[4:0] + 1;
if (ts_r || (rd_stb && (raddr[4:0]==5'h1b)) || !en) rdy_r <= 1'b0;
else if (trig_denoise[1] && !trig_denoise[0]) rdy_r <= 1'b1;
end
reg [31:0] odbuf0_ram[0:15];
wire [31:0] odbuf0_ram_out;
always @ (posedge mclk) if (we) begin
odbuf0_ram[wa[3:0]] <= din[31:0];
end
assign odbuf0_ram_out = odbuf0_ram[raddr[4:1]];
assign rdata[15:0] = raddr[0] ? odbuf0_ram_out[15:0] : odbuf0_ram_out[31:16];
endmodule
logger/imu_spi393.v
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logger/imu_timestamps393.v
View file @ e9862dab
......@@ -4,7 +4,7 @@
* Author: andrey
* Description: Acquire timestmps for events
*
* Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .
* Copyright (c) 2015 Elphel, Inc.
* imu_timestamps393.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
......
logger/logger_arbiter393.v
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logger/nmea_decoder393.v
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logger/rs232_rcv393.v
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timing/timestamp_fifo.v
View file @ e9862dab
......@@ -30,7 +30,7 @@ module timestamp_fifo(
input pre_stb, // marks pre-first input byte (s0,s1,s2,s3,u0,u1,u2,u3)
input [7:0] din, // data in - valid for 8 cycles after pre_stb
input aclk, // clock to synchronize advance puls
input aclk, // clock to synchronize "advance" commands
input advance, // @aclk advance registers
input rclk, // output clock
......@@ -65,11 +65,11 @@ module timestamp_fifo(
always @(posedge rst or posedge rclk) begin
if (rst) snd <= 0;
else if (rstb) snd <= 1;
else if (&rpntr[2:0]) snd <= 0;
else if (&rpntr[2:1]) snd <= 0; // at count 6
if (rst) rpntr[2:0] <= 0;
else if (!snd) rpntr[2:0] <= 0;
else rpntr[2:0] <= rpntr[2:0] + 1;
if (rst) rpntr[2:0] <= 0;
else if (!snd && !rstb) rpntr[2:0] <= 0;
else rpntr[2:0] <= rpntr[2:0] + 1;
if (snd) dout <= fifo_ram[rpntr];
end
......
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