debugging command/address timing adjustment (e4dae58e) · Commits · Elphel / x393

py393/args

+0 −1

Original line number	Original line	Diff line number	Diff line
	-v
	-d TARGET_MODE=1		-d TARGET_MODE=1
	-f ../system_defines.vh		-f ../system_defines.vh
	-f ../includes/x393_parameters.vh ../includes/x393_cur_params_target.vh ../includes/x393_localparams.vh		-f ../includes/x393_parameters.vh ../includes/x393_cur_params_target.vh ../includes/x393_localparams.vh

py393/test_mcntrl.py

+11 −3

Original line number	Original line	Diff line number	Diff line
	@@ -61,7 +61,7 @@ __version__ = 0.1
	__date__ = '2015-03-01'		__date__ = '2015-03-01'
	__updated__ = '2015-03-01'		__updated__ = '2015-03-01'

	DEBUG = 1		DEBUG = 0 # 1
	TESTRUN = 0		TESTRUN = 0
	PROFILE = 0		PROFILE = 0
	QUIET=1 # more try/excepts		QUIET=1 # more try/excepts
	@@ -223,6 +223,14 @@ USAGE
	#print("--- commands=%s"% str(args.commands))		#print("--- commands=%s"% str(args.commands))
	# paths = args.paths		# paths = args.paths
	verbose = args.verbose		verbose = args.verbose
			if not verbose:
			verbose=0
			print("args=%s"%(str(args)))
			print("sys.argv=%s"%(str(sys.argv)))
			print("DEBUG=%s"%(str(DEBUG)))
			print ("verbose=%d"%verbose)


	paths=[]		paths=[]
	if (args.paths):		if (args.paths):
	for group in args.paths:		for group in args.paths:
	@@ -247,7 +255,7 @@ USAGE
	preDefines[kv[0].strip("`")]=kv[1]		preDefines[kv[0].strip("`")]=kv[1]
	#print("+++ defines=%s"% str(preDefines))		#print("+++ defines=%s"% str(preDefines))

	if verbose > 0:		if verbose > -1: # always
	# print("Verbose mode on "+hex(verbose))		# print("Verbose mode on "+hex(verbose))
	args.parameters.append(['VERBOSE=%d'%verbose]) # add as verilog parameter		args.parameters.append(['VERBOSE=%d'%verbose]) # add as verilog parameter

py393/vrlg.py

+9 −5

Original line number	Original line	Diff line number	Diff line
	@@ -44,15 +44,11 @@ def set_name_field(vname,
	<fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)		<fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)
	<value> value to set the specified byte to		<value> value to set the specified byte to
	"""		"""
	# v=vrlg.__dict__[vname]
	v=globals()[vname]		v=globals()[vname]
	# print ("old value for %s is %s"%(vname,str(vrlg.__dict__[vname])))
	mask = 0xff << (8*fieldIndex)		mask = 0xff << (8*fieldIndex)
	val = value << (8*fieldIndex)		val = value << (8*fieldIndex)
	v = ((v ^ val) & mask) ^ v		v = ((v ^ val) & mask) ^ v
	# vrlg.__dict__[vname]=v
	globals()[vname]=v		globals()[vname]=v
	# print ("new value for %s is %s (0x%x)"%(vname,str(vrlg.__dict__[vname]),vrlg.__dict__[vname]))

	def get_name_field(vname,		def get_name_field(vname,
	fieldIndex):		fieldIndex):
	@@ -62,6 +58,11 @@ def get_name_field(vname,
	<fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)		<fieldIndex> byte field index (0 - lowest byte, 1 - bits[15:8], etc)
	Return specified byte		Return specified byte
	"""		"""
			# print ("value for %s is %s"%(vname,str(globals()[vname])))
			# print ("dflt for %s is %s"%(vname,str(DEFAULTS[vname])))
			# print ("value[%d] for %s is 0x%x"%(fieldIndex,vname,globals()[vname]))
			# print ("dflt[%d] for %s is 0x%x"%(fieldIndex,vname,DEFAULTS[vname]))

	return ( globals()[vname] >> (8*fieldIndex)) & 0xff		return ( globals()[vname] >> (8*fieldIndex)) & 0xff

	def get_default_field(vname,		def get_default_field(vname,
	@@ -74,8 +75,11 @@ def get_default_field(vname,
	Return specified byte		Return specified byte
	"""		"""
	global DEFAULTS		global DEFAULTS
			# print ("value for %s is %s"%(vname,str(globals()[vname])))
			# print ("dflt for %s is %s"%(vname,str(DEFAULTS[vname])))
			# print ("value[%d] for %s is 0x%x"%(fieldIndex,vname,globals()[vname]))
			# print ("dflt[%d] for %s is 0x%x"%(fieldIndex,vname,DEFAULTS[vname]))

	# return (vrlg.DEFAULTS[vname] >> (8*fieldIndex)) & 0xff
	return (DEFAULTS[vname] >> (8*fieldIndex)) & 0xff		return (DEFAULTS[vname] >> (8*fieldIndex)) & 0xff

	def get_default(vname):		def get_default(vname):

py393/x393_axi_control_status.py

+144 −12

Original line number	Original line	Diff line number	Diff line
	@@ -36,24 +36,122 @@ from x393_mem import X393Mem
	from verilog_utils import hx		from verilog_utils import hx
	from time import time		from time import time
	import vrlg		import vrlg

			enabled_channels=0 # currently enable channels
			cke_en=0
			cmda_en=0
			sdrst_on=1
			mcntrl_en=0
			refresh_en=0
			channel_priority=[None]*16
			sequences_set=0
	class X393AxiControlStatus(object):		class X393AxiControlStatus(object):
	DRY_MODE= True # True		DRY_MODE= True # True
	DEBUG_MODE=1		DEBUG_MODE=1
	# vpars=None		# vpars=None
	x393_mem=None		x393_mem=None
	enabled_channels=0 # currently enable channels
	FPGA_RST_CTRL=0xf8000240		FPGA_RST_CTRL=0xf8000240
	# verbose=1		verbose=1
	def __init__(self, debug_mode=1,dry_mode=True):		def __init__(self, debug_mode=1,dry_mode=True):
	self.DEBUG_MODE=debug_mode		self.DEBUG_MODE=debug_mode
	self.DRY_MODE=dry_mode		self.DRY_MODE=dry_mode
	self.x393_mem=X393Mem(debug_mode,dry_mode)		self.x393_mem=X393Mem(debug_mode,dry_mode)
			try:
			self.verbose=vrlg.VERBOSE
			except:
			pass

	# self.__dict__.update(VerilogParameters.__dict__["_VerilogParameters__shared_state"]) # Add verilog parameters to the class namespace		# self.__dict__.update(VerilogParameters.__dict__["_VerilogParameters__shared_state"]) # Add verilog parameters to the class namespace
	'''		'''
	Maybe import parameters into the module, not class namespace to use directly, w/o self. ?		Maybe import parameters into the module, not class namespace to use directly, w/o self. ?
	# __dict__.update(VerilogParameters.__dict__) # Add verilog parameters to the class namespace		# __dict__.update(VerilogParameters.__dict__) # Add verilog parameters to the class namespace
	'''		'''

			# Use 'import pickle' (exists in the camera) to save/restore state
			def init_state(self):
			global enabled_channels, cke_en, cmda_en, sdrst_on, mcntrl_en, channel_priority, refresh_en, sequences_set
			"""
			reset state (as after bitstream load)
			"""
			enabled_channels=0 # currently enable channels
			cke_en=0
			cmda_en=0
			sdrst_on=1
			mcntrl_en=0
			channel_priority=[None]*16
			refresh_en=0
			sequences_set=0
			if self.verbose>0:
			print ("* System state reset **")
			# TODO: Add state save/restore in tmpfs file (like /var/state/...) (/var/state does not exist initially)
			def get_sequences_set(self,quiet=1):
			global sequences_set
			if quiet<2 :
			print ("SEQUENCES SET = %d"%sequences_set)
			return sequences_set

			def set_sequences_set(self,val,quiet=1):
			global sequences_set
			val= (0,1)[val]
			sequences_set=val
			if quiet<2 :
			print ("SEQUENCES SET = %d"%sequences_set)

			def get_cke_en(self,quiet=1):
			global cke_en
			if quiet<2 :
			print ("CKE EN = %d"%cke_en)
			return cke_en
			def get_cmda_en(self,quiet=1):
			global cmda_en
			if quiet<2 :
			print ("CMDA EN = %d"%cmda_en)
			return cmda_en
			def get_sdrst_on(self,quiet=1):
			global sdrst_on
			if quiet<2 :
			print ("SDRST ON = %d"%sdrst_on)
			return sdrst_on
			def get_mcntrl_en(self,quiet=1):
			global mcntrl_en
			if quiet<2 :
			print ("MCNTRL ON = %d"%mcntrl_en)
			return mcntrl_en
			def get_refresh_en(self,quiet=1):
			global refresh_en
			if quiet<2 :
			print ("REFRESH EN = %d"%refresh_en)
			return refresh_en
			def get_enabled_channels(self,quiet=1):
			global enabled_channels
			if quiet<2 :
			print ("ENABLED_CHANNELS = 0x%x"%enabled_channels)
			return enabled_channels

			def get_channel_priorities(self,quiet=1):
			global channel_priority
			if quiet<2 :
			print ("CHANNEL PRIORITIES:",end=" ")
			for v in channel_priority:
			if v is None:
			print (" - ",end=" ")
			else:
			print ("%d"%v,end=" ")
			print()
			return channel_priority

			def get_state(self,quiet=1):
			return {
			'cke_en': self.get_cke_en(quiet),
			'cmda_en': self.get_cmda_en(quiet),
			'sdrst_on': self.get_sdrst_on(quiet),
			'mcntrl_en': self.get_mcntrl_en(quiet),
			'enabled_channels': self.get_enabled_channels(quiet),
			'channel_priorities': self.get_channel_priorities(quiet),
			'refresh_en': self.get_refresh_en(quiet),
			'sequences_set': self.get_sequences_set(quiet)
			}

	def write_contol_register(self, reg_addr, data):		def write_contol_register(self, reg_addr, data):
	"""		"""
	Write 32-bit word to the control register		Write 32-bit word to the control register
	@@ -202,7 +300,12 @@ class X393AxiControlStatus(object):
	Enable (disable) address, bank and command lines to the DDR3 memory		Enable (disable) address, bank and command lines to the DDR3 memory
	<en> - 1 - enable, 0 - disable		<en> - 1 - enable, 0 - disable
	"""		"""
			global cmda_en
			en=(0,1)[en]
			if self.verbose>0:
			print ("ENABLE CMDA %s"%str(en))
	self.write_contol_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_CMDA_EN + en, 0);		self.write_contol_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_CMDA_EN + en, 0);
			cmda_en=en

	def enable_cke(self,		def enable_cke(self,
	en): # input en;		en): # input en;
	@@ -210,7 +313,12 @@ class X393AxiControlStatus(object):
	Enable (disable) CKE - clock enable to DDR3 memory		Enable (disable) CKE - clock enable to DDR3 memory
	<en> - 1 - enable, 0 - disable		<en> - 1 - enable, 0 - disable
	"""		"""
			global cke_en
			en=(0,1)[en]
			if self.verbose>0:
			print ("ENABLE CKE %s"%str(en))
	self.write_contol_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_CKE_EN + en, 0);		self.write_contol_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_CKE_EN + en, 0);
			cke_en=en

	def activate_sdrst(self,		def activate_sdrst(self,
	en): # input en;		en): # input en;
	@@ -218,7 +326,12 @@ class X393AxiControlStatus(object):
	Activate SDRST (reset) to DDR3 memory		Activate SDRST (reset) to DDR3 memory
	<en> - 1 - activate (low), 0 - deactivate (high)		<en> - 1 - activate (low), 0 - deactivate (high)
	"""		"""
			global sdrst_on
			en=(0,1)[en]
			if self.verbose>0:
			print ("ACTIVATE SDRST %s"%str(en))
	self.write_contol_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_SDRST_ACT + en, 0);		self.write_contol_register(vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_SDRST_ACT + en, 0);
			sdrst_on=en

	def enable_refresh(self,		def enable_refresh(self,
	en): # input en;		en): # input en;
	@@ -226,7 +339,12 @@ class X393AxiControlStatus(object):
	Enable (disable) refresh of the DDR3 memory		Enable (disable) refresh of the DDR3 memory
	<en> - 1 - enable, 0 - disable		<en> - 1 - enable, 0 - disable
	"""		"""
			global refresh_en
			en=(0,1)[en]
			if self.verbose>0:
			print ("ENABLE REFRESH %s"%str(en))
	self.write_contol_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_REFRESH_EN + en, 0);		self.write_contol_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_REFRESH_EN + en, 0);
			refresh_en=en

	def enable_memcntrl(self,		def enable_memcntrl(self,
	en): # input en;		en): # input en;
	@@ -234,16 +352,23 @@ class X393AxiControlStatus(object):
	Enable memory controller module		Enable memory controller module
	<en> - 1 - enable, 0 - disable		<en> - 1 - enable, 0 - disable
	"""		"""
			global mcntrl_en
			en=(0,1)[en]
			if self.verbose>0:
			print ("ENABLE MEMCTRL %s"%str(en))
	self.write_contol_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_MCONTR_EN + en, 0);		self.write_contol_register(vrlg.MCONTR_TOP_0BIT_ADDR + vrlg.MCONTR_TOP_0BIT_MCONTR_EN + en, 0);
			mcntrl_en=en
	def enable_memcntrl_channels(self,		def enable_memcntrl_channels(self,
	chnen): # input [15:0] chnen; // bit-per-channel, 1 - enable;		chnen): # input [15:0] chnen; // bit-per-channel, 1 - enable;
	"""		"""
	Enable memory controller channels (all at once control)		Enable memory controller channels (all at once control)
	<chnen> - 16-bit control word with per-channel enable bits (bit0 - chn0, ... bit15 - chn15)		<chnen> - 16-bit control word with per-channel enable bits (bit0 - chn0, ... bit15 - chn15)
	"""		"""
	self.enabled_channels = chnen; # currently enabled memory channels		global enabled_channels
	self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, self.enabled_channels & 0xffff) # {16'b0,chnen});		enabled_channels = chnen # currently enabled memory channels
			self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + vrlg.MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,chnen});
			if self.verbose>0:
			print ("ENABLED MEMCTRL CHANNELS 0x%x (word)"%enabled_channels)

	def enable_memcntrl_en_dis(self,		def enable_memcntrl_en_dis(self,
	chn, # input [3:0] chn;		chn, # input [3:0] chn;
	@@ -253,19 +378,26 @@ class X393AxiControlStatus(object):
	<chn> - 4-bit channel select		<chn> - 4-bit channel select
	<en> - 1 - enable, 0 - disable of the selected channel		<en> - 1 - enable, 0 - disable of the selected channel
	"""		"""
			global enabled_channels
	if en:		if en:
	self.enabled_channels = self.enabled_channels \| (1<<chn);		enabled_channels \|= 1<<chn;
	else:		else:
	self.enabled_channels = self.enabled_channels & ~(1<<chn);		enabled_channels &= ~(1<<chn);
	self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + self. MCONTR_TOP_16BIT_CHN_EN, self.enabled_channels & 0xffff) # {16'b0,ENABLED_CHANNELS});		self.write_contol_register(vrlg.MCONTR_TOP_16BIT_ADDR + self. MCONTR_TOP_16BIT_CHN_EN, enabled_channels & 0xffff) # {16'b0,ENABLED_CHANNELS});
			if self.verbose>0:
			print ("ENABLED MEMCTRL CHANNELS 0x%x (en/dis)"%enabled_channels)

	def configure_channel_priority(self,		def configure_channel_priority(self,
	chn, # input [ 3:0] chn;		chn, # input [ 3:0] chn;
	priority): #input [15:0] priority; // (higher is more important)		priority=0): #input [15:0] priority; // (higher is more important)
	"""		"""
	Configure channel priority		Configure channel priority
	<chn> - 4-bit channel select		<chn> - 4-bit channel select
	<priority> - 16-bit priority value (higher value means more important)		<priority> - 16-bit priority value (higher value means more important)
	"""		"""
			global channel_priority
	self.write_contol_register(vrlg.MCONTR_ARBIT_ADDR + chn, priority & 0xffff)# {16'b0,priority});		self.write_contol_register(vrlg.MCONTR_ARBIT_ADDR + chn, priority & 0xffff)# {16'b0,priority});
			if self.verbose>0:
			print ("SET CHANNEL %d priority=0x%x"%(chn,priority))
			channel_priority[chn]=priority

py393/x393_mcntrl_adjust.py

+387 −6

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