modified scanline mode to work with SDRAM page crossing (by splitting in 2), debugging read mode

memctrl/cmd_encod_linear_rd.v

@@ -47,6 +47,7 @@ module  cmd_encod_linear_rd #(
     input   [ADDRESS_NUMBER-1:0] row_in,      // memory row
     input   [COLADDR_NUMBER-4:0] start_col,   // start memory column in 8-bursts
     input    [NUM_XFER_BITS-1:0] num128_in,   // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
+    input                        skip_next_page_in, // do not reset external buffer (continue)    
     input                        start,       // start generating commands
     output reg            [31:0] enc_cmd,     // encoded commnad
     output reg                   enc_wr,      // write encoded command
@@ -72,7 +73,7 @@ module  cmd_encod_linear_rd #(
     localparam REPEAT_ADDR=3;
     
     localparam CMD_NOP=      0; // 3-bit normal memory RCW commands (positive logic)
-    localparam CMD_READ=    3;
+    localparam CMD_READ=     2;
     localparam CMD_PRECHARGE=5;
     localparam CMD_ACTIVATE= 4;
     
@@ -80,7 +81,7 @@ module  cmd_encod_linear_rd #(
     reg   [COLADDR_NUMBER-4:0] col;     // start memory column (3 LSBs should be 0?) // VDT BUG: col is used as a function call parameter!
     reg                  [2:0] bank;    // memory bank;
     reg    [NUM_XFER_BITS-1:0] num128;  // number of 128-bit words to transfer
-    
+    reg                        skip_next_page;
     reg                        gen_run;
     reg                        gen_run_d;
     reg        [ROM_DEPTH-1:0] gen_addr; // will overrun as stop comes from ROM
@@ -120,6 +121,8 @@ module  cmd_encod_linear_rd #(
         row<=row_in;
         col <= start_col;
         bank <= bank_in;
+        skip_next_page <= skip_next_page_in;
+        
     end
     
     // ROM-based (registered output) encoded sequence
@@ -146,7 +149,7 @@ module  cmd_encod_linear_rd #(
         else               enc_wr <= gen_run || gen_run_d;
         
         if (rst)           enc_done <= 0;
-        else               enc_done <= enc_wr || !gen_run_d;
+        else               enc_done <= enc_wr && !gen_run_d;
         
         if (rst)             enc_cmd <= 0;
         else if (rom_cmd==0) enc_cmd <= func_encode_skip ( // encode pause
@@ -162,7 +165,7 @@ module  cmd_encod_linear_rd #(
             rom_r[ENC_DCI],          //   dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
             rom_r[ENC_BUF_WR],       //   buf_wr;     // connect to external buffer (but only if not paused)
             1'b0,                    //   buf_rd;     // connect to external buffer (but only if not paused)
-            rom_r[ENC_BUF_PGNEXT]);     //   buf_rst;    // connect to external buffer (but only if not paused)
+            rom_r[ENC_BUF_PGNEXT] && !skip_next_page);     //   buf_rst;    // connect to external buffer (but only if not paused)
        else  enc_cmd <= func_encode_cmd ( // encode non-NOP command
             rom_cmd[1]?
                     row:
@@ -179,7 +182,7 @@ module  cmd_encod_linear_rd #(
             rom_r[ENC_BUF_WR],       //   buf_wr;     // connect to external buffer (but only if not paused)
             1'b0,                    //   buf_rd;     // connect to external buffer (but only if not paused)     
             rom_r[ENC_NOP],          //   nop;        // add NOP after the current command, keep other data
-            rom_r[ENC_BUF_PGNEXT]);  //   buf_rst;    // connect to external buffer (but only if not paused)
+            rom_r[ENC_BUF_PGNEXT] && !skip_next_page);  //   buf_rst;    // connect to external buffer (but only if not paused)
     end    
     
 

memctrl/cmd_encod_linear_wr.v

@@ -38,6 +38,7 @@ module  cmd_encod_linear_wr #(
     input   [ADDRESS_NUMBER-1:0] row_in,      // memory row
     input   [COLADDR_NUMBER-4:0] start_col,   // start memory column (3 LSBs should be 0?)
     input    [NUM_XFER_BITS-1:0] num128_in,   // number of 128-bit words to transfer (8*16 bits) - full burst of 8 (0 - full 64)
+    input                        skip_next_page_in, // do not reset external buffer (continue)    
     input                        start,       // start generating commands
     output reg            [31:0] enc_cmd,     // encoded commnad
     output reg                   enc_wr,      // write encoded command
@@ -72,7 +73,8 @@ module  cmd_encod_linear_wr #(
     reg   [ADDRESS_NUMBER-1:0] row;     // memory row
     reg   [COLADDR_NUMBER-4:0] col;     // start memory column (3 LSBs should be 0?) // VDT BUG: col is used as a function call parameter!
     reg                  [2:0] bank;    // memory bank;
-    reg    [NUM_XFER_BITS:0] num128;  // number of 128-bit words to transfer
+    reg      [NUM_XFER_BITS:0] num128;  // number of 128-bit words to transfer
+    reg                        skip_next_page;
     
     reg                        gen_run;
     reg                        gen_run_d;
@@ -131,6 +133,7 @@ module  cmd_encod_linear_wr #(
         row<=row_in;
         col <= start_col;
         bank <= bank_in;
+        skip_next_page <= skip_next_page_in;
     end
     
     // ROM-based (registered output) encoded sequence
@@ -177,7 +180,7 @@ module  cmd_encod_linear_wr #(
             1'b0,                    //   dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
             1'b0,                    //   buf_wr;     // connect to external buffer (but only if not paused)
             rom_r[ENC_BUF_RD] && !cut_buf_rd, //buf_rd;// connect to external buffer (but only if not paused)
-            rom_r[ENC_BUF_PGNEXT]);     //   buf_rst;    // connect to external buffer (but only if not paused)
+            rom_r[ENC_BUF_PGNEXT] && !skip_next_page);     //   buf_rst;    // connect to external buffer (but only if not paused)
        else  enc_cmd <= func_encode_cmd ( // encode non-NOP command
             rom_cmd[1]?
                     row:
@@ -194,7 +197,7 @@ module  cmd_encod_linear_wr #(
             1'b0,                    //   buf_wr;     // connect to external buffer (but only if not paused)
             rom_r[ENC_BUF_RD] && !cut_buf_rd, //buf_rd;// connect to external buffer (but only if not paused)     
             rom_r[ENC_NOP],          //   nop;        // add NOP after the current command, keep other data
-            rom_r[ENC_BUF_PGNEXT]);     //   buf_rst;    // connect to external buffer (but only if not paused)
+            rom_r[ENC_BUF_PGNEXT] && !skip_next_page);     //   buf_rst;    // connect to external buffer (but only if not paused)
     end    
     
 

memctrl/cmd_encod_tiled_rd.v

@@ -68,7 +68,7 @@ module  cmd_encod_tiled_rd #(
     localparam ENC_CMD_SHIFT=  4; // [5:4] - command: 0 -= NOP, 1 - READ, 2 - PRECHARGE, 3 - ACTIVATE
     localparam ENC_PAUSE_SHIFT=6; // [7:6] - 2- bit pause (for NOP commandes)
     localparam ENC_PRE_DONE=   8;
-    localparam ENC_BUF_PGNEXT=    9;
+    localparam ENC_BUF_PGNEXT= 9;
     
     localparam ENC_CMD_NOP=      0; // 2-bit locally encoded commands
     localparam ENC_CMD_READ=     1;
@@ -242,7 +242,7 @@ module  cmd_encod_tiled_rd #(
             4'h7:  rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT)                          | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL); 
             4'h8:  rom_r <= (ENC_CMD_READ <<      ENC_CMD_SHIFT)                          | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL); 
             4'h9:  rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (2 << ENC_PAUSE_SHIFT) | (1 << ENC_BUF_WR) | (1 << ENC_DCI) | (1 << ENC_SEL); 
-            4'ha: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL) | (skip_next_page? 1'b0:(1 << ENC_BUF_PGNEXT)); 
+            4'ha: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_DCI) | (1 << ENC_SEL) | (1 << ENC_BUF_PGNEXT); 
             4'hb: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (3 << ENC_PAUSE_SHIFT)                     | (1 << ENC_DCI);
             4'hc: rom_r <= (ENC_CMD_NOP <<       ENC_CMD_SHIFT) | (1 << ENC_PRE_DONE);
             default:rom_r <= 0;
@@ -272,7 +272,7 @@ module  cmd_encod_tiled_rd #(
             rom_r[ENC_DCI],          //   dci;        // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
             rom_r[ENC_BUF_WR],       //   buf_wr;     // connect to external buffer (but only if not paused)
             1'b0,                    //   buf_rd;     // connect to external buffer (but only if not paused)
-            rom_r[ENC_BUF_PGNEXT]);     //   buf_rst;    // connect to external buffer (but only if not paused)
+            rom_r[ENC_BUF_PGNEXT] && !skip_next_page);     //   buf_rst;    // connect to external buffer (but only if not paused)
        else  enc_cmd <= func_encode_cmd ( // encode non-NOP command
             rom_cmd[1]? // activate
             row_col_bank[FULL_ADDR_NUMBER-1:COLADDR_NUMBER]: // top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act
@@ -294,7 +294,7 @@ module  cmd_encod_tiled_rd #(
             rom_r[ENC_BUF_WR],       //   buf_wr;     // connect to external buffer (but only if not paused)
             1'b0,                    //   buf_rd;     // connect to external buffer (but only if not paused)     
             rom_r[ENC_NOP],          //   nop;        // add NOP after the current command, keep other data
-            rom_r[ENC_BUF_PGNEXT]);     //   buf_rst;    // connect to external buffer (but only if not paused)
+            rom_r[ENC_BUF_PGNEXT] && !skip_next_page);     //   buf_rst;    // connect to external buffer (but only if not paused)
     end    
 
 // move to include?, Yes, after fixing problem with paths

memctrl/mcntrl393.v

@@ -459,17 +459,19 @@ module  mcntrl393 #(
     wire                        buf4_regen;
 
 // common for channels 2 and 3
-    wire                [2:0] lin_rw_bank;     // memory bank
-    wire [ADDRESS_NUMBER-1:0] lin_rw_row;      // memory row
-    wire [COLADDR_NUMBER-4:0] lin_rw_col;      // start memory column in 8-bursts
-    wire                [5:0] lin_rw_num128;   // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
-    wire                      lin_rd_start;    // start generating commands for read sequence
-    wire                      lin_wr_start;    // start generating commands for write sequence
+    wire                  [2:0] lin_rw_bank;     // memory bank
+    wire   [ADDRESS_NUMBER-1:0] lin_rw_row;      // memory row
+    wire   [COLADDR_NUMBER-4:0] lin_rw_col;      // start memory column in 8-bursts
+    wire                  [5:0] lin_rw_num128;   // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
+    wire                        lin_rw_xfer_partial; // do not increment page in the end, continue current
+    wire                        lin_rd_start;    // start generating commands for read sequence
+    wire                        lin_wr_start;    // start generating commands for write sequence
 
     wire                  [2:0] lin_rd_chn2_bank;   // bank address
     wire   [ADDRESS_NUMBER-1:0] lin_rd_chn2_row;    // memory row
     wire   [COLADDR_NUMBER-4:0] lin_rd_chn2_col;    // start memory column in 8-bursts
     wire                  [5:0] lin_rd_chn2_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
+    wire                        lin_rd_chn2_partial;  // do not increment page in the end, continue current
     wire                        lin_rd_chn2_start;  // start generating commands
 //    wire                  [1:0] xfer_page2;         // "internal" buffer page
     wire                        xfer_reset_page2_pos;         // "internal" buffer page reset, @posedge mclk
@@ -479,6 +481,7 @@ module  mcntrl393 #(
     wire   [ADDRESS_NUMBER-1:0] lin_wr_chn3_row;    // memory row
     wire   [COLADDR_NUMBER-4:0] lin_wr_chn3_col;    // start memory column in 8-bursts
     wire                  [5:0] lin_wr_chn3_num128; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
+    wire                        lin_wr_chn3_partial; // do not increment page in the end, continue current
     wire                        lin_wr_chn3_start;  // start generating commands
 //    wire                  [1:0] xfer_page3;       // "internal" buffer page
     wire                        xfer_reset_page3;   // "internal" buffer page reset, @posedge mclk
@@ -667,11 +670,11 @@ module  mcntrl393 #(
         .status_ad            (status_tiled_chn4_ad), // output[7:0] 
         .status_rq            (status_tiled_chn4_rq), // output
         .status_start         (status_tiled_chn4_start), // input
-        .frame_start       (frame_start_chn4), // input
-        .next_page         (next_page_chn4), // input
-        .frame_done        (frame_done_chn4), // output
-        .line_unfinished   (line_unfinished_chn4), // output[15:0] 
-        .suspend           (suspend_chn4), // input
+        .frame_start          (frame_start_chn4), // input
+        .next_page            (next_page_chn4), // input
+        .frame_done           (frame_done_chn4), // output
+        .line_unfinished      (line_unfinished_chn4), // output[15:0] 
+        .suspend              (suspend_chn4), // input
         .xfer_want            (want_rq4), // output
         .xfer_need            (need_rq4), // output
         .xfer_grant           (channel_pgm_en4), // input
@@ -836,12 +839,12 @@ module  mcntrl393 #(
         .xfer_bank       (lin_rd_chn2_bank), // output[2:0] 
         .xfer_row        (lin_rd_chn2_row), // output[14:0] 
         .xfer_col        (lin_rd_chn2_col), // output[6:0] 
-        .xfer_num128     (lin_rd_chn2_num128), // output[5:0] 
+        .xfer_num128     (lin_rd_chn2_num128), // output[5:0]
+        .xfer_partial    (lin_rd_chn2_partial), // output
         .xfer_done       (seq_done2), // input: sequence over
         .xfer_reset_page (xfer_reset_page2_pos) // output
     );
 
-
     mcntrl_linear_rw #(
         .ADDRESS_NUMBER                    (ADDRESS_NUMBER),
         .COLADDR_NUMBER                    (COLADDR_NUMBER),
@@ -880,7 +883,8 @@ module  mcntrl393 #(
         .xfer_bank       (lin_wr_chn3_bank), // output[2:0] 
         .xfer_row        (lin_wr_chn3_row), // output[14:0] 
         .xfer_col        (lin_wr_chn3_col), // output[6:0] 
-        .xfer_num128     (lin_wr_chn3_num128), // output[5:0] 
+        .xfer_num128     (lin_wr_chn3_num128), // output[5:0]
+        .xfer_partial         (lin_wr_chn3_partial), // output
         .xfer_done       (seq_done3), // input : sequence over
 //        .xfer_page       (xfer_page3) // output[1:0]
         .xfer_reset_page (xfer_reset_page3) // output
@@ -895,24 +899,26 @@ module  mcntrl393 #(
         .row2                     (lin_rd_chn2_row), // input[14:0] 
         .start_col2               (lin_rd_chn2_col), // input[6:0] 
         .num128_2                 (lin_rd_chn2_num128), // input[5:0] 
+        .partial2                 (lin_rd_chn2_partial), // input
         .start2                   (lin_rd_chn2_start), // input
         
         .bank3                    (lin_wr_chn3_bank), // input[2:0] 
         .row3                     (lin_wr_chn3_row), // input[14:0] 
         .start_col3               (lin_wr_chn3_col), // input[6:0] 
         .num128_3                 (lin_wr_chn3_num128), // input[5:0] 
+        .partial3                 (lin_wr_chn3_partial), // input
         .start3                   (lin_wr_chn3_start), // input
 
         .bank                     (lin_rw_bank), // output[2:0] 
         .row                      (lin_rw_row), // output[14:0] 
         .start_col                (lin_rw_col), // output[6:0] 
-        .num128                   (lin_rw_num128), // output[5:0] 
+        .num128                   (lin_rw_num128), // output[5:0]
+        .partial                  (lin_rw_xfer_partial), // output
         .start_rd                 (lin_rd_start), // output
         .start_wr                 (lin_wr_start) // output
     );
 
     
-    /* Instance template for module cmd_encod_linear_rd */
     cmd_encod_linear_rd #(
         .ADDRESS_NUMBER  (ADDRESS_NUMBER),
         .COLADDR_NUMBER  (COLADDR_NUMBER),
@@ -920,40 +926,40 @@ module  mcntrl393 #(
         .CMD_PAUSE_BITS  (CMD_PAUSE_BITS),
         .CMD_DONE_BIT    (CMD_DONE_BIT)
     ) cmd_encod_linear_rd_i (
-        .rst       (rst), // input
-        .clk       (mclk), // input
-        .bank_in   (lin_rw_bank), // input[2:0] 
-        .row_in    (lin_rw_row), // input[14:0] 
-        .start_col (lin_rw_col), // input[6:0] 
-        .num128_in (lin_rw_num128), // input[5:0] 
-        .start     (lin_rd_start), // input
-        .enc_cmd   (seq_data2x), // output[31:0] reg 
-        .enc_wr    (seq_wr2x), // output reg 
-        .enc_done  (seq_set2x) // output reg 
+        .rst               (rst), // input
+        .clk               (mclk), // input
+        .bank_in           (lin_rw_bank), // input[2:0] 
+        .row_in            (lin_rw_row), // input[14:0] 
+        .start_col         (lin_rw_col), // input[6:0] 
+        .num128_in         (lin_rw_num128), // input[5:0] 
+        .skip_next_page_in (lin_rw_xfer_partial), // input
+        .start             (lin_rd_start), // input
+        .enc_cmd           (seq_data2x), // output[31:0] reg 
+        .enc_wr            (seq_wr2x), // output reg 
+        .enc_done          (seq_set2x) // output reg 
     );
 
-    /* Instance template for module cmd_encod_linear_wr */
     cmd_encod_linear_wr #(
         .ADDRESS_NUMBER  (ADDRESS_NUMBER),
         .COLADDR_NUMBER  (COLADDR_NUMBER),
         .NUM_XFER_BITS   (NUM_XFER_BITS),
         .CMD_PAUSE_BITS  (CMD_PAUSE_BITS),
-        .CMD_DONE_BIT  (CMD_DONE_BIT)
+        .CMD_DONE_BIT    (CMD_DONE_BIT)
     ) cmd_encod_linear_wr_i (
-        .rst       (rst), // input
-        .clk       (mclk), // input
-        .bank_in   (lin_rw_bank), // input[2:0] 
-        .row_in    (lin_rw_row), // input[14:0] 
-        .start_col (lin_rw_col), // input[6:0] 
-        .num128_in (lin_rw_num128), // input[5:0] 
-        .start     (lin_wr_start), // input
-        .enc_cmd   (seq_data3x), // output[31:0] reg 
-        .enc_wr    (seq_wr3x), // output reg 
-        .enc_done  (seq_set3x) // output reg 
+        .rst               (rst), // input
+        .clk               (mclk), // input
+        .bank_in           (lin_rw_bank), // input[2:0] 
+        .row_in            (lin_rw_row), // input[14:0] 
+        .start_col         (lin_rw_col), // input[6:0] 
+        .num128_in         (lin_rw_num128), // input[5:0] 
+        .skip_next_page_in (lin_rw_xfer_partial), // input
+        .start             (lin_wr_start), // input
+        .enc_cmd           (seq_data3x), // output[31:0] reg 
+        .enc_wr            (seq_wr3x), // output reg 
+        .enc_done          (seq_set3x) // output reg 
     );
 
 
-     /* Instance template for module mcntrl_ps_pio */
     mcntrl_ps_pio #(
         .MCNTRL_PS_ADDR            (MCNTRL_PS_ADDR), //'h100),
         .MCNTRL_PS_MASK            (MCNTRL_PS_MASK), //'h3e0),

memctrl/mcntrl393_test01.v

@@ -118,9 +118,9 @@ module  mcntrl393_test01#(
     assign suspend_chn2 = suspend_chn2_r;
     assign suspend_chn3 = suspend_chn3_r;
     assign suspend_chn4 = suspend_chn4_r;
-    assign status_chn2={page_chn2,line_unfinished_chn2,1'b0, frame_busy_chn2};
-    assign status_chn3={page_chn3,line_unfinished_chn3,1'b0, frame_busy_chn3};
-    assign status_chn4={page_chn4,line_unfinished_chn4,1'b0, frame_busy_chn4};
+    assign status_chn2={page_chn2,line_unfinished_chn2,frame_busy_chn2, frame_busy_chn2};
+    assign status_chn3={page_chn3,line_unfinished_chn3,frame_busy_chn3, frame_busy_chn3};
+    assign status_chn4={page_chn4,line_unfinished_chn4,frame_busy_chn4, frame_busy_chn4};
 
     always @ (posedge mclk) begin
         frame_start_chn2_r <= set_chh2_mode && cmd_frame_start_w;

memctrl/mcntrl_tiled_rw.v

@@ -24,7 +24,6 @@
 module  mcntrl_tiled_rw#(
    parameter ADDRESS_NUMBER=                   15,
     parameter COLADDR_NUMBER=                   10,
-    parameter NUM_XFER_BITS=                     6,    // number of bits to specify transfer length
     parameter FRAME_WIDTH_BITS=                 13,    // Maximal frame width - 8-word (16 bytes) bursts 
     parameter FRAME_HEIGHT_BITS=                16,    // Maximal frame height 
     parameter MAX_TILE_WIDTH=                   6,     // number of bits to specify maximal tile (width-1) (6 -> 64)
@@ -106,7 +105,7 @@ module  mcntrl_tiled_rw#(
     reg        [MAX_TILE_WIDTH:0] lim_by_tile_width;     // number of bursts left limited by the longest transfer (currently 64)
     wire     [COLADDR_NUMBER-3:0] remainder_tile_width;  // number of bursts postponed to the next partial tile (because of the page crossing) MSB-sign
     reg                           continued_tile;        // this is a continued tile (caused by page crossing) - only once
-    reg      [MAX_TILE_WIDTH-1:0] leftower_cols;         // valid with continued_tile, number of columns left
+    reg      [MAX_TILE_WIDTH-1:0] leftover_cols;         // valid with continued_tile, number of columns left
     wire                          pgm_param_w;  // program one of the parameters, invalidate calculated results for PAR_MOD_LATENCY
     reg                     [2:0] xfer_start_r;
     reg     [PAR_MOD_LATENCY-1:0] par_mod_r; 
@@ -242,7 +241,7 @@ module  mcntrl_tiled_rw#(
     assign cmd_extra_pages = mode_reg[3:2]; // external module needs more than 1 page
     assign keep_open=        mode_reg[4]; // keep banks open (will be used only if number of rows <= 8 
 //    assign cmd_wrmem =       mode_reg[5];// 0: read from memory, 1:write to memory
-    assign status_data= {1'b0, busy_r};     // TODO: Add second bit?
+    assign status_data=      {frame_done, busy_r}; 
     assign pgm_param_w=      cmd_we;
     assign rowcol_inc=       frame_full_width;
     assign num_cols_m1_w=    num_cols_r-1;
@@ -281,9 +280,9 @@ module  mcntrl_tiled_rw#(
         if (recalc_r[2]) begin
             xfer_limited_by_mem_page_r <= xfer_limited_by_mem_page && !continued_tile;     
             num_cols_r<= continued_tile?
-                {EXTRA_BITS,leftower_cols}:
+                {EXTRA_BITS,leftover_cols}:
                 (xfer_limited_by_mem_page? mem_page_left[MAX_TILE_WIDTH:0]:lim_by_tile_width[MAX_TILE_WIDTH:0]);
-                leftower_cols <= remainder_tile_width[MAX_TILE_WIDTH-1:0];
+                leftover_cols <= remainder_tile_width[MAX_TILE_WIDTH-1:0];
 //            remainder_tile_width <= {EXTRA_BITS,lim_by_tile_width}-mem_page_left;
         end
 // VDT bug? next line gives a warning        
@@ -344,10 +343,12 @@ wire    start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
         else if (chn_rst || xfer_grant)                          want_r <= 0;
         else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1;
         
-        if (rst)                               page_cntr <= 0;
-        else if (frame_start)                  page_cntr <= cmd_wrmem?0:4;
-        else if ( xfer_start_r[0] && !next_page) page_cntr <= page_cntr + 1;     
-        else if (!xfer_start_r[0] &&  next_page) page_cntr <= page_cntr - 1;
+        if (rst)                                   page_cntr <= 0;
+        else if (frame_start)                      page_cntr <= cmd_wrmem?0:4;
+//        else if ( xfer_start_r[0] && !next_page) page_cntr <= page_cntr + 1;     
+//        else if (!xfer_start_r[0] &&  next_page) page_cntr <= page_cntr - 1;
+        else if ( start_not_partial && !next_page) page_cntr <= page_cntr + 1;     
+        else if (!start_not_partial &&  next_page) page_cntr <= page_cntr - 1;
         
         if (rst) xfer_page_rst_r <= 1;
         else     xfer_page_rst_r <= chn_rst || (MCNTRL_TILED_FRAME_PAGE_RESET ? frame_start:1'b0);

x393_testbench01.tf

@@ -23,12 +23,19 @@
 `define DEBUG_FIFO 1
 `undef WAIT_MRS
 `define SET_PER_PIN_DEALYS 1 // set individual (including per-DQ pin delays)
+`define PS_PIO_WAIT_COMPLETE 0 // wait until PS PIO module finished transaction before starting a new one
+// Disabled already passed test to speedup simulation
 //`define TEST_WRITE_LEVELLING 1
 //`define TEST_READ_PATTERN 1
 //`define TEST_WRITE_BLOCK 1
 //`define TEST_READ_BLOCK 1
+
+
 `define TEST_SCANLINE_WRITE 1
-`define PS_PIO_WAIT_COMPLETE 0 // wait until PS PIO module finished transaction before starting a new one
+`define TEST_SCANLINE_WRITE_WAIT 1 // wait TEST_SCANLINE_WRITE finished (frame_done)
+`define TEST_SCANLINE_READ  1
+
+
 
 module  x393_testbench01 #(
 `include "includes/x393_parameters.vh"
@@ -191,7 +198,7 @@ module  x393_testbench01 #(
   localparam       SCANLINE_WINDOW_W=   'h000b;  // 176:  13-bit window width (0->'h4000)
   localparam       SCANLINE_WINDOW_H=   'h0009;  // 9:    16-bit frame height (0->'h10000)
 //  localparam       SCANLINE_X0Y0=       'h00050003;  // X0=3*16=48, Y0=5: // low word - 13-bit window left, high word - 16-bit window top
-  localparam       SCANLINE_X0=         'h0003;  // X0=3*16=48 - 13-bit window left
+  localparam       SCANLINE_X0=         'h7c; // 'h0003;  // X0=3*16=48 - 13-bit window left
   localparam       SCANLINE_Y0=         'h0005;  // Y0=5: 16-bit window top
 //  localparam       SCANLINE_STARTXY=    'h0;         // low word - 13-bit start X (relative to window), high word - 16-bit start y (normally 0)
   localparam       SCANLINE_STARTX=     'h0;         // 13-bit start X (relative to window), high word (normally 0)
@@ -364,7 +371,7 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
     write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_WINDOW_STARTXY,   SCANLINE_STARTX+(SCANLINE_STARTY<<16));
     write_contol_register(MCNTRL_SCANLINE_CHN3_ADDR + MCNTRL_SCANLINE_MODE,             {28'b0,SCANLINE_EXTRA_PAGES,2'b11});// set mode register: {extra_pages[1:0],enable,!reset}
 
-    configure_channel_priority(3,0);    // lowest priority channel 1
+    configure_channel_priority(3,0);    // lowest priority channel 3
     enable_memcntrl_channels(16'h000b); // channels 0,1,3 are enabled
 //  localparam       TEST01_START_FRAME=   1;         
 //  localparam       TEST01_NEXT_PAGE=     2;         
@@ -374,17 +381,8 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
     for (ii=0;ii<TEST_INITIAL_BURST;ii=ii+1) begin
         write_block_scanline_chn(3, (ii & 3), SCANLINE_WINDOW_W << 2, SCANLINE_X0,SCANLINE_Y0+ii);  // now assumes that width is <= than maximal xfer
     end
-//    write_block_scanline_chn(3,0, SCANLINE_WINDOW_W << 2, SCANLINE_X0,SCANLINE_Y0+0);  // now assumes that width is <= than maximal xfer
-//    write_block_scanline_chn(3,1, SCANLINE_WINDOW_W << 2, SCANLINE_X0,SCANLINE_Y0+1);
-//    write_block_scanline_chn(3,2, SCANLINE_WINDOW_W << 2, SCANLINE_X0,SCANLINE_Y0+2);
 
-//    write_block_scanline_chn(3,3, SCANLINE_WINDOW_W << 2, SCANLINE_X0,SCANLINE_Y0+3);
-//    write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE,            TEST01_NEXT_PAGE);
-//    write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE,            TEST01_NEXT_PAGE);
-//    write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE,            TEST01_NEXT_PAGE);
-//    write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE,            TEST01_NEXT_PAGE);
-// now need to repeat - test ready, then next page
-    for (ii=0;ii<SCANLINE_WINDOW_H;ii = ii+1) begin
+    for (ii=0;ii<SCANLINE_WINDOW_H;ii = ii+1) begin // here assuming 1 page per line
         if (ii >= TEST_INITIAL_BURST) begin // wait page ready and fill page after first 4 are filled
             wait_status_condition (
                 MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
@@ -397,8 +395,42 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
         end
         write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_MODE,            TEST01_NEXT_PAGE);
     end
-    
+    `ifdef TEST_SCANLINE_WRITE_WAIT
+            wait_status_condition ( // may also be read directly from the same bit of mctrl_linear_rw (address=5) status
+                MCNTRL_TEST01_STATUS_REG_CHN3_ADDR,
+                MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN3_STATUS_CNTRL,
+                DEFAULT_STATUS_MODE,
+                2 << STATUS_2LSB_SHFT, // bit 24 - busy, bit 25 - frame done
+                2 << STATUS_2LSB_SHFT,  // mask for the 4-bit page number
+                0); // equal to
+    `endif
 `endif
+`ifdef TEST_SCANLINE_READ
+   // program to the
+    write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_STARTADDR,        FRAME_START_ADDRESS); // RA=80, CA=0, BA=0 22-bit frame start address (3 CA LSBs==0. BA==0) 
+    write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_FRAME_FULL_WIDTH, FRAME_FULL_WIDTH);
+    write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_WINDOW_WH,        SCANLINE_WINDOW_W + (SCANLINE_WINDOW_H<<16));
+    write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_WINDOW_X0Y0,      SCANLINE_X0+ (SCANLINE_Y0<<16));
+    write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_WINDOW_STARTXY,   SCANLINE_STARTX+(SCANLINE_STARTY<<16));
+    write_contol_register(MCNTRL_SCANLINE_CHN2_ADDR + MCNTRL_SCANLINE_MODE,             {28'b0,SCANLINE_EXTRA_PAGES,2'b11});// set mode register: {extra_pages[1:0],enable,!reset}
+
+    configure_channel_priority(2,0);    // lowest priority channel 2
+    enable_memcntrl_channels(16'h000f); // channels 0,1,2,3 are enabled
+
+    write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE,            TEST01_START_FRAME);
+    for (ii=0;ii<SCANLINE_WINDOW_H;ii = ii+1) begin // here assuming 1 page per line
+            wait_status_condition (
+                MCNTRL_TEST01_STATUS_REG_CHN2_ADDR,
+                MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_STATUS_CNTRL,
+                DEFAULT_STATUS_MODE,
+                (ii) << 16, // -TEST_INITIAL_BURST)<<16, // 4-bit page number
+                'hf << 16,  // mask for the 4-bit page number
+                1); // not equal to
+// read block (if needed), for now just sikip                
+        write_contol_register(MCNTRL_TEST01_ADDR + MCNTRL_TEST01_CHN2_MODE,            TEST01_NEXT_PAGE);
+    end
+`endif
+
   #40000;
   $finish;
 end