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Commit e300b2ef authored by Andrey Filippov's avatar Andrey Filippov
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Fixed duplicate names

parent 27886e13
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Showing with 14 additions and 14 deletions
py393/generated/x393.c
View file @ e300b2ef
/*******************************************************************************
* File: x393.c
* Date: 2016-03-27
* Date: 2016-03-28
* Author: auto-generated file, see x393_export_c.py
* Description: Functions definitions to access x393 hardware registers
*******************************************************************************/
......@@ -56,8 +56,8 @@ void set_x393_mcntrl_dm_odly1 (x393_dly_t d)
x393_dly_t get_x393_mcntrl_dm_odly1 (void) {return (x393_dly_t) readl(0x400002a4)};
void set_x393_mcntrl_cmda_odly (x393_dly_t d, int chn){writel(0x40000300 + 0x4 * chn, (u32) d)}; // Address, bank and commands delays
x393_dly_t get_x393_mcntrl_cmda_odly (int chn) {return (x393_dly_t) readl(0x40000300 + 0x4 * chn)};
void set_x393_mcntrl_cmda_odly (x393_dly_t d) {writel(0x40000380, (u32) d)}; // Clock phase
x393_dly_t get_x393_mcntrl_cmda_odly (void) {return (x393_dly_t) readl(0x40000380)};
void set_x393_mcntrl_phase (x393_dly_t d) {writel(0x40000380, (u32) d)}; // Clock phase
x393_dly_t get_x393_mcntrl_phase (void) {return (x393_dly_t) readl(0x40000380)};
void x393_mcntrl_dly_set (void) {writel(0x40000080, 0)}; // Set all pre-programmed delays
void set_x393_mcntrl_wbuf_dly (x393_wbuf_dly_t d) {writel(0x40000148, (u32) d)}; // Set write buffer delay
x393_wbuf_dly_t get_x393_mcntrl_wbuf_dly (void) {return (x393_wbuf_dly_t) readl(0x40000148)};
......
py393/generated/x393.h
View file @ e300b2ef
/*******************************************************************************
* File: x393.h
* Date: 2016-03-27
* Date: 2016-03-28
* Author: auto-generated file, see x393_export_c.py
* Description: Constants definitions and functions declarations to access x393 hardware registers
*******************************************************************************/
......@@ -56,8 +56,8 @@ void set_x393_mcntrl_dm_odly1 (x393_dly_t d);
x393_dly_t get_x393_mcntrl_dm_odly1 (void);
void set_x393_mcntrl_cmda_odly (x393_dly_t d, int chn); // Address, bank and commands delays
x393_dly_t get_x393_mcntrl_cmda_odly (int chn);
void set_x393_mcntrl_cmda_odly (x393_dly_t d); // Clock phase
x393_dly_t get_x393_mcntrl_cmda_odly (void);
void set_x393_mcntrl_phase (x393_dly_t d); // Clock phase
x393_dly_t get_x393_mcntrl_phase (void);
void x393_mcntrl_dly_set (void); // Set all pre-programmed delays
void set_x393_mcntrl_wbuf_dly (x393_wbuf_dly_t d); // Set write buffer delay
x393_wbuf_dly_t get_x393_mcntrl_wbuf_dly (void);
......
py393/generated/x393_defs.h
View file @ e300b2ef
/*******************************************************************************
* File: x393_defs.h
* Date: 2016-03-27
* Date: 2016-03-28
* Author: auto-generated file, see x393_export_c.py
* Description: Constants and hardware addresses definitions to access x393 hardware registers
*******************************************************************************/
......@@ -41,7 +41,7 @@
#define X393_MCNTRL_DM_ODLY0 0x40000224 // Lane0 DM output delay , data type: x393_dly_t (rw)
#define X393_MCNTRL_DM_ODLY1 0x400002a4 // Lane1 DM output delay , data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY(chn) (0x40000300 + 0x4 * (chn)) // Address, bank and commands delays, chn = 0..31, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY 0x40000380 // Clock phase, data type: x393_dly_t (rw)
#define X393_MCNTRL_PHASE 0x40000380 // Clock phase, data type: x393_dly_t (rw)
#define X393_MCNTRL_DLY_SET 0x40000080 // Set all pre-programmed delays
#define X393_MCNTRL_WBUF_DLY 0x40000148 // Set write buffer delay, data type: x393_wbuf_dly_t (rw)
......
py393/generated/x393_map.h
View file @ e300b2ef
/*******************************************************************************
* File: x393_map.h
* Date: 2016-03-27
* Date: 2016-03-28
* Author: auto-generated file, see x393_export_c.py
* Description: Sorted hardware addresses map
*******************************************************************************/
......@@ -116,7 +116,7 @@
#define X393_MCNTRL_CMDA_ODLY__29 0x40000374 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__30 0x40000378 // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY__31 0x4000037c // Address, bank and commands delays, data type: x393_dly_t (rw)
#define X393_MCNTRL_CMDA_ODLY 0x40000380 // Clock phase, data type: x393_dly_t (rw)
#define X393_MCNTRL_PHASE 0x40000380 // Clock phase, data type: x393_dly_t (rw)
// RESERVED: 0x13 DWORDs
#define X393_MCNTRL_TEST01_CHN2_MODE 0x400003d0 // Set command for test01 channel 2, data type: x393_test01_mode_t (wo)
#define X393_MCNTRL_TEST01_CHN2_STATUS_CNTRL 0x400003d4 // Set status control register (status update mode), data type: x393_status_ctrl_t (rw)
......
py393/generated/x393_types.h
View file @ e300b2ef
/*******************************************************************************
* File: x393_types.h
* Date: 2016-03-27
* Date: 2016-03-28
* Author: auto-generated file, see x393_export_c.py
* Description: typedef definitions for the x393 hardware registers
*******************************************************************************/
......@@ -366,7 +366,7 @@ typedef union {
} struct_0;
struct {
u32 :14;
u32 diff: 1; // [ 17] (0) Difference scale: 0 - keep diff, 1- multiply diff by 16
u32 diff_scale: 1; // [ 17] (0) Difference scale: 0 - keep diff, 1- multiply diff by 16
char diff: 7; // [16:10] (0) Difference to next (signed, -64..+63)
u32 base:10; // [ 9: 0] (0) Knee point value (to be interpolated between)
} struct_1;
......
py393/x393_export_c.py
View file @ e300b2ef
......@@ -634,7 +634,7 @@ class X393ExportC(object):
(("X393_MCNTRL_DM_ODLY0", c, vrlg.LD_DLY_LANE0_ODELAY + ba + 9, 0, None, "x393_dly", "rw", "Lane0 DM output delay ")),
(("X393_MCNTRL_DM_ODLY1", c, vrlg.LD_DLY_LANE1_ODELAY + ba + 9, 0, None, "x393_dly", "rw", "Lane1 DM output delay ")),
(("X393_MCNTRL_CMDA_ODLY", c, vrlg.LD_DLY_CMDA + ba, 1, z31, "x393_dly", "rw", "Address, bank and commands delays")),
(("X393_MCNTRL_CMDA_ODLY", c, vrlg.LD_DLY_PHASE + ba, 0, None, "x393_dly", "rw", "Clock phase")),
(("X393_MCNTRL_PHASE", c, vrlg.LD_DLY_PHASE + ba, 0, None, "x393_dly", "rw", "Clock phase")),
(("X393_MCNTRL_DLY_SET", c, vrlg.MCONTR_PHY_0BIT_ADDR + vrlg.MCONTR_PHY_0BIT_DLY_SET + ba, 0, None, "", "", "Set all pre-programmed delays")),
(("X393_MCNTRL_WBUF_DLY", c, vrlg.MCONTR_PHY_16BIT_ADDR + vrlg.MCONTR_PHY_16BIT_WBUF_DELAY + ba, 0, None, "x393_wbuf_dly", "rw", "Set write buffer delay")),
]
......@@ -1816,7 +1816,7 @@ class X393ExportC(object):
dw=[]
dw.append(("base", 0, 10, 0, "Knee point value (to be interpolated between)"))
dw.append((("diff","char"), 10, 7, 0, "Difference to next (signed, -64..+63)"))
dw.append(("diff", 17, 1, 0, "Difference scale: 0 - keep diff, 1- multiply diff by 16"))
dw.append(("diff_scale", 17, 1, 0, "Difference scale: 0 - keep diff, 1- multiply diff by 16"))
return dw
def _enc_gamma_height01(self):
dw=[]
......
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