working on dtt

dct_tests_01.sav

 [*]
 [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
-[*] Tue Dec 13 19:43:18 2016
+[*] Tue Dec  5 02:26:14 2017
 [*]
-[dumpfile] "/home/eyesis/git/x393-neon/simulation/dct_tests_01-20161213123921501.fst"
-[dumpfile_mtime] "Tue Dec 13 19:39:21 2016"
-[dumpfile_size] 103386
-[savefile] "/home/eyesis/git/x393-neon/dct_tests_01.sav"
+[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/dct_tests_01-20171130150416223.fst"
+[dumpfile_mtime] "Thu Nov 30 22:04:17 2017"
+[dumpfile_size] 105262
+[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/dct_tests_01.sav"
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-[size] 1814 1171
-[pos] 1912 0
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+[size] 1814 1167
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 [treeopen] dct_tests_01.
 [treeopen] dct_tests_01.dct_iv8_1d_i.
 [treeopen] dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.
@@ -19,11 +19,14 @@
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@@ -79,6 +82,7 @@ dct_tests_01.x_out[23:0]
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 [color] 2
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+dct_tests_01.start2
 dct_tests_01.y_dv
 dct_tests_01.y_pre_we
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@@ -91,7 +95,8 @@ dct_tests_01.phase_y[3:0]
 dct_tests_01.y_dct[23:0]
 dct_tests_01.y_out[23:0]
 dct_tests_01.dct_iv8_1d_i.y_index[2:0]
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+dct_tests_01.x_in_2d[23:0]
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@@ -203,7 +208,7 @@ dct_tests_01.dct_iv8_1d_i.dsp_post_add_1
 dct_tests_01.dct_iv8_1d_i.dsp_accum_1
 @22
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-@800200
+@c00200
 -dsp_1
 @22
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@@ -235,7 +240,7 @@ dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.p_reg_cond[47:0]
 dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.p_reg[47:0]
 @200
 -
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+@1401200
 -dsp_1
 @22
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@@ -274,7 +279,7 @@ dct_tests_01.dct_iv8_1d_i.dsp_p_2[47:0]
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 @22
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-@800200
+@c00200
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@@ -286,7 +291,7 @@ dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_2_i.ad_reg[24:0]
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@@ -393,10 +398,53 @@ dct_tests_01.d_out_2d[23:0]
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dct_tests_02.sav

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+[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
+[*] Tue Dec  5 05:26:29 2017
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dsp/dtt_iv8_1d.v

@@ -66,7 +66,7 @@ module  dtt_iv8_1d#(
     input                          clk,
     input                          rst,
     input                          en,
-    input                          dst_in, // 0 - dct, 1 - dst. @ start/restart
+    input                          dst_in, // 0 - dct, 1 - dst. @ start only, no restart
     input  [WIDTH -1:0]            d_in,   // X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X6-X7-*
     input                          start,  // one cycle before first X6 input 
     output [OUT_WIDTH -1:0]        dout,
@@ -75,6 +75,7 @@ module  dtt_iv8_1d#(
                                              // In DST mode the sequence is the same (to be inverted), but
                                              // Y0, Y2, Y4 and Y6 are negated 
     output                         en_out,   // valid at the same time slot as pre2_start_out (goes active with pre2_start_out), 2 ahead of data
+    output                         dst_out,  // valid with en_out
     output reg               [2:0] y_index   // for simulation - valid with dout - index of the data output
                                           
 );
@@ -140,7 +141,10 @@ module  dtt_iv8_1d#(
     reg                         en_out_r2;
     
     reg                         dst_pre; // keeps dst_in value for second stage
-    reg                         dst_out; // controls source of dsp_neg_m_2 mux
+    reg                         dst_2;     // controls source of dsp_neg_m_2 mux
+    reg                         dst_out_r; // // 2 ahead of data out
+    
+    assign dst_out = dst_out_r;
     
     assign en_out = en_out_r;
     
@@ -162,14 +166,14 @@ module  dtt_iv8_1d#(
         en_out_r2 <= en_out_r;
         if (en_out_r2) begin
             case (phase_cnt[3:1])
-                3'h0: y_index <= 0;
-                3'h1: y_index <= 7;
-                3'h2: y_index <= 4;
-                3'h3: y_index <= 3;
-                3'h4: y_index <= 1;
-                3'h5: y_index <= 6;
-                3'h6: y_index <= 2;
-                3'h7: y_index <= 5;
+                3'h0: y_index <= dst_out_r ? 7 : 0;
+                3'h1: y_index <= dst_out_r ? 0 : 7;
+                3'h2: y_index <= dst_out_r ? 3 : 4;
+                3'h3: y_index <= dst_out_r ? 4 : 3;
+                3'h4: y_index <= dst_out_r ? 6 : 1;
+                3'h5: y_index <= dst_out_r ? 1 : 6;
+                3'h6: y_index <= dst_out_r ? 5 : 2;
+                3'h7: y_index <= dst_out_r ? 2 : 5;
             endcase
         end else begin
             y_index <= 'bx;
@@ -193,11 +197,14 @@ module  dtt_iv8_1d#(
         else if (start || restart) run_in <= 1;
         else if (phase_cnt==15)    run_in <= 0;
         
-        if (start || restart)      dst_pre <= dst_in;
+//        if (start || restart)      dst_pre <= dst_in;
+        if (start)                 dst_pre <= dst_in;
+        
+        if (phase_cnt == 12)       dst_2 <=      dst_pre;
+        if (phase_cnt == 14)       dst_out_r <=  dst_2;
         
-        if (phase_cnt == 12)       dst_out <= dst_pre;
         
-        dsp_neg_m_2 <= dst_out ?  dsp_neg_m_2_dst : dsp_neg_m_2_dct;
+        dsp_neg_m_2 <= dst_2 ?  dsp_neg_m_2_dst : dsp_neg_m_2_dct;
 
         if      (rst)              run_out <= 0;
         else if (phase_cnt == 13)  run_out <= run_in;
@@ -280,7 +287,7 @@ module  dtt_iv8_1d#(
         dsp_selb_2 <=      p00             | p03       | p05 | p06       | p08             | p11       | p13 | p14       ;
 //        dsp_neg_m_2 <=                       p03             | p06                               | p12             | p15 ;
         dsp_neg_m_2_dct <=             p02             | p05                               | p11             | p14       ;
-        dsp_neg_m_2_dst <= p00 | p01 | p02             | p05 | p06 | p07 | p08 | p09       | p11             | p14       ;
+        dsp_neg_m_2_dst <= p00 | p01 | p02             | p05 | p06 | p07 | p08 | p09       | p11 | p12 | p13 | p14       ;
         dsp_accum_2 <=     p00       | p02       | p04       | p06       | p08       | p10       | p12       | p14       ;
     end