Commit e2153595 authored by Andrey Filippov's avatar Andrey Filippov

working on dtt

parent 6a91d1aa
[*] [*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Tue Dec 13 19:43:18 2016 [*] Tue Dec 5 02:26:14 2017
[*] [*]
[dumpfile] "/home/eyesis/git/x393-neon/simulation/dct_tests_01-20161213123921501.fst" [dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/dct_tests_01-20171130150416223.fst"
[dumpfile_mtime] "Tue Dec 13 19:39:21 2016" [dumpfile_mtime] "Thu Nov 30 22:04:17 2017"
[dumpfile_size] 103386 [dumpfile_size] 105262
[savefile] "/home/eyesis/git/x393-neon/dct_tests_01.sav" [savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/dct_tests_01.sav"
[timestart] 0 [timestart] 0
[size] 1814 1171 [size] 1814 1167
[pos] 1912 0 [pos] 1940 0
*-19.687614 3465000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-18.730682 785000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] dct_tests_01. [treeopen] dct_tests_01.
[treeopen] dct_tests_01.dct_iv8_1d_i. [treeopen] dct_tests_01.dct_iv8_1d_i.
[treeopen] dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i. [treeopen] dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.
...@@ -19,11 +19,14 @@ ...@@ -19,11 +19,14 @@
[sst_width] 204 [sst_width] 204
[signals_width] 302 [signals_width] 302
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 344 [sst_vpaned_height] 343
@c00200 @800200
-top -top
@24 @24
dct_tests_01.i dct_tests_01.i
@420
dct_tests_01.i1
@24
dct_tests_01.j dct_tests_01.j
@28 @28
dct_tests_01.CLK dct_tests_01.CLK
...@@ -79,6 +82,7 @@ dct_tests_01.x_out[23:0] ...@@ -79,6 +82,7 @@ dct_tests_01.x_out[23:0]
@28 @28
[color] 2 [color] 2
dct_tests_01.start dct_tests_01.start
dct_tests_01.start2
dct_tests_01.y_dv dct_tests_01.y_dv
dct_tests_01.y_pre_we dct_tests_01.y_pre_we
@22 @22
...@@ -91,7 +95,8 @@ dct_tests_01.phase_y[3:0] ...@@ -91,7 +95,8 @@ dct_tests_01.phase_y[3:0]
dct_tests_01.y_dct[23:0] dct_tests_01.y_dct[23:0]
dct_tests_01.y_out[23:0] dct_tests_01.y_out[23:0]
dct_tests_01.dct_iv8_1d_i.y_index[2:0] dct_tests_01.dct_iv8_1d_i.y_index[2:0]
@1401200 dct_tests_01.x_in_2d[23:0]
@1000200
-top -top
@c00200 @c00200
-2d-1d -2d-1d
...@@ -203,7 +208,7 @@ dct_tests_01.dct_iv8_1d_i.dsp_post_add_1 ...@@ -203,7 +208,7 @@ dct_tests_01.dct_iv8_1d_i.dsp_post_add_1
dct_tests_01.dct_iv8_1d_i.dsp_accum_1 dct_tests_01.dct_iv8_1d_i.dsp_accum_1
@22 @22
dct_tests_01.dct_iv8_1d_i.dsp_p_1[47:0] dct_tests_01.dct_iv8_1d_i.dsp_p_1[47:0]
@800200 @c00200
-dsp_1 -dsp_1
@22 @22
dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.ain[24:0] dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.ain[24:0]
...@@ -235,7 +240,7 @@ dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.p_reg_cond[47:0] ...@@ -235,7 +240,7 @@ dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.p_reg_cond[47:0]
dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.p_reg[47:0] dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_1_i.p_reg[47:0]
@200 @200
- -
@1000200 @1401200
-dsp_1 -dsp_1
@22 @22
dct_tests_01.dct_iv8_1d_i.dsp_p_2[47:0] dct_tests_01.dct_iv8_1d_i.dsp_p_2[47:0]
...@@ -274,7 +279,7 @@ dct_tests_01.dct_iv8_1d_i.dsp_p_2[47:0] ...@@ -274,7 +279,7 @@ dct_tests_01.dct_iv8_1d_i.dsp_p_2[47:0]
dct_tests_01.dct_iv8_1d_i.phase_cnt[3:0] dct_tests_01.dct_iv8_1d_i.phase_cnt[3:0]
@22 @22
dct_tests_01.dct_iv8_1d_i.dout[23:0] dct_tests_01.dct_iv8_1d_i.dout[23:0]
@800200 @c00200
-dsp_2 -dsp_2
@22 @22
dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_2_i.ain[24:0] dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_2_i.ain[24:0]
...@@ -286,7 +291,7 @@ dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_2_i.ad_reg[24:0] ...@@ -286,7 +291,7 @@ dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_2_i.ad_reg[24:0]
dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_2_i.p_reg[47:0] dct_tests_01.dct_iv8_1d_i.dsp_ma_preadd_c_2_i.p_reg[47:0]
@200 @200
- -
@1000200 @1401200
-dsp_2 -dsp_2
@28 @28
dct_tests_01.dct_iv8_1d_i.en dct_tests_01.dct_iv8_1d_i.en
...@@ -393,10 +398,53 @@ dct_tests_01.d_out_2d[23:0] ...@@ -393,10 +398,53 @@ dct_tests_01.d_out_2d[23:0]
dct_tests_01.dv_2dr dct_tests_01.dv_2dr
@22 @22
dct_tests_01.d_out_2dr[23:0] dct_tests_01.d_out_2dr[23:0]
@8421 @8420
dct_tests_01.d_out_2dr[23:0] dct_tests_01.d_out_2dr[23:0]
@800200
-debug
@420
dct_tests_01.dct_iv_8x8_i.dcth_dout0[23:0]
@8420
dct_tests_01.dct_iv_8x8_i.dcth_dout0[23:0]
@420
dct_tests_01.dct_iv_8x8_i.dcth_dout1[23:0]
@8420
dct_tests_01.dct_iv_8x8_i.dcth_dout1[23:0]
@28
dct_tests_01.dct_iv_8x8_i.transpose_start
@22
dct_tests_01.dct_iv_8x8_i.transpose_debug_di[7:0]
@8022
dct_tests_01.dct_iv_8x8_i.transpose_debug_di[7:0]
@420
dct_tests_01.dct_iv_8x8_i.transpose_di[23:0]
@8420
dct_tests_01.dct_iv_8x8_i.transpose_di[23:0]
@22
dct_tests_01.dct_iv_8x8_i.transpose_wa[7:0]
@8022
dct_tests_01.dct_iv_8x8_i.transpose_wa[7:0]
@28
(0)dct_tests_01.dct_iv_8x8_i.transpose_we[1:0]
@22
dct_tests_01.dct_iv_8x8_i.transpose_cntr[6:0]
@8022
dct_tests_01.dct_iv_8x8_i.transpose_cntr[6:0]
@420
dct_tests_01.dct_iv_8x8_i.transpose_out[23:0]
@8420
dct_tests_01.dct_iv_8x8_i.transpose_out[23:0]
@22
dct_tests_01.dct_iv_8x8_i.dctv_xin0[23:0]
dct_tests_01.dct_iv_8x8_i.dctv_xin1[23:0]
@28
dct_tests_01.dct_iv_8x8_i.dctv_start_0_r
@29
dct_tests_01.dct_iv_8x8_i.dctv_start_1_r
@200 @200
- -
@1000200
-debug
@800200 @800200
-dct_iv_8x8 -dct_iv_8x8
@28 @28
......
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Tue Dec 5 05:26:29 2017
[*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/dct_tests_02-20171204214928041.fst"
[dumpfile_mtime] "Tue Dec 5 04:49:28 2017"
[dumpfile_size] 180339
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/dct_tests_02.sav"
[timestart] 1311000
[size] 1920 1171
[pos] -1723 40
*-19.492632 3855000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] dct_tests_02.
[treeopen] dct_tests_02.dtt_iv_8x8_i.
[sst_width] 204
[signals_width] 287
[sst_expanded] 1
[sst_vpaned_height] 344
@420
dct_tests_02.i
dct_tests_02.i1
dct_tests_02.j
@28
dct_tests_02.CLK
dct_tests_02.RST
[color] 2
dct_tests_02.start
[color] 2
dct_tests_02.start2
@22
dct_tests_02.mode_in[1:0]
dct_tests_02.mode_out[1:0]
dct_tests_02.x_in_2d[23:0]
@800200
-dtt_iv8x8_direct
@28
dct_tests_02.dtt_iv_8x8_i.rst
dct_tests_02.dtt_iv_8x8_i.clk
dct_tests_02.dtt_iv_8x8_i.start
@22
dct_tests_02.dtt_iv_8x8_i.mode[1:0]
dct_tests_02.dtt_iv_8x8_i.xin[23:0]
@8022
dct_tests_02.dtt_iv_8x8_i.xin[23:0]
@28
dct_tests_02.dtt_iv_8x8_i.pre_last_in
dct_tests_02.dtt_iv_8x8_i.pre_first_out
dct_tests_02.dtt_iv_8x8_i.dv
@420
dct_tests_02.dtt_iv_8x8_i.d_out[23:0]
@8420
dct_tests_02.dtt_iv_8x8_i.d_out[23:0]
@800200
-debug
@420
dct_tests_02.dtt_iv_8x8_i.dcth_dout0[23:0]
@8420
dct_tests_02.dtt_iv_8x8_i.dcth_dout0[23:0]
@420
dct_tests_02.dtt_iv_8x8_i.dcth_dout1[23:0]
@8420
dct_tests_02.dtt_iv_8x8_i.dcth_dout1[23:0]
@28
dct_tests_02.dtt_iv_8x8_i.transpose_start
@22
dct_tests_02.dtt_iv_8x8_i.transpose_debug_di[7:0]
@8022
dct_tests_02.dtt_iv_8x8_i.transpose_debug_di[7:0]
@420
dct_tests_02.dtt_iv_8x8_i.transpose_di[23:0]
@8420
dct_tests_02.dtt_iv_8x8_i.transpose_di[23:0]
@c00022
dct_tests_02.dtt_iv_8x8_i.transpose_wa[7:0]
@28
(0)dct_tests_02.dtt_iv_8x8_i.transpose_wa[7:0]
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(2)dct_tests_02.dtt_iv_8x8_i.transpose_wa[7:0]
(3)dct_tests_02.dtt_iv_8x8_i.transpose_wa[7:0]
(4)dct_tests_02.dtt_iv_8x8_i.transpose_wa[7:0]
(5)dct_tests_02.dtt_iv_8x8_i.transpose_wa[7:0]
(6)dct_tests_02.dtt_iv_8x8_i.transpose_wa[7:0]
(7)dct_tests_02.dtt_iv_8x8_i.transpose_wa[7:0]
@1401200
-group_end
@c08022
dct_tests_02.dtt_iv_8x8_i.transpose_wa[7:0]
@28
(0)dct_tests_02.dtt_iv_8x8_i.transpose_wa[7:0]
(1)dct_tests_02.dtt_iv_8x8_i.transpose_wa[7:0]
(2)dct_tests_02.dtt_iv_8x8_i.transpose_wa[7:0]
(3)dct_tests_02.dtt_iv_8x8_i.transpose_wa[7:0]
(4)dct_tests_02.dtt_iv_8x8_i.transpose_wa[7:0]
(5)dct_tests_02.dtt_iv_8x8_i.transpose_wa[7:0]
(6)dct_tests_02.dtt_iv_8x8_i.transpose_wa[7:0]
(7)dct_tests_02.dtt_iv_8x8_i.transpose_wa[7:0]
@1401200
-group_end
@28
(0)dct_tests_02.dtt_iv_8x8_i.transpose_we[1:0]
dct_tests_02.dtt_iv_8x8_i.pre_dsth
@8022
dct_tests_02.dtt_iv_8x8_i.transpose_cntr[6:0]
@22
dct_tests_02.dtt_iv_8x8_i.transpose_ra[7:0]
dct_tests_02.dtt_iv_8x8_i.transpose_reg[23:0]
@420
dct_tests_02.dtt_iv_8x8_i.transpose_out[23:0]
@8420
dct_tests_02.dtt_iv_8x8_i.transpose_out[23:0]
@22
dct_tests_02.dtt_iv_8x8_i.dctv_xin0[23:0]
dct_tests_02.dtt_iv_8x8_i.dctv_xin1[23:0]
@28
dct_tests_02.dtt_iv_8x8_i.dctv_start_0_r
dct_tests_02.dtt_iv_8x8_i.dctv_start_1_r
dct_tests_02.dtt_iv_8x8_i.dctv_out_sel
dct_tests_02.dtt_iv_8x8_i.dctv_out_we_2
@800028
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@28
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(1)dct_tests_02.dtt_iv_8x8_i.pre2_dstv[1:0]
@1001200
-group_end
@28
(0)dct_tests_02.dtt_iv_8x8_i.dctv_out_we_1[1:0]
@420
dct_tests_02.dtt_iv_8x8_i.dctv_dout0[23:0]
dct_tests_02.dtt_iv_8x8_i.dctv_dout1[23:0]
@8420
dct_tests_02.dtt_iv_8x8_i.dctv_dout0[23:0]
dct_tests_02.dtt_iv_8x8_i.dctv_dout1[23:0]
@420
dct_tests_02.dtt_iv_8x8_i.debug_dctv_dout[23:0]
@8420
dct_tests_02.dtt_iv_8x8_i.debug_dctv_dout[23:0]
@420
dct_tests_02.dtt_iv_8x8_i.dctv_out_reg_1[23:0]
dct_tests_02.dtt_iv_8x8_i.dctv_out_reg_2[23:0]
@8420
dct_tests_02.dtt_iv_8x8_i.dctv_out_reg_1[23:0]
dct_tests_02.dtt_iv_8x8_i.dctv_out_reg_2[23:0]
@1000200
-debug
@22
dct_tests_02.dtt_iv_8x8_i.mode_out[1:0]
@28
dct_tests_02.dtt_iv_8x8_i.pre_first_out_w
dct_tests_02.dtt_iv_8x8_i.pre_first_out
dct_tests_02.dtt_iv_8x8_i.pre_busy
@800200
-direct_internal
@28
dct_tests_02.dtt_iv_8x8_i.dcth_en0
dct_tests_02.dtt_iv_8x8_i.dcth_en1
dct_tests_02.dtt_iv_8x8_i.dcth_start_0_r
dct_tests_02.dtt_iv_8x8_i.dcth_start_1_r
@22
dct_tests_02.dtt_iv_8x8_i.mode[1:0]
dct_tests_02.dtt_iv_8x8_i.mode_h[1:0]
dct_tests_02.dtt_iv_8x8_i.mode_h_late[1:0]
dct_tests_02.dtt_iv_8x8_i.mode_v[1:0]
dct_tests_02.dtt_iv_8x8_i.mode_out[1:0]
@28
dct_tests_02.dtt_iv_8x8_i.dctv_start_0_w
@22
dct_tests_02.dtt_iv_8x8_i.dctv_start_1_w
@800028
dct_tests_02.dtt_iv_8x8_i.pre2_dsth[1:0]
@28
(0)dct_tests_02.dtt_iv_8x8_i.pre2_dsth[1:0]
(1)dct_tests_02.dtt_iv_8x8_i.pre2_dsth[1:0]
@1001200
-group_end
@200
-
@800028
dct_tests_02.dtt_iv_8x8_i.pre2_dstv[1:0]
@28
(0)dct_tests_02.dtt_iv_8x8_i.pre2_dstv[1:0]
(1)dct_tests_02.dtt_iv_8x8_i.pre2_dstv[1:0]
@800200
-g3
@28
dct_tests_02.dtt_iv_8x8_i.dct_iv8_1d_pass2_0_i.start
dct_tests_02.dtt_iv_8x8_i.dct_iv8_1d_pass2_0_i.dst_in
dct_tests_02.dtt_iv_8x8_i.dct_iv8_1d_pass2_0_i.dst_out
@1000200
-g3
@28
dct_tests_02.dtt_iv_8x8_i.dct_iv8_1d_pass2_1_i.start
dct_tests_02.dtt_iv_8x8_i.dct_iv8_1d_pass2_1_i.dst_in
@29
dct_tests_02.dtt_iv_8x8_i.dct_iv8_1d_pass2_1_i.dst_out
@200
-
@1001200
-group_end
@1000200
-direct_internal
-dtt_iv8x8_direct
@800200
-dtt_iv8x8_inv
@200
-
@1000200
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@200
-dbg
[pattern_trace] 1
[pattern_trace] 0
...@@ -66,7 +66,7 @@ module dtt_iv8_1d#( ...@@ -66,7 +66,7 @@ module dtt_iv8_1d#(
input clk, input clk,
input rst, input rst,
input en, input en,
input dst_in, // 0 - dct, 1 - dst. @ start/restart input dst_in, // 0 - dct, 1 - dst. @ start only, no restart
input [WIDTH -1:0] d_in, // X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X6-X7-* input [WIDTH -1:0] d_in, // X2-X7-X3-X4-X5-X6-X0-X1-*-X3-X5-X4-*-X6-X7-*
input start, // one cycle before first X6 input input start, // one cycle before first X6 input
output [OUT_WIDTH -1:0] dout, output [OUT_WIDTH -1:0] dout,
...@@ -75,6 +75,7 @@ module dtt_iv8_1d#( ...@@ -75,6 +75,7 @@ module dtt_iv8_1d#(
// In DST mode the sequence is the same (to be inverted), but // In DST mode the sequence is the same (to be inverted), but
// Y0, Y2, Y4 and Y6 are negated // Y0, Y2, Y4 and Y6 are negated
output en_out, // valid at the same time slot as pre2_start_out (goes active with pre2_start_out), 2 ahead of data output en_out, // valid at the same time slot as pre2_start_out (goes active with pre2_start_out), 2 ahead of data
output dst_out, // valid with en_out
output reg [2:0] y_index // for simulation - valid with dout - index of the data output output reg [2:0] y_index // for simulation - valid with dout - index of the data output
); );
...@@ -140,7 +141,10 @@ module dtt_iv8_1d#( ...@@ -140,7 +141,10 @@ module dtt_iv8_1d#(
reg en_out_r2; reg en_out_r2;
reg dst_pre; // keeps dst_in value for second stage reg dst_pre; // keeps dst_in value for second stage
reg dst_out; // controls source of dsp_neg_m_2 mux reg dst_2; // controls source of dsp_neg_m_2 mux
reg dst_out_r; // // 2 ahead of data out
assign dst_out = dst_out_r;
assign en_out = en_out_r; assign en_out = en_out_r;
...@@ -162,14 +166,14 @@ module dtt_iv8_1d#( ...@@ -162,14 +166,14 @@ module dtt_iv8_1d#(
en_out_r2 <= en_out_r; en_out_r2 <= en_out_r;
if (en_out_r2) begin if (en_out_r2) begin
case (phase_cnt[3:1]) case (phase_cnt[3:1])
3'h0: y_index <= 0; 3'h0: y_index <= dst_out_r ? 7 : 0;
3'h1: y_index <= 7; 3'h1: y_index <= dst_out_r ? 0 : 7;
3'h2: y_index <= 4; 3'h2: y_index <= dst_out_r ? 3 : 4;
3'h3: y_index <= 3; 3'h3: y_index <= dst_out_r ? 4 : 3;
3'h4: y_index <= 1; 3'h4: y_index <= dst_out_r ? 6 : 1;
3'h5: y_index <= 6; 3'h5: y_index <= dst_out_r ? 1 : 6;
3'h6: y_index <= 2; 3'h6: y_index <= dst_out_r ? 5 : 2;
3'h7: y_index <= 5; 3'h7: y_index <= dst_out_r ? 2 : 5;
endcase endcase
end else begin end else begin
y_index <= 'bx; y_index <= 'bx;
...@@ -193,11 +197,14 @@ module dtt_iv8_1d#( ...@@ -193,11 +197,14 @@ module dtt_iv8_1d#(
else if (start || restart) run_in <= 1; else if (start || restart) run_in <= 1;
else if (phase_cnt==15) run_in <= 0; else if (phase_cnt==15) run_in <= 0;
if (start || restart) dst_pre <= dst_in; // if (start || restart) dst_pre <= dst_in;
if (start) dst_pre <= dst_in;
if (phase_cnt == 12) dst_2 <= dst_pre;
if (phase_cnt == 14) dst_out_r <= dst_2;
if (phase_cnt == 12) dst_out <= dst_pre;
dsp_neg_m_2 <= dst_out ? dsp_neg_m_2_dst : dsp_neg_m_2_dct; dsp_neg_m_2 <= dst_2 ? dsp_neg_m_2_dst : dsp_neg_m_2_dct;
if (rst) run_out <= 0; if (rst) run_out <= 0;
else if (phase_cnt == 13) run_out <= run_in; else if (phase_cnt == 13) run_out <= run_in;
...@@ -280,7 +287,7 @@ module dtt_iv8_1d#( ...@@ -280,7 +287,7 @@ module dtt_iv8_1d#(
dsp_selb_2 <= p00 | p03 | p05 | p06 | p08 | p11 | p13 | p14 ; dsp_selb_2 <= p00 | p03 | p05 | p06 | p08 | p11 | p13 | p14 ;
// dsp_neg_m_2 <= p03 | p06 | p12 | p15 ; // dsp_neg_m_2 <= p03 | p06 | p12 | p15 ;
dsp_neg_m_2_dct <= p02 | p05 | p11 | p14 ; dsp_neg_m_2_dct <= p02 | p05 | p11 | p14 ;
dsp_neg_m_2_dst <= p00 | p01 | p02 | p05 | p06 | p07 | p08 | p09 | p11 | p14 ; dsp_neg_m_2_dst <= p00 | p01 | p02 | p05 | p06 | p07 | p08 | p09 | p11 | p12 | p13 | p14 ;
dsp_accum_2 <= p00 | p02 | p04 | p06 | p08 | p10 | p12 | p14 ; dsp_accum_2 <= p00 | p02 | p04 | p06 | p08 | p10 | p12 | p14 ;
end end
......
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