Commit e194837a authored by Andrey Filippov's avatar Andrey Filippov

tweaking Eyesis startup

parent ea0f8823
......@@ -4,7 +4,9 @@
-l /usr/local/verilog/x393_cur_params_target.vh
-p PICKLE="/usr/local/verilog/x393_mcntrl.pickle
-c bitstream_set_path /usr/local/verilog/x393_parallel.bit
-c setupEyesisPower 50 100
-c setupSensorsPower "PAR12" all 0 0.0
-c setEyesisPower 1
-c sleep_ms 20
-c measure_all "*DI"
-c setSensorClock 24.0 "2V5_LVDS"
-c set_rtc
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