Loading py393/hargs-eyesis +3 −1 Original line number Diff line number Diff line Loading @@ -4,7 +4,9 @@ -l /usr/local/verilog/x393_cur_params_target.vh -p PICKLE="/usr/local/verilog/x393_mcntrl.pickle -c bitstream_set_path /usr/local/verilog/x393_parallel.bit -c setupEyesisPower 50 100 -c setupSensorsPower "PAR12" all 0 0.0 -c setEyesisPower 1 -c sleep_ms 20 -c measure_all "*DI" -c setSensorClock 24.0 "2V5_LVDS" -c set_rtc Loading
py393/hargs-eyesis +3 −1 Original line number Diff line number Diff line Loading @@ -4,7 +4,9 @@ -l /usr/local/verilog/x393_cur_params_target.vh -p PICKLE="/usr/local/verilog/x393_mcntrl.pickle -c bitstream_set_path /usr/local/verilog/x393_parallel.bit -c setupEyesisPower 50 100 -c setupSensorsPower "PAR12" all 0 0.0 -c setEyesisPower 1 -c sleep_ms 20 -c measure_all "*DI" -c setSensorClock 24.0 "2V5_LVDS" -c set_rtc