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x393
Commit df889f79 authored by Andrey Filippov's avatar Andrey Filippov
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left from May,17 2021

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fpga_version.vh
View file @ df889f79
......@@ -35,7 +35,9 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03934014; // Boson640, for 103993A, debugging 4 removed DE deglitch
parameter FPGA_VERSION = 32'h03934015; // Boson640, for 103993A, debugging 4 removed DE deglitch - modifying decimation
// parameter FPGA_VERSION = 32'h03931004; // parallel, adding camsync trigger decimation - modifying decimation
// parameter FPGA_VERSION = 32'h03934014; // Boson640, for 103993A, debugging 4 removed DE deglitch
// parameter FPGA_VERSION = 32'h03934013; // Boson640, for 103993A, debugging 3 failed (maybe just phases)
// parameter FPGA_VERSION = 32'h03934012; // Boson640, for 103993A, debugging 2 works, shifted by 1 pix hor (found bug)
// parameter FPGA_VERSION = 32'h03934011; // Boson640, for 103993A, debugging 1
......
py393/x393_export_c.py
View file @ df889f79
......@@ -598,6 +598,10 @@ class X393ExportC(object):
data = self._enc_camsync_mode(),
name = "x393_camsync_mode", typ="wo",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "CAMSYNC decimation mode",
data = self._enc_camsync_decimate(),
name = "x393_camsync_decimate", typ="wo",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "CMDFRAMESEQ mode",
data = self._enc_cmdframeseq_mode(),
name = "x393_cmdframeseq_mode", typ="wo",
......@@ -1116,9 +1120,15 @@ class X393ExportC(object):
ba = vrlg.CAMSYNC_DECIMATE_ADDR
ia = 0
c = "sens_chn"
"""
sdefines +=[
(('CAMSYNC trigger decimation',)),
(("X393_CAMSYNC_TRIG_DECIMATION", c, 0 + ba, 1, z3, "u32*", "rw", "CAMSYNC trigger decimation"))]
"""
sdefines +=[
(('CAMSYNC trigger decimation',)),
(("X393_CAMSYNC_TRIG_DECIMATION", c, 0 + ba, 1, z3, "x393_camsync_decimate", "rw", "CAMSYNC trigger decimation"))]
ba = vrlg.CMDFRAMESEQ_ADDR_BASE
ia = vrlg.CMDFRAMESEQ_ADDR_INC
......@@ -2602,6 +2612,7 @@ class X393ExportC(object):
dw.append(("line8", 16, 2, 1, "line 8 mode: 0 - inactive, 1 - keep (nop), 2 - active low, 3 - active high"))
dw.append(("line9", 18, 2, 1, "line 9 mode: 0 - inactive, 1 - keep (nop), 2 - active low, 3 - active high"))
return dw
def _enc_camsync_mode(self):
dw=[]
dw.append(("en", vrlg.CAMSYNC_EN_BIT-1, 1, 1, "Enable CAMSYNC module"))
......@@ -2618,6 +2629,12 @@ class X393ExportC(object):
dw.append(("ts_chns_set", vrlg.CAMSYNC_CHN_EN_BIT - 3, 4, 0, "Sets for 'ts_chns' (each bit controls corresponding 'ts_chns' bit)"))
return dw
def _enc_camsync_decimate(self):
dw=[]
dw.append(("decimate", 0, vrlg.CAMSYNC_DECIMATE_BITS, 0, "Trigger decimation minus 1 value. 'decimate==0' - each trigger goes through, 1 - each other."))
dw.append(("first_pulse", vrlg.CAMSYNC_DECIMATE_BITS, 1, 0, "If set, the first incoming trigger will go through, if 0 - decimation will be applied to the next cycle"))
return dw
def _enc_cmdframeseq_mode(self):
dw=[]
dw.append(("interrupt_cmd", vrlg.CMDFRAMESEQ_IRQ_BIT, 2, 0, "Interrupt command: 0-nop, 1 - clear is, 2 - disable, 3 - enable"))
......
sensor/sensor_channel.v
View file @ df889f79
......@@ -1483,7 +1483,7 @@ module sensor_channel#(
.IPCLK_PHASE (IPCLK1X_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.BUF_IPCLK1X (BUF_IPCLK1X),
.BUF_IPCLK (BUF_IPCLK1X),
.BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
......
system_defines.vh
View file @ df889f79
......@@ -63,10 +63,11 @@
`define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels
`define BOSON 1 /*************** CHANGE here and x393_hispi/x393_parallel/x393_lwir/x393_boson in bitstream tool settings ****************/
// `define LWIR /*************** CHANGE here and x393_hispi/x393_parallel/x393_lwir in bitstream tool settings ****************/
// `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
// if specific sesnor is not defined, parallel sensor interface is used for all channels
/*************** CHANGE here and x393_hispi | x393_parallel | x393_lwir | x393_boson in bitstream (and few other) tool settings ****************/
`define BOSON 1
// `define LWIR
// `define HISPI
// also change in utilization and timimg summary tools (x393_parallel_utilization.report, ...)
`ifdef BOSON
......@@ -75,7 +76,7 @@
`elsif HISPI
`else
`define PAR12 // use default sensors interface
`define PAR12 1 // use default sensors interface
`endif
......
timing/camsync393.v
View file @ df889f79
......@@ -227,6 +227,7 @@ module camsync393 #(
wire decimate_we; // write trigger decimate (per-cnannel)
wire [3:0] set_decimate; // @mclk per channel - set decimate value (0 - every trigger, 1 - every second, 2 - every third, ...)
wire [3:0] reset_decimate; // @pclk - reset decimate counter, so next pulse will go through
wire [3:0] reset_decimate_mclk; // Makes next trigger to go through, enabled by data bit[16]
wire set_mode_reg_w;
wire set_trig_src_w;
......@@ -467,6 +468,11 @@ module camsync393 #(
assign set_decimate[2] = decimate_we && (cmd_a[1:0] == 2);
assign set_decimate[3] = decimate_we && (cmd_a[1:0] == 3);
assign reset_decimate_mclk[0] = set_decimate[0] & cmd_data[CAMSYNC_DECIMATE_BITS];
assign reset_decimate_mclk[1] = set_decimate[1] & cmd_data[CAMSYNC_DECIMATE_BITS];
assign reset_decimate_mclk[2] = set_decimate[2] & cmd_data[CAMSYNC_DECIMATE_BITS];
assign reset_decimate_mclk[3] = set_decimate[3] & cmd_data[CAMSYNC_DECIMATE_BITS];
assign pre_input_use = {cmd_data[19],cmd_data[17],cmd_data[15],cmd_data[13],cmd_data[11],
cmd_data[9],cmd_data[7],cmd_data[5],cmd_data[3],cmd_data[1]};
assign pre_input_pattern = {cmd_data[18],cmd_data[16],cmd_data[14],cmd_data[12],cmd_data[10],
......@@ -1003,10 +1009,10 @@ module camsync393 #(
pulse_cross_clock i_suppress_immediate_set_pclk(.rst(!en), .src_clk(mclk), .dst_clk(pclk), .in_pulse(suppress_immediate_set_mclk), .out_pulse(suppress_immediate_set_pclk),.busy());
pulse_cross_clock i_rdecim_to_pclk0 (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(set_decimate[0]), .out_pulse(reset_decimate[0]),.busy());
pulse_cross_clock i_rdecim_to_pclk1 (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(set_decimate[1]), .out_pulse(reset_decimate[1]),.busy());
pulse_cross_clock i_rdecim_to_pclk2 (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(set_decimate[2]), .out_pulse(reset_decimate[2]),.busy());
pulse_cross_clock i_rdecim_to_pclk3 (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(set_decimate[3]), .out_pulse(reset_decimate[3]),.busy());
pulse_cross_clock i_rdecim_to_pclk0 (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(reset_decimate_mclk[0]), .out_pulse(reset_decimate[0]),.busy());
pulse_cross_clock i_rdecim_to_pclk1 (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(reset_decimate_mclk[1]), .out_pulse(reset_decimate[1]),.busy());
pulse_cross_clock i_rdecim_to_pclk2 (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(reset_decimate_mclk[2]), .out_pulse(reset_decimate[2]),.busy());
pulse_cross_clock i_rdecim_to_pclk3 (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(reset_decimate_mclk[3]), .out_pulse(reset_decimate[3]),.busy());
endmodule
......
x393_parallel.bit
View file @ df889f79
No preview for this file type
x393_parallel.report 0 → 100644
View file @ df889f79
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Sun May 16 16:32:01 2021
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization -file vivado_build/x393_parallel.report
| Design : x393
| Device : 7z030fbg484-1
| Design State : Routed
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 41686 | 0 | 78600 | 53.04 |
| LUT as Logic | 38300 | 0 | 78600 | 48.73 |
| LUT as Memory | 3386 | 0 | 26600 | 12.73 |
| LUT as Distributed RAM | 2850 | 0 | | |
| LUT as Shift Register | 536 | 0 | | |
| Slice Registers | 54215 | 0 | 157200 | 34.49 |
| Register as Flip Flop | 54215 | 0 | 157200 | 34.49 |
| Register as Latch | 0 | 0 | 157200 | 0.00 |
| F7 Muxes | 30 | 0 | 39300 | 0.08 |
| F8 Muxes | 0 | 0 | 19650 | 0.00 |
+----------------------------+-------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 16 | Yes | - | Set |
| 692 | Yes | - | Reset |
| 954 | Yes | Set | - |
| 52553 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+-------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+
| Slice | 16383 | 0 | 19650 | 83.37 |
| SLICEL | 10774 | 0 | | |
| SLICEM | 5609 | 0 | | |
| LUT as Logic | 38300 | 0 | 78600 | 48.73 |
| using O5 output only | 3 | | | |
| using O6 output only | 29756 | | | |
| using O5 and O6 | 8541 | | | |
| LUT as Memory | 3386 | 0 | 26600 | 12.73 |
| LUT as Distributed RAM | 2850 | 0 | | |
| using O5 output only | 2 | | | |
| using O6 output only | 84 | | | |
| using O5 and O6 | 2764 | | | |
| LUT as Shift Register | 536 | 0 | | |
| using O5 output only | 254 | | | |
| using O6 output only | 230 | | | |
| using O5 and O6 | 52 | | | |
| LUT Flip Flop Pairs | 24377 | 0 | 78600 | 31.01 |
| fully used LUT-FF pairs | 4602 | | | |
| LUT-FF pairs with one unused LUT output | 17723 | | | |
| LUT-FF pairs with one unused Flip Flop | 17425 | | | |
| Unique Control Sets | 4570 | | | |
+-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 85 | 0 | 265 | 32.08 |
| RAMB36/FIFO* | 54 | 0 | 265 | 20.38 |
| RAMB36E1 only | 54 | | | |
| RAMB18 | 62 | 0 | 530 | 11.70 |
| RAMB18E1 only | 62 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs | 76 | 0 | 400 | 19.00 |
| DSP48E1 only | 76 | | | |
+----------------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 151 | 151 | 163 | 92.64 |
| IOB Master Pads | 73 | | | |
| IOB Slave Pads | 76 | | | |
| Bonded IPADs | 4 | 4 | 14 | 28.57 |
| Bonded OPADs | 2 | 2 | 8 | 25.00 |
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 3 | 0 | 5 | 60.00 |
| IBUFDS | 2 | 2 | 155 | 1.29 |
| GTXE2_COMMON | 0 | 0 | 1 | 0.00 |
| GTXE2_CHANNEL | 1 | 1 | 4 | 25.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 78 | 78 | 250 | 31.20 |
| IDELAYE2 only | 60 | 60 | | |
| IDELAYE2_FINEDELAY only | 18 | 18 | | |
| ODELAYE2/ODELAYE2_FINEDELAY | 43 | 43 | 150 | 28.67 |
| ODELAYE2_FINEDELAY only | 43 | 43 | | |
| IBUFDS_GTE2 | 1 | 1 | 2 | 50.00 |
| ILOGIC | 72 | 72 | 163 | 44.17 |
| ISERDES | 72 | 72 | | |
| OLOGIC | 48 | 48 | 163 | 29.45 |
| OUTFF_ODDR_Register | 5 | 5 | | |
| OSERDES | 43 | 43 | | |
+-----------------------------+------+-------+-----------+-------+
6. Clocking
-----------
+--------------+------+-------+-----------+--------+
| Site Type | Used | Fixed | Available | Util% |
+--------------+------+-------+-----------+--------+
| BUFGCTRL | 14 | 0 | 32 | 43.75 |
| BUFIO | 3 | 0 | 20 | 15.00 |
| BUFIO only | 3 | 0 | | |
| MMCME2_ADV | 5 | 0 | 5 | 100.00 |
| PLLE2_ADV | 2 | 0 | 5 | 40.00 |
| BUFMRCE | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 96 | 0.00 |
| BUFR | 6 | 0 | 20 | 30.00 |
+--------------+------+-------+-----------+--------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+------------------------+-------+----------------------+
| Ref Name | Used | Functional Category |
+------------------------+-------+----------------------+
| FDRE | 52553 | Flop & Latch |
| LUT3 | 11295 | LUT |
| LUT6 | 10183 | LUT |
| LUT2 | 8397 | LUT |
| LUT4 | 7776 | LUT |
| LUT5 | 7570 | LUT |
| RAMD32 | 4198 | Distributed Memory |
| CARRY4 | 2809 | CarryLogic |
| LUT1 | 1620 | LUT |
| RAMS32 | 1416 | Distributed Memory |
| FDSE | 954 | Flop & Latch |
| FDCE | 692 | Flop & Latch |
| SRL16E | 484 | Distributed Memory |
| OBUFT | 121 | IO |
| SRLC32E | 104 | Distributed Memory |
| IBUF | 99 | IO |
| DSP48E1 | 76 | Block Arithmetic |
| ISERDESE2 | 72 | IO |
| RAMB18E1 | 62 | Block Memory |
| IDELAYE2 | 60 | IO |
| RAMB36E1 | 54 | Block Memory |
| OSERDESE2 | 43 | IO |
| ODELAYE2_FINEDELAY | 43 | IO |
| MUXF7 | 30 | MuxFx |
| OBUFT_DCIEN | 18 | IO |
| IDELAYE2_FINEDELAY | 18 | IO |
| IBUF_IBUFDISABLE | 18 | IO |
| PULLUP | 16 | I/O |
| FDPE | 16 | Flop & Latch |
| BUFG | 14 | Clock |
| BUFR | 6 | Clock |
| ODDR | 5 | IO |
| MMCME2_ADV | 5 | Clock |
| OBUFTDS_DCIEN | 4 | IO |
| IBUFDS_IBUFDISABLE_INT | 4 | IO |
| OBUF | 3 | IO |
| INV | 3 | LUT |
| IDELAYCTRL | 3 | IO |
| BUFIO | 3 | Clock |
| PLLE2_ADV | 2 | Clock |
| OBUFTDS | 2 | IO |
| IBUFDS | 2 | IO |
| PS7 | 1 | Specialized Resource |
| IBUFDS_GTE2 | 1 | IO |
| GTXE2_CHANNEL | 1 | IO |
| DCIRESET | 1 | Others |
+------------------------+-------+----------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
x393_parallel.timing_summary_impl
View file @ df889f79
This source diff could not be displayed because it is too large. You can view the blob instead.
x393_placement.tcl
View file @ df889f79
......@@ -56,6 +56,8 @@ seek $infile 0 start
while { [gets $infile line] >= 0 } {
if { [regexp {(.*)`define(\s*)BOSON} $line matched prematch] } {
if {[regexp "//" $prematch] != 0} { continue }
puts $line
if {[regexp {(.*)`define(\s*)BOSON_REVA} $line matched prematch] } { continue }
set BOSON 1
break
}
......
x393_timing.tcl
View file @ df889f79
......@@ -56,6 +56,8 @@ seek $infile 0 start
while { [gets $infile line] >= 0 } {
if { [regexp {(.*)`define(\s*)BOSON} $line matched prematch] } {
if {[regexp "//" $prematch] != 0} { continue }
puts $line
if {[regexp {(.*)`define(\s*)BOSON_REVA} $line matched prematch] } { continue }
set BOSON 1
break
}
......@@ -67,7 +69,7 @@ if { $LWIR} {
} elseif { $HISPI} {
puts "x393_timing.tcl: using HISPI sensors"
} elseif { $BOSON} {
puts "x393_placement.tcl: using Boson640 sensors"
puts "x393_timing.tcl: using Boson640 sensors"
} else {
puts "x393_timing.tcl: using parallel sensors"
}
......
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