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x393
Commit df889f79 authored by Andrey Filippov's avatar Andrey Filippov
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left from May,17 2021

parent b732c0f0
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Showing with 1687 additions and 1409 deletions
fpga_version.vh
View file @ df889f79
......@@ -35,8 +35,10 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03934014; // Boson640, for 103993A, debugging 4 removed DE deglitch
// parameter FPGA_VERSION = 32'h03934013; // Boson640, for 103993A, debugging 3 failed (maybe just phases)
parameter FPGA_VERSION = 32'h03934015; // Boson640, for 103993A, debugging 4 removed DE deglitch - modifying decimation
// parameter FPGA_VERSION = 32'h03931004; // parallel, adding camsync trigger decimation - modifying decimation
// parameter FPGA_VERSION = 32'h03934014; // Boson640, for 103993A, debugging 4 removed DE deglitch
// parameter FPGA_VERSION = 32'h03934013; // Boson640, for 103993A, debugging 3 failed (maybe just phases)
// parameter FPGA_VERSION = 32'h03934012; // Boson640, for 103993A, debugging 2 works, shifted by 1 pix hor (found bug)
// parameter FPGA_VERSION = 32'h03934011; // Boson640, for 103993A, debugging 1
// parameter FPGA_VERSION = 32'h03934010; // Boson640, for 103993A
......
py393/x393_export_c.py
View file @ df889f79
......@@ -598,6 +598,10 @@ class X393ExportC(object):
data = self._enc_camsync_mode(),
name = "x393_camsync_mode", typ="wo",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "CAMSYNC decimation mode",
data = self._enc_camsync_decimate(),
name = "x393_camsync_decimate", typ="wo",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "CMDFRAMESEQ mode",
data = self._enc_cmdframeseq_mode(),
name = "x393_cmdframeseq_mode", typ="wo",
......@@ -1116,9 +1120,15 @@ class X393ExportC(object):
ba = vrlg.CAMSYNC_DECIMATE_ADDR
ia = 0
c = "sens_chn"
"""
sdefines +=[
(('CAMSYNC trigger decimation',)),
(("X393_CAMSYNC_TRIG_DECIMATION", c, 0 + ba, 1, z3, "u32*", "rw", "CAMSYNC trigger decimation"))]
"""
sdefines +=[
(('CAMSYNC trigger decimation',)),
(("X393_CAMSYNC_TRIG_DECIMATION", c, 0 + ba, 1, z3, "x393_camsync_decimate", "rw", "CAMSYNC trigger decimation"))]
ba = vrlg.CMDFRAMESEQ_ADDR_BASE
ia = vrlg.CMDFRAMESEQ_ADDR_INC
......@@ -2602,6 +2612,7 @@ class X393ExportC(object):
dw.append(("line8", 16, 2, 1, "line 8 mode: 0 - inactive, 1 - keep (nop), 2 - active low, 3 - active high"))
dw.append(("line9", 18, 2, 1, "line 9 mode: 0 - inactive, 1 - keep (nop), 2 - active low, 3 - active high"))
return dw
def _enc_camsync_mode(self):
dw=[]
dw.append(("en", vrlg.CAMSYNC_EN_BIT-1, 1, 1, "Enable CAMSYNC module"))
......@@ -2618,6 +2629,12 @@ class X393ExportC(object):
dw.append(("ts_chns_set", vrlg.CAMSYNC_CHN_EN_BIT - 3, 4, 0, "Sets for 'ts_chns' (each bit controls corresponding 'ts_chns' bit)"))
return dw
def _enc_camsync_decimate(self):
dw=[]
dw.append(("decimate", 0, vrlg.CAMSYNC_DECIMATE_BITS, 0, "Trigger decimation minus 1 value. 'decimate==0' - each trigger goes through, 1 - each other."))
dw.append(("first_pulse", vrlg.CAMSYNC_DECIMATE_BITS, 1, 0, "If set, the first incoming trigger will go through, if 0 - decimation will be applied to the next cycle"))
return dw
def _enc_cmdframeseq_mode(self):
dw=[]
dw.append(("interrupt_cmd", vrlg.CMDFRAMESEQ_IRQ_BIT, 2, 0, "Interrupt command: 0-nop, 1 - clear is, 2 - disable, 3 - enable"))
......
sensor/sensor_channel.v
View file @ df889f79
......@@ -1483,7 +1483,7 @@ module sensor_channel#(
.IPCLK_PHASE (IPCLK1X_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.BUF_IPCLK1X (BUF_IPCLK1X),
.BUF_IPCLK (BUF_IPCLK1X),
.BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
......
system_defines.vh
View file @ df889f79
......@@ -62,11 +62,12 @@
// End of parameters from x393_sata project
`define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels
`define BOSON 1 /*************** CHANGE here and x393_hispi/x393_parallel/x393_lwir/x393_boson in bitstream tool settings ****************/
// `define LWIR /*************** CHANGE here and x393_hispi/x393_parallel/x393_lwir in bitstream tool settings ****************/
// `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
`define DISPLAY_COMPRESSED_DATA
// if specific sesnor is not defined, parallel sensor interface is used for all channels
/*************** CHANGE here and x393_hispi | x393_parallel | x393_lwir | x393_boson in bitstream (and few other) tool settings ****************/
`define BOSON 1
// `define LWIR
// `define HISPI
// also change in utilization and timimg summary tools (x393_parallel_utilization.report, ...)
`ifdef BOSON
......@@ -75,7 +76,7 @@
`elsif HISPI
`else
`define PAR12 // use default sensors interface
`define PAR12 1 // use default sensors interface
`endif
......
timing/camsync393.v
View file @ df889f79
......@@ -227,6 +227,7 @@ module camsync393 #(
wire decimate_we; // write trigger decimate (per-cnannel)
wire [3:0] set_decimate; // @mclk per channel - set decimate value (0 - every trigger, 1 - every second, 2 - every third, ...)
wire [3:0] reset_decimate; // @pclk - reset decimate counter, so next pulse will go through
wire [3:0] reset_decimate_mclk; // Makes next trigger to go through, enabled by data bit[16]
wire set_mode_reg_w;
wire set_trig_src_w;
......@@ -467,6 +468,11 @@ module camsync393 #(
assign set_decimate[2] = decimate_we && (cmd_a[1:0] == 2);
assign set_decimate[3] = decimate_we && (cmd_a[1:0] == 3);
assign reset_decimate_mclk[0] = set_decimate[0] & cmd_data[CAMSYNC_DECIMATE_BITS];
assign reset_decimate_mclk[1] = set_decimate[1] & cmd_data[CAMSYNC_DECIMATE_BITS];
assign reset_decimate_mclk[2] = set_decimate[2] & cmd_data[CAMSYNC_DECIMATE_BITS];
assign reset_decimate_mclk[3] = set_decimate[3] & cmd_data[CAMSYNC_DECIMATE_BITS];
assign pre_input_use = {cmd_data[19],cmd_data[17],cmd_data[15],cmd_data[13],cmd_data[11],
cmd_data[9],cmd_data[7],cmd_data[5],cmd_data[3],cmd_data[1]};
assign pre_input_pattern = {cmd_data[18],cmd_data[16],cmd_data[14],cmd_data[12],cmd_data[10],
......@@ -1003,10 +1009,10 @@ module camsync393 #(
pulse_cross_clock i_suppress_immediate_set_pclk(.rst(!en), .src_clk(mclk), .dst_clk(pclk), .in_pulse(suppress_immediate_set_mclk), .out_pulse(suppress_immediate_set_pclk),.busy());
pulse_cross_clock i_rdecim_to_pclk0 (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(set_decimate[0]), .out_pulse(reset_decimate[0]),.busy());
pulse_cross_clock i_rdecim_to_pclk1 (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(set_decimate[1]), .out_pulse(reset_decimate[1]),.busy());
pulse_cross_clock i_rdecim_to_pclk2 (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(set_decimate[2]), .out_pulse(reset_decimate[2]),.busy());
pulse_cross_clock i_rdecim_to_pclk3 (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(set_decimate[3]), .out_pulse(reset_decimate[3]),.busy());
pulse_cross_clock i_rdecim_to_pclk0 (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(reset_decimate_mclk[0]), .out_pulse(reset_decimate[0]),.busy());
pulse_cross_clock i_rdecim_to_pclk1 (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(reset_decimate_mclk[1]), .out_pulse(reset_decimate[1]),.busy());
pulse_cross_clock i_rdecim_to_pclk2 (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(reset_decimate_mclk[2]), .out_pulse(reset_decimate[2]),.busy());
pulse_cross_clock i_rdecim_to_pclk3 (.rst(mrst), .src_clk(mclk), .dst_clk(pclk), .in_pulse(reset_decimate_mclk[3]), .out_pulse(reset_decimate[3]),.busy());
endmodule
......
x393_parallel.bit
View file @ df889f79
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x393_parallel.report 0 → 100644
View file @ df889f79
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x393_parallel.timing_summary_impl
View file @ df889f79
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x393_placement.tcl
View file @ df889f79
......@@ -56,6 +56,8 @@ seek $infile 0 start
while { [gets $infile line] >= 0 } {
if { [regexp {(.*)`define(\s*)BOSON} $line matched prematch] } {
if {[regexp "//" $prematch] != 0} { continue }
puts $line
if {[regexp {(.*)`define(\s*)BOSON_REVA} $line matched prematch] } { continue }
set BOSON 1
break
}
......
x393_timing.tcl
View file @ df889f79
......@@ -56,6 +56,8 @@ seek $infile 0 start
while { [gets $infile line] >= 0 } {
if { [regexp {(.*)`define(\s*)BOSON} $line matched prematch] } {
if {[regexp "//" $prematch] != 0} { continue }
puts $line
if {[regexp {(.*)`define(\s*)BOSON_REVA} $line matched prematch] } { continue }
set BOSON 1
break
}
......@@ -67,7 +69,7 @@ if { $LWIR} {
} elseif { $HISPI} {
puts "x393_timing.tcl: using HISPI sensors"
} elseif { $BOSON} {
puts "x393_placement.tcl: using Boson640 sensors"
puts "x393_timing.tcl: using Boson640 sensors"
} else {
puts "x393_timing.tcl: using parallel sensors"
}
......
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