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Commit df351507 authored by Andrey Filippov's avatar Andrey Filippov
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more simulating cmprs_afi_mux

parent cd341af8
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Showing with 85 additions and 33 deletions
axi/cmprs_afi_mux.v
View file @ df351507
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compressor_jp/compressor393.v
View file @ df351507
......@@ -243,7 +243,8 @@ module compressor393 # (
wire [255:0] fifo_rdata;
wire [3:0] fifo_eof; //SuppressThisWarning VEditor : Not used?
wire [3:0] eof_written;
wire [3:0] fifo_flush;
wire [3:0] fifo_flush; // after last frame data was written
wire [3:0] flush_hclk; // before last data was written
wire [31:0] fifo_count;
/* Instance template for module status_router8 */
......@@ -405,6 +406,7 @@ module compressor393 # (
.fifo_eof (fifo_eof[i]), // output
.eof_written (eof_written[i]), // input
.fifo_flush (fifo_flush[i]), // output
.flush_hclk (flush_hclk[i]), // output
.fifo_count (fifo_count[8* i +: 8]) // output[7:0]
);
end
......@@ -440,6 +442,7 @@ module compressor393 # (
.fifo_rdata0 (fifo_rdata[0 +: 64]), // input[63:0]
.eof_written0 (eof_written[0]), // output //?
.pre_flush0 (flush_hclk[0]), // input
.fifo_flush0 (fifo_flush[0]), // input
.fifo_count0 (fifo_count[0 +: 8]), // input[7:0]
......@@ -447,18 +450,21 @@ module compressor393 # (
.fifo_ren1 (fifo_ren[1]), // output
.fifo_rdata1 (fifo_rdata[64 +: 64]), // input[63:0]
.eof_written1 (eof_written[1]), // output
.pre_flush1 (flush_hclk[1]), // input
.fifo_flush1 (fifo_flush[1]), // input
.fifo_count1 (fifo_count[8 +: 8]), // input[7:0]
.fifo_rst2 (), // output
.fifo_ren2 (), // output
.fifo_rdata2 (64'b0), // input[63:0]
.eof_written2 (), // output
.pre_flush2 (1'b0), // input
.fifo_flush2 (1'b0), // input
.fifo_count2 (8'b0), // input[7:0]
.fifo_rst3 (), // output
.fifo_ren3 (), // output
.fifo_rdata3 (64'b0), // input[63:0]
.eof_written3 (), // output
.pre_flush3 (1'b0), // input
.fifo_flush3 (1'b0), // input
.fifo_count3 (8'b0), // input[7:0]
.afi_awaddr (afi0_awaddr), // output[31:0]
......@@ -514,24 +520,28 @@ module compressor393 # (
.fifo_ren0 (fifo_ren[2]), // output
.fifo_rdata0 (fifo_rdata[128 +: 64]), // input[63:0]
.eof_written0 (eof_written[2]), // output
.pre_flush0 (flush_hclk[2]), // input
.fifo_flush0 (fifo_flush[2]), // input
.fifo_count0 (fifo_count[16 +: 8]), // input[7:0]
.fifo_rst1 (fifo_rst[3]), // output
.fifo_ren1 (fifo_ren[3]), // output
.fifo_rdata1 (fifo_rdata[192 +: 64]), // input[63:0]
.eof_written1 (eof_written[3]), // output
.eof_written1 (eof_written[3]), // output
.pre_flush1 (flush_hclk[3]), // input
.fifo_flush1 (fifo_flush[3]), // input
.fifo_count1 (fifo_count[24 +: 8]), // input[7:0]
.fifo_rst2 (), // output
.fifo_ren2 (), // output
.fifo_rdata2 (64'b0), // input[63:0]
.eof_written2 (), // output
.pre_flush2 (1'b0), // input
.fifo_flush2 (1'b0), // input
.fifo_count2 (8'b0), // input[7:0]
.fifo_rst3 (), // output
.fifo_ren3 (), // output
.fifo_rdata3 (64'b0), // input[63:0]
.eof_written3 (), // output
.pre_flush3 (1'b0), // input
.fifo_flush3 (1'b0), // input
.fifo_count3 (8'b0), // input[7:0]
.afi_awaddr (afi1_awaddr), // output[31:0]
......@@ -587,24 +597,28 @@ module compressor393 # (
.fifo_ren0 (fifo_ren[0]), // output
.fifo_rdata0 (fifo_rdata[0 +: 64]), // input[63:0]
.eof_written0 (eof_written[0]), // output
.pre_flush0 (flush_hclk[0]), // input
.fifo_flush0 (fifo_flush[0]), // input
.fifo_count0 (fifo_count[0 +: 8]), // input[7:0]
.fifo_rst1 (fifo_rst[1]), // output
.fifo_ren1 (fifo_ren[1]), // output
.fifo_rdata1 (fifo_rdata[64 +: 64]), // input[63:0]
.eof_written1 (eof_written[1]), // output
.eof_written1 (eof_written[1]), // output
.pre_flush1 (flush_hclk[1]), // input
.fifo_flush1 (fifo_flush[1]), // input
.fifo_count1 (fifo_count[8 +: 8]), // input[7:0]
.fifo_rst2 (fifo_rst[2]), // output
.fifo_ren2 (fifo_ren[2]), // output
.fifo_rdata2 (fifo_rdata[128 +: 64]), // input[63:0]
.eof_written2 (eof_written[2]), // output
.eof_written2 (eof_written[2]), // output
.pre_flush2 (flush_hclk[2]), // input
.fifo_flush2 (fifo_flush[2]), // input
.fifo_count2 (fifo_count[16 +: 8]), // input[7:0]
.fifo_rst3 (fifo_rst[3]), // output
.fifo_ren3 (fifo_ren[3]), // output
.fifo_rdata3 (fifo_rdata[192 +: 64]), // input[63:0]
.eof_written3 (eof_written[3]), // output
.eof_written3 (eof_written[3]), // output
.pre_flush3 (flush_hclk[3]), // input
.fifo_flush3 (fifo_flush[3]), // input
.fifo_count3 (fifo_count[24 +: 8]), // input[7:0]
.afi_awaddr (afi0_awaddr), // output[31:0]
......
compressor_jp/huffman393.v
View file @ df351507
......@@ -44,7 +44,9 @@ module huffman393 (
output reg flush, // last block done - flush the rest bits
output reg last_block,
output reg test_lbw,
output gotLastBlock // last block done - flush the rest bits
output gotLastBlock, // last block done - flush the rest bits
input clk_flush, // other clock to generate synchronized 1-cycle flush_clk output
output flush_clk // 1-cycle flush output @ clk_flush
);
`ifdef INFER_LATCHES
reg [15:0] hcode_latch; // table output huffman code (1..16 bits)
......@@ -407,5 +409,14 @@ module huffman393 (
.web(4'hf), // input[3:0]
.data_in(tdi[15:0]) // input[15:0]
);
pulse_cross_clock flush_clk_i (
.rst (!en2x),
.src_clk (~xclk2x),
.dst_clk (clk_flush),
.in_pulse (flush),
.out_pulse (flush_clk),
.busy ());
endmodule
compressor_jp/jp_channel.v
View file @ df351507
......@@ -165,9 +165,11 @@ module jp_channel#(
input fifo_rst, // reset FIFO (set read address to write, reset count)
input fifo_ren,
output [63:0] fifo_rdata,
output fifo_eof, // single rclk pulse signalling EOF
output fifo_eof, // single rclk pulse signalling EOF
input eof_written, // confirm frame written ofer AFI to the system memory (single rclk pulse)
output fifo_flush, // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
output flush_hclk, // output before writing last chunk - use it to suspend AFI to have
// last burst marked as the last one (otherwise last may be empty if frame had %4==0 chunks)
output [7:0] fifo_count // number of 32-byte chunks in FIFO
);
localparam CMPRS_ADDR = CMPRS_GROUP_ADDR + CMPRS_NUMBER * CMPRS_BASE_INC;
......@@ -855,15 +857,18 @@ module jp_channel#(
.di (enc_do[15:0]), // input[15:0] - specially RLL prepared 16-bit data (to FIFO)
.ds (enc_dv), // input - di valid strobe
.rdy (stuffer_rdy), // input - receiver (bit stuffer) is ready to accept data
.do(huff_do[15:0]), // output[15:0] reg
.dl(huff_dl[3:0]), // output[3:0] reg
.dv(huff_dv), // output reg
.flush(flush), // output reg
.do (huff_do[15:0]), // output[15:0] reg
.dl (huff_dl[3:0]), // output[3:0] reg
.dv (huff_dv), // output reg
.flush (flush), // output reg
/// .last_block(last_block), // output reg
.last_block(), // output reg unused
.test_lbw(), // output reg ??
.last_block (), // output reg unused
.test_lbw (), // output reg ??
/// .gotLastBlock(test_lbw) // output ??
.gotLastBlock() // output ?? - unused (was for debug)
.gotLastBlock (), // output ?? - unused (was for debug)
.clk_flush (hclk), // input
.flush_clk (flush_hclk) // output
);
......@@ -911,9 +916,9 @@ module jp_channel#(
.wa_rst (!stuffer_en), // input reset low address bits when stuffer is disabled (to make sure it is multiple of 32 bytes
.wlast (stuffer_done), // input - written last 32 bytes of a frame (flush FIFO) - stuffer_done (has to be later than we)
.eof_written_wclk (eof_written_xclk2xn), // output - AFI had transferred frame data to the system memory
// AFI clock domain
.rclk (hclk), // input - AFI clock
.rrst (hrst), // input - AFI clock
// AFI clock domain
.rst_fifo (fifo_rst), // input - reset FIFO (set read address to write, reset count)
.ren (fifo_ren), // input - fifo read from AFI channel mux
.rdata (fifo_rdata), // output[63:0] - data to AFI channel mux (latency == 2 from fifo_ren)
......
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