continiuing co-simulation with 353 code, verified martching data to the compressor input (de641880) · Commits · Elphel / x393

compressor_jp/cmprs_cmd_decode.v

+8 −4

Original line number	Original line	Diff line number	Diff line
	@@ -153,6 +153,8 @@ module cmprs_cmd_decode#(
	// cr_w, // data written to cr (1 cycle long) - just to reset legacy IRQ		// cr_w, // data written to cr (1 cycle long) - just to reset legacy IRQ
	// ntiles,//[17:0] - number of tiles in a frame to process		// ntiles,//[17:0] - number of tiles in a frame to process
	input frame_start, // @mclk		input frame_start, // @mclk
			output frame_start_xclk, // frame start, parameters are copied at this pulse

	// outputs sync @ posedge mclk:		// outputs sync @ posedge mclk:
	output cmprs_en_mclk, // @mclk 0 resets immediately		output cmprs_en_mclk, // @mclk 0 resets immediately
	input cmprs_en_extend, // @mclk keep compressor enabled for graceful shutdown		input cmprs_en_extend, // @mclk keep compressor enabled for graceful shutdown
	@@ -162,7 +164,7 @@ module cmprs_cmd_decode#(
	// cmprs_run should be off		// cmprs_run should be off
	output reg sigle_frame_buf, // memory controller uses a single frame buffer (frame_number_* == 0), use other sync		output reg sigle_frame_buf, // memory controller uses a single frame buffer (frame_number_* == 0), use other sync
	// outputs sync @ posedge xclk:		// outputs sync @ posedge xclk:
	output reg cmprs_en_xclk, // enable compressor, turne off immedaitely		output reg cmprs_en_xclk, // enable compressor, turn off immedaitely
	output reg cmprs_en_late_xclk, // enable stuffer, extends control fields for graceful shutdown		output reg cmprs_en_late_xclk, // enable stuffer, extends control fields for graceful shutdown
	// cmprs_start, // single cycle when single or constant compression is turned on		// cmprs_start, // single cycle when single or constant compression is turned on
	// cmprs_repeat,// high in repetitive mode		// cmprs_repeat,// high in repetitive mode
	@@ -283,7 +285,7 @@ module cmprs_cmd_decode#(
	if (mrst) format_mclk <= 0;		if (mrst) format_mclk <= 0;
	else if (format_we_r) format_mclk <= di_r[30:0];		else if (format_we_r) format_mclk <= di_r[30:0];

	if (mrst) color_sat_mclk <= 0;		if (mrst) color_sat_mclk <= 'h0b6090; // 'h16c120 - saturation = 2
	else if (color_sat_we_r) color_sat_mclk <= di_r[23:0];		else if (color_sat_we_r) color_sat_mclk <= di_r[23:0];

	if (mrst) coring_mclk <= 0;		if (mrst) coring_mclk <= 0;
	@@ -292,10 +294,12 @@ module cmprs_cmd_decode#(
	end		end

	// re-clock to compressor clock		// re-clock to compressor clock
			always @ (posedge xclk) begin
	always @ (posedge xclk) if (ctrl_we_xclk) begin
	cmprs_en_xclk <= cmprs_en_mclk_r;		cmprs_en_xclk <= cmprs_en_mclk_r;
	cmprs_en_late_xclk <= cmprs_en_mclk_r \|\| cmprs_en_extend;		cmprs_en_late_xclk <= cmprs_en_mclk_r \|\| cmprs_en_extend;
			end
			always @ (posedge xclk) if (ctrl_we_xclk) begin
			// cmprs_en_late_xclk <= cmprs_en_mclk_r \|\| cmprs_en_extend;
	cmprs_qpage_xclk <= cmprs_qpage_mclk;		cmprs_qpage_xclk <= cmprs_qpage_mclk;
	cmprs_dcsub_xclk <= cmprs_dcsub_mclk;		cmprs_dcsub_xclk <= cmprs_dcsub_mclk;
	cmprs_mode_xclk <= cmprs_mode_mclk;		cmprs_mode_xclk <= cmprs_mode_mclk;

compressor_jp/cmprs_frame_sync.v

+15 −10

compressor_jp/cmprs_macroblock_buf_iface.v

+14 −4

Original line number	Original line	Diff line number	Diff line
	@@ -36,6 +36,7 @@ module cmprs_macroblock_buf_iface (
	output next_page_chn, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data		output next_page_chn, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data

	input frame_en, // if 0 - will reset logic immediately (but not page number)		input frame_en, // if 0 - will reset logic immediately (but not page number)
			input frame_start_xclk, // frame parameters are valid after this pulse
	input frame_go, // start frame: if idle, will start reading data (if available),		input frame_go, // start frame: if idle, will start reading data (if available),
	// if running - will not restart a new frame if 0.		// if running - will not restart a new frame if 0.
	input [ 4:0] left_marg, // left margin (for not-yet-implemented) mono JPEG (8 lines tile row) can need 7 bits (mod 32 - tile)		input [ 4:0] left_marg, // left margin (for not-yet-implemented) mono JPEG (8 lines tile row) can need 7 bits (mod 32 - tile)
	@@ -93,6 +94,7 @@ module cmprs_macroblock_buf_iface (
	// reg first_mb; // from mb_pre_start[2] to mb_pre_start[1]		// reg first_mb; // from mb_pre_start[2] to mb_pre_start[1]
	wire starting;		wire starting;
	reg frame_pre_run;		reg frame_pre_run;
			reg [1:0] frame_may_start;

	assign frame_en_w = frame_en && frame_go;		assign frame_en_w = frame_en && frame_go;

	@@ -106,14 +108,20 @@ module cmprs_macroblock_buf_iface (
	assign last_mb = mb_last_row && mb_last_in_row;		assign last_mb = mb_last_row && mb_last_in_row;
	assign starting = \|mb_pre_start;		assign starting = \|mb_pre_start;

	assign mb_pre_start_w = (mb_pre_end_in && (!last_mb \|\| frame_en_w)) \|\| (!frame_pre_run && frame_en_w && !frame_en_r && !starting);		// assign mb_pre_start_w = (mb_pre_end_in && (!last_mb \|\| frame_en_w)) \|\| (!frame_pre_run && frame_en_w && !frame_en_r && !starting);
	assign frame_pre_start_w = frame_en_w && ((mb_pre_end_in && last_mb) \|\| (!frame_pre_run && !frame_en_r && !starting));		// assign frame_pre_start_w = frame_en_w && ((mb_pre_end_in && last_mb) \|\| (!frame_pre_run && !frame_en_r && !starting));
			assign mb_pre_start_w = (mb_pre_end_in && (!last_mb \|\| frame_may_start)) \|\| ((frame_may_start==2'b1) && !frame_pre_run && !starting);
			assign frame_pre_start_w = frame_may_start[0] && ((mb_pre_end_in && last_mb) \|\| (!frame_pre_run && !frame_may_start[1] && !starting));

	assign start_page = next_invalid[1:0]; // oldest page needed for this macroblock		assign start_page = next_invalid[1:0]; // oldest page needed for this macroblock
	always @ (posedge xclk) begin		always @ (posedge xclk) begin
	if (!frame_en) frame_en_r <= 0;		if (!frame_en) frame_en_r <= 0;
	else frame_en_r <= frame_en_w;		else frame_en_r <= frame_en_w;

			if (!frame_en_w \|\| starting) frame_may_start[0] <= 0;
			else if (frame_start_xclk) frame_may_start[0] <= 1;
			frame_may_start[1] <= frame_may_start[0];

	frame_pre_start_r <= frame_pre_start_w; // same time as mb_pre_start		frame_pre_start_r <= frame_pre_start_w; // same time as mb_pre_start

	if (!frame_en) mb_first_in_row <= 0;		if (!frame_en) mb_first_in_row <= 0;
	@@ -147,8 +155,10 @@ module cmprs_macroblock_buf_iface (

	// calculate before starting each macroblock (will wait if buffer is not ready) (TODO: align mb_pre_start[0] to mb_pre_end[2] - same)		// calculate before starting each macroblock (will wait if buffer is not ready) (TODO: align mb_pre_start[0] to mb_pre_end[2] - same)
	//mb_pre_start_w		//mb_pre_start_w
			if (!frame_en_r) mb_pre_start <= 0;
	if (mb_pre_start_w) mb_pre_start <= 1;		if (mb_pre_start_w) mb_pre_start <= 1;
	else if (!mb_pre_start[4] \|\| buf_ready_w) mb_pre_start <= mb_pre_start << 1;		else if (!mb_pre_start[4] \|\| buf_ready_w) mb_pre_start <= mb_pre_start << 1;

	if (mb_pre_start[1]) mbl_x_r[6:3] <= mb_first_in_row? {2'b0,left_marg[4:3]} : mbl_x_next_r[6:3];		if (mb_pre_start[1]) mbl_x_r[6:3] <= mb_first_in_row? {2'b0,left_marg[4:3]} : mbl_x_next_r[6:3];
	if (mb_pre_start[2]) mbl_x_last_r[7:3] <= {1'b0,mbl_x_r[6:3]} + {2'b0,mb_w_m1[5:3]};		if (mb_pre_start[2]) mbl_x_last_r[7:3] <= {1'b0,mbl_x_r[6:3]} + {2'b0,mb_w_m1[5:3]};
	if (mb_pre_start[3]) begin		if (mb_pre_start[3]) begin
	@@ -163,7 +173,7 @@ module cmprs_macroblock_buf_iface (
	// at the end of each macroblock - calculate start page increment (and after delay - advance invalidate_next)		// at the end of each macroblock - calculate start page increment (and after delay - advance invalidate_next)
	// changed to after started:		// changed to after started:

	// calculate next start X in page (regardless of emd of macroblock row - selection will be at macroblock start)		// calculate next start X in page (regardless of end of macroblock row - selection will be at macroblock start)

	if (mb_pre_start[5]) mbl_x_inc_r[7:3] <= {1'b0,mbl_x_r[6:3]} + {3'b0,mb_hper[4:3]};		if (mb_pre_start[5]) mbl_x_inc_r[7:3] <= {1'b0,mbl_x_r[6:3]} + {3'b0,mb_hper[4:3]};
	if (mb_pre_start[6]) begin		if (mb_pre_start[6]) begin

compressor_jp/cmprs_pixel_buf_iface.v

+45 −31

Original line number	Original line	Diff line number	Diff line
	@@ -44,8 +44,8 @@ module cmprs_pixel_buf_iface #(
	output [ 1:0] buf_rd, // buf {regen, re}		output [ 1:0] buf_rd, // buf {regen, re}
	// if running - will not restart a new frame if 0.		// if running - will not restart a new frame if 0.
	input [ 2:0] converter_type, // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff, 7 - mono8 (not yet implemented)		input [ 2:0] converter_type, // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff, 7 - mono8 (not yet implemented)
	input [ 5:0] mb_w_m1, // macroblock width minus 1 // 3 LSB not used, SHOULD BE SET to 3'b111		input [ 5:0] mb_w_m1, // macroblock width minus 1
	input [ 5:0] mb_h_m1, // macroblock horizontal period (8/16) // 3 LSB not used SHOULD BE SET to 3'b111		input [ 5:0] mb_h_m1, // macroblock height minus 1
	input [ 1:0] tile_width, // memory tile width (can be 128 for monochrome JPEG) Can be 32/64/128: 0 - 16, 1 - 32, 2 - 64, 3 - 128		input [ 1:0] tile_width, // memory tile width (can be 128 for monochrome JPEG) Can be 32/64/128: 0 - 16, 1 - 32, 2 - 64, 3 - 128
	input tile_col_width, // 0 - 16 pixels, 1 -32 pixels		input tile_col_width, // 0 - 16 pixels, 1 -32 pixels
	// Tiles/macroblocks level (from cmprs_macroblock_buf_iface)		// Tiles/macroblocks level (from cmprs_macroblock_buf_iface)
	@@ -55,9 +55,9 @@ module cmprs_pixel_buf_iface #(
	input mb_pre_start, // 1 clock cycle before stream of addresses to the buffer		input mb_pre_start, // 1 clock cycle before stream of addresses to the buffer
	input [ 1:0] start_page, // page to read next tile from (or first of several pages)		input [ 1:0] start_page, // page to read next tile from (or first of several pages)
	input [ 6:0] macroblock_x, // macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide		input [ 6:0] macroblock_x, // macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide
	output [ 7:0] data_out, //		output reg [ 7:0] data_out, //
	output pre_first_out, // For each macroblock in a frame		output pre_first_out, // For each macroblock in a frame
	output data_valid //		output reg data_valid //
	);		);
	localparam PERIOD_COLOR18 = 384; // >1818, limited by 664 (macroblocks)		localparam PERIOD_COLOR18 = 384; // >1818, limited by 664 (macroblocks)
	localparam PERIOD_COLOR20 = 400; // limited by the 20x20 padded macroblock		localparam PERIOD_COLOR20 = 400; // limited by the 20x20 padded macroblock
	@@ -68,7 +68,7 @@ module cmprs_pixel_buf_iface #(


	reg [CMPRS_BUF_EXTRA_LATENCY+3:0] buf_re=0;		reg [CMPRS_BUF_EXTRA_LATENCY+3:0] buf_re=0;
	reg [ 7:0] do_r;		// reg [ 7:0] do_r;
	reg [11:0] bufa_r; // buffer read address (2 MSB - page number)		reg [11:0] bufa_r; // buffer read address (2 MSB - page number)
	reg [11:0] row_sa; // row start address		reg [11:0] row_sa; // row start address
	reg [ 9:0] tile_sa; // tile start address for the same row (w/o page number) for continuing row		reg [ 9:0] tile_sa; // tile start address for the same row (w/o page number) for continuing row
	@@ -79,9 +79,9 @@ module cmprs_pixel_buf_iface #(
	reg [ 5:0] rows_left;		reg [ 5:0] rows_left;
	reg [ 6:0] tile_x; // horizontal position in a tile		reg [ 6:0] tile_x; // horizontal position in a tile
	reg [ 4:0] column_x; // horizontal position in a column (0..31 or 0..15)		reg [ 4:0] column_x; // horizontal position in a column (0..31 or 0..15)
	reg last_col;		reg last_col; // macroblock last column
	reg first_col;		reg first_col; // macroblock first column
	reg last_row;		reg last_row; // macroblock last row

	wire addr_run_end; // generate last cycle of address run		wire addr_run_end; // generate last cycle of address run
	wire [ 6:0] tile_width_or; // set unused msb to all 1		wire [ 6:0] tile_width_or; // set unused msb to all 1
	@@ -105,9 +105,8 @@ module cmprs_pixel_buf_iface #(
	assign mb_pre_end = mb_pre_end_r;		assign mb_pre_end = mb_pre_end_r;
	assign mb_release_buf = mb_release_buf_r;		assign mb_release_buf = mb_release_buf_r;
	assign buf_rd = buf_re[1:0];		assign buf_rd = buf_re[1:0];
	assign data_out = do_r;		// assign data_out = do_r;
	assign pre_first_out = pre_first_out_r;		assign pre_first_out = pre_first_out_r;
	assign data_valid = buf_re[CMPRS_BUF_EXTRA_LATENCY+2];

	always @(posedge xclk) begin		always @(posedge xclk) begin
	if (!frame_en) buf_re[0] <= 0;		if (!frame_en) buf_re[0] <= 0;
	@@ -118,7 +117,7 @@ module cmprs_pixel_buf_iface #(
	else buf_re[CMPRS_BUF_EXTRA_LATENCY+3:1] <= {buf_re[CMPRS_BUF_EXTRA_LATENCY+2:0]};		else buf_re[CMPRS_BUF_EXTRA_LATENCY+3:1] <= {buf_re[CMPRS_BUF_EXTRA_LATENCY+2:0]};

	// Buffer data read:		// Buffer data read:
	if (buf_re[CMPRS_BUF_EXTRA_LATENCY+2]) do_r <= buf_di;		if (buf_re[CMPRS_BUF_EXTRA_LATENCY+2]) data_out <= buf_di;

	if (!frame_en) pre_first_out_r <= 0;		if (!frame_en) pre_first_out_r <= 0;
	else pre_first_out_r <= buf_re[CMPRS_BUF_EXTRA_LATENCY+1] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY+2];		else pre_first_out_r <= buf_re[CMPRS_BUF_EXTRA_LATENCY+1] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY+2];
	@@ -131,10 +130,12 @@ module cmprs_pixel_buf_iface #(

	if (!frame_en) buf_re[CMPRS_BUF_EXTRA_LATENCY+2:1] <= 0;		if (!frame_en) buf_re[CMPRS_BUF_EXTRA_LATENCY+2:1] <= 0;

	if (buf_re[0]) last_col <= 0;		// if (buf_re[0]) last_col <= 0; // ????
			if (!buf_re[0]) last_col <= 0;
	else last_col <= (cols_left == 1);		else last_col <= (cols_left == 1);

	if (buf_re[0]) last_row <= 0;		// if (buf_re[0]) last_row <= 0;
			if (!buf_re[0]) last_row <= 0;
	else if (last_col) last_row <= (rows_left == 1);		else if (last_col) last_row <= (rows_left == 1);

	first_col <= (mb_pre_start \|\| (last_col && !last_row));		first_col <= (mb_pre_start \|\| (last_col && !last_row));
	@@ -153,12 +154,13 @@ module cmprs_pixel_buf_iface #(
	if (mb_pre_start \|\| last_col) tile_x <= {2'b0,macroblock_x[4:0]} \| tile_width_or;		if (mb_pre_start \|\| last_col) tile_x <= {2'b0,macroblock_x[4:0]} \| tile_width_or;
	else if (buf_re[0]) tile_x <= (tile_x+1) \| tile_width_or;		else if (buf_re[0]) tile_x <= (tile_x+1) \| tile_width_or;

	if (mb_pre_start \|\| last_col) bufa_r[11:10] <= start_page;		if (mb_pre_start) bufa_r[11:10] <= start_page;
			else if (last_col) bufa_r[11:10] <= row_sa[11:10]; // start_page;
	else if (last_in_tile) bufa_r[11:10] <= bufa_r[11:10] + 1;		else if (last_in_tile) bufa_r[11:10] <= bufa_r[11:10] + 1;

	// Most time critical - calculation of the buffer address		// Most time critical - calculation of the buffer address
	if (mb_pre_start) bufa_r[9:0] <= {3'b0,macroblock_x};		if (mb_pre_start) bufa_r[9:0] <= {3'b0,macroblock_x};
	else if (last_col) bufa_r[9:0] <= row_sa[9:0];		else if (last_col) bufa_r[9:0] <= row_sa[9:0]; // 'bx next cycle after AFTER mb_pre_start
	else if (last_in_tile) bufa_r[9:0] <= tile_sa;		else if (last_in_tile) bufa_r[9:0] <= tile_sa;
	else if (buf_re[0]) bufa_r[9:0] <= bufa_r[9:0] + {last_in_col?col_inc[9:4]:6'b0,4'b1};		else if (buf_re[0]) bufa_r[9:0] <= bufa_r[9:0] + {last_in_col?col_inc[9:4]:6'b0,4'b1};

	@@ -166,7 +168,7 @@ module cmprs_pixel_buf_iface #(
	if (!frame_en) period_cntr <= 0;		if (!frame_en) period_cntr <= 0;
	else if (mb_pre_start) begin		else if (mb_pre_start) begin
	case (converter_type[2:0])		case (converter_type[2:0])
	CMPRS_COLOR18: period_cntr <= PERIOD_COLOR18 - 1;		CMPRS_COLOR18: period_cntr <= PERIOD_COLOR18 - 1; // period = 384 - limited by 6*64, not by 18x18
	CMPRS_COLOR20: period_cntr <= PERIOD_COLOR20 - 1;		CMPRS_COLOR20: period_cntr <= PERIOD_COLOR20 - 1;
	CMPRS_MONO16: period_cntr <= PERIOD_MONO16 - 1;		CMPRS_MONO16: period_cntr <= PERIOD_MONO16 - 1;
	CMPRS_JP4: period_cntr <= PERIOD_JP4 - 1;		CMPRS_JP4: period_cntr <= PERIOD_JP4 - 1;
	@@ -182,6 +184,18 @@ module cmprs_pixel_buf_iface #(
	if (!frame_en) mb_release_buf_r <= 0;		if (!frame_en) mb_release_buf_r <= 0;
	else mb_release_buf_r <= (period_cntr == (CMPRS_RELEASE_EARLY+1));		else mb_release_buf_r <= (period_cntr == (CMPRS_RELEASE_EARLY+1));

			data_valid <= buf_re[CMPRS_BUF_EXTRA_LATENCY+2];

			end
			`ifdef SIMULATION
			reg [8:0] sim_dout_cntr;
			always @(posedge xclk) begin
			if (!data_valid) sim_dout_cntr <= 0;
			else sim_dout_cntr <= sim_dout_cntr + 1;
			if (data_valid) begin
			$display("CMPRS INPUT %x:%x @ %t",sim_dout_cntr, data_out, $time);
			end
	end		end
			`endif

	endmodule		endmodule

compressor_jp/cmprs_tile_mode_decode.v

+24 −24

Original line number	Original line	Diff line number	Diff line
	@@ -40,7 +40,7 @@ module cmprs_frame_sync#(
	input cmprs_standalone, // @mclk single-cycle: generate a single frame_start_dst in unbonded (not synchronized) mode.		input cmprs_standalone, // @mclk single-cycle: generate a single frame_start_dst in unbonded (not synchronized) mode.
	// cmprs_run should be off		// cmprs_run should be off
	input sigle_frame_buf, // memory controller uses a single frame buffer (frame_number_* == 0), use other sync		input sigle_frame_buf, // memory controller uses a single frame buffer (frame_number_* == 0), use other sync
	input vsync_late, // @xclk delayed start of frame, @xclk. In 353 it was 16 lines after VACT active		input vsync_late, // @mclk delayed start of frame, @xclk. In 353 it was 16 lines after VACT active
	// source channel should already start, some delay give time for sequencer commands		// source channel should already start, some delay give time for sequencer commands
	// that should arrive before it		// that should arrive before it
	input frame_started, // @xclk started first macroblock (checking for broken frames)		input frame_started, // @xclk started first macroblock (checking for broken frames)
	@@ -71,7 +71,7 @@ module cmprs_frame_sync#(
	b) turned off enable while frame was being compressed		b) turned off enable while frame was being compressed
	Abort frame lasts until flush end or timeout expire		Abort frame lasts until flush end or timeout expire
	*/		*/
	wire vsync_late_mclk; // single mclk cycle, reclocked from vsync_late		// wire vsync_late_mclk; // single mclk cycle, reclocked from vsync_late
	wire frame_started_mclk;		wire frame_started_mclk;
	reg bonded_mode;		reg bonded_mode;
	reg frame_start_dst_r;		reg frame_start_dst_r;
	@@ -86,12 +86,16 @@ module cmprs_frame_sync#(
	reg [CMPRS_TIMEOUT_BITS-1:0] timeout;		reg [CMPRS_TIMEOUT_BITS-1:0] timeout;
	reg cmprs_en_extend_r=0;		reg cmprs_en_extend_r=0;
	reg cmprs_en_d;		reg cmprs_en_d;
			// reg cmprs_en_xclk;
	assign frame_start_dst = frame_start_dst_r;		assign frame_start_dst = frame_start_dst_r;
	assign cmprs_en_extend = cmprs_en_extend_r;		assign cmprs_en_extend = cmprs_en_extend_r;

	assign stuffer_running_mclk = stuffer_running_mclk_r;		assign stuffer_running_mclk = stuffer_running_mclk_r;
	assign reading_frame = reading_frame_r;		assign reading_frame = reading_frame_r;

			// always @ (posedge xclk) begin
			// cmprs_en_xclk <=cmprs_en;
			// end
	always @ (posedge mclk) begin		always @ (posedge mclk) begin
	if (mrst) cmprs_en_extend_r <= 0;		if (mrst) cmprs_en_extend_r <= 0;
	else if (cmprs_en) cmprs_en_extend_r <= 1;		else if (cmprs_en) cmprs_en_extend_r <= 1;
	@@ -107,34 +111,35 @@ module cmprs_frame_sync#(

	cmprs_en_d <= cmprs_en;		cmprs_en_d <= cmprs_en;

	broken_frame <= cmprs_en && cmprs_run && vsync_late_mclk && reading_frame_r; // single xclk pulse		broken_frame <= cmprs_en && cmprs_run && vsync_late && reading_frame_r; // single xclk pulse
	aborted_frame <= cmprs_en_d && !cmprs_en && stuffer_running_mclk_r;		aborted_frame <= cmprs_en_d && !cmprs_en && stuffer_running_mclk_r;

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