CVC defines set, part2

wrap/idelay_fine_pipe.v

@@ -47,7 +47,13 @@ module  idelay_fine_pipe
         always @ (fdly_pre) begin
             if (fdly_pre > 3'h4) $display ("ERROR: fine idelay value should be <5, specified %d @ %t", fdly_pre,$time);  
         end
-    `endif
+    `else // IVERILOG
+    `ifdef CVC
+        always @ (fdly_pre) begin
+            if (fdly_pre > 3'h4) $display ("ERROR: fine idelay value should be <5, specified %d @ %t", fdly_pre,$time);  
+        end
+    `endif //CVC
+    `endif //IVERILOG
 `ifndef IGNORE_ATTR
   (* IODELAY_GROUP = IODELAY_GRP *) 
 `endif

wrap/iserdes_mem.v

@@ -20,6 +20,13 @@
  *******************************************************************************/
 `timescale 1ns/1ps
 //`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch
+`ifdef IVERILOG
+    `define IVERILOGorCVC
+`else
+`ifdef CVC
+    `define IVERILOGorCVC
+`endif
+`endif
 module  iserdes_mem #
 (
     parameter DYN_CLKDIV_INV_EN="FALSE",
@@ -35,7 +42,7 @@ module  iserdes_mem #
     output [3:0] dout
 );
 
-`ifndef IVERILOG  // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )           
+`ifndef IVERILOGorCVC  // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )           
      ISERDESE2 #(
          .DATA_RATE                  ("DDR"),
          .DATA_WIDTH                 (4),

wrap/odelay_fine_pipe.v

@@ -46,7 +46,13 @@ module  odelay_fine_pipe
         always @ (fdly_pre) begin
             if (fdly_pre > 3'h4) $display ("ERROR: fine odelay value should be <5, specified %d @ %t", fdly_pre,$time);  
         end
-    `endif
+    `else // IVERILOG
+    `ifdef CVC
+        always @ (fdly_pre) begin
+            if (fdly_pre > 3'h4) $display ("ERROR: fine odelay value should be <5, specified %d @ %t", fdly_pre,$time);  
+        end
+    `endif // CVC
+    `endif // IVERILOG
  
 `ifndef IGNORE_ATTR
   (* IODELAY_GROUP = IODELAY_GRP *) 

wrap/oserdes_mem.v

@@ -20,6 +20,13 @@
  *******************************************************************************/
 `timescale 1ns/1ps
 //`define IVERILOG // uncomment just to chenck syntax (by the editor) in the corresponding branch
+`ifdef IVERILOG
+    `define IVERILOGorCVC
+`else
+`ifdef CVC
+    `define IVERILOGorCVC
+`endif
+`endif
 module  oserdes_mem #(
     parameter MODE_DDR="TRUE"
 ) (
@@ -46,7 +53,7 @@ localparam integer DATA_WIDTH_TRI=  (MODE_DDR=="TRUE")?4:1;
     seems to be OK.
 */
 
-`ifndef IVERILOG  // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted ) 
+`ifndef IVERILOGorCVC  // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted ) 
            OSERDESE2 #(
                .DATA_RATE_OQ         (DATA_RATE),
                .DATA_RATE_TQ         (DATA_RATE),

x393_testbench01.tf

@@ -58,14 +58,18 @@ module  x393_testbench01 #(
 `else
     `include "IVERILOG_INCLUDE.v"
 `endif // NON_VDT_ENVIROMENT
-`else
+`else // IVERILOG
 //    $display("IVERILOG is not defined");
 `ifdef CVC
+`ifdef NON_VDT_ENVIROMENT
     parameter lxtname = "x393.fst";
+`else // NON_VDT_ENVIROMENT
+    `include "IVERILOG_INCLUDE.v"
+`endif // NON_VDT_ENVIROMENT
 `else
     parameter lxtname = "x393.lxt";
 `endif // CVC
-`endif
+`endif // IVERILOG
 `define DEBUG_WR_SINGLE 1  
 `define DEBUG_RD_DATA 1  
 //`include "includes/x393_cur_params_sim.vh" // parameters that may need adjustment, should be before x393_localparams.vh