debugging upgrade from 15.3 to 17.4

axi/histogram_saxi.v

@@ -503,6 +503,7 @@ module  histogram_saxi#(
     );
 
     ram_var_w_var_r #(
+        .COMMENT("histogram_saxi"),
         .REGISTERS(1),
         .LOG2WIDTH_WR(5),
         .LOG2WIDTH_RD(5),

axi/mult_saxi_wr.v

@@ -497,6 +497,7 @@ module  mult_saxi_wr #(
     generate
         if (MULT_SAXI_HALF_BRAM)
             ram18_var_w_var_r #(
+                .COMMENT("mult_saxi_wr_MULT_SAXI_HALF_BRAM"),
                 .REGISTERS(1),
                 .LOG2WIDTH_WR(5),
                 .LOG2WIDTH_RD(5),
@@ -515,6 +516,7 @@ module  mult_saxi_wr #(
             );
         else
             ram_var_w_var_r #(
+                .COMMENT("mult_saxi_wr_not_MULT_SAXI_HALF_BRAM"),
                 .REGISTERS(1),
                 .LOG2WIDTH_WR(5),
                 .LOG2WIDTH_RD(5),

axi/mult_saxi_wr_inbuf.v

@@ -120,6 +120,7 @@ module  mult_saxi_wr_inbuf#(
     generate
         if (MULT_SAXI_HALF_BRAM_IN)
             ram18_var_w_var_r #(
+                .COMMENT("mult_saxi_wr_inbuf_MULT_SAXI_HALF_BRAM_IN"),
                 .REGISTERS(1),
                 .LOG2WIDTH_WR(MULT_SAXI_WLOG),
                 .LOG2WIDTH_RD(5),
@@ -138,6 +139,7 @@ module  mult_saxi_wr_inbuf#(
             );
         else
             ram_var_w_var_r #(
+                .COMMENT("mult_saxi_wr_inbuf_not_MULT_SAXI_HALF_BRAM_IN"),
                 .REGISTERS(1),
                 .LOG2WIDTH_WR(MULT_SAXI_WLOG),
                 .LOG2WIDTH_RD(5),

compressor_jp/cmprs_out_fifo.v

@@ -108,6 +108,7 @@ module  cmprs_out_fifo(
 // rclk -> wclk
     pulse_cross_clock eof_written_wclk_i (.rst(rrst), .src_clk(rclk), .dst_clk(wclk), .in_pulse(eof_written), .out_pulse(eof_written_wclk),.busy());
     ram_var_w_var_r #(
+        .COMMENT("cmprs_out_fifo"),
         .REGISTERS(1),
         .LOG2WIDTH_WR(4),
         .LOG2WIDTH_RD(6)

compressor_jp/cmprs_out_fifo32.v

@@ -108,6 +108,7 @@ module  cmprs_out_fifo32(
 // rclk -> wclk
     pulse_cross_clock eof_written_wclk_i (.rst(rrst), .src_clk(rclk), .dst_clk(wclk), .in_pulse(eof_written), .out_pulse(eof_written_wclk),.busy());
     ram_var_w_var_r #(
+        .COMMENT("cmprs_out_fifo32"),
         .REGISTERS(1),
         .LOG2WIDTH_WR(5),
         .LOG2WIDTH_RD(6)

fpga_version.vh

@@ -35,7 +35,31 @@
  * contains all the components and scripts required to completely simulate it
  * with at least one of the Free Software programs.
  */
-        parameter FPGA_VERSION =          32'h039300da;      //parallel - sata v.13 - tolerating elidle from device during comreset/cominit -0.014 /1, 81.38%, 
+ 
+        parameter FPGA_VERSION =          32'h039300f0;      //parallel - 17.4 - retry with spells in clean directory
+//      parameter FPGA_VERSION =          32'h039300ef;      //parallel - 17.4 - trying more set_param VivadoSynthesis-20180203230051566.log - OK!
+//      parameter FPGA_VERSION =          32'h039300ee;      //parallel - 17.4 - save after re-running vivado, same dir - bad
+//      parameter FPGA_VERSION =          32'h039300ed;      //parallel - 17.4 - twice synth+par, then bit - good
+//      parameter FPGA_VERSION =          32'h039300edc;      //parallel - 17.4 - twice synth, then bit - bad
+//      parameter FPGA_VERSION =          32'h039300ec;      //parallel - 17.4 - same, no debug, nofresh maxThreads 1- good
+//      parameter FPGA_VERSION =          32'h039300eb;      //parallel - 17.4 - same, no debug, fresh maxThreads 1 - bad (bad numbers)
+//      parameter FPGA_VERSION =          32'h039300ea;      //parallel - 17.4 - same, no debug, nofresh - good
+//      parameter FPGA_VERSION =          32'h039300e9;      //parallel - 17.4 - same, no debug, nofresh - bad, seemed goog log
+//      parameter FPGA_VERSION =          32'h039300e8;      //parallel - 17.4 - same, no debug, fresh - bad
+//      parameter FPGA_VERSION =          32'h039300e7;      //parallel - 17.4 - same, no debug - good
+//      parameter FPGA_VERSION =          32'h039300e6;      //parallel - 17.4 - clean, debug - OK
+//      parameter FPGA_VERSION =          32'h039300e5;      //parallel - 17.4 - clean, debug - OK
+//      parameter FPGA_VERSION =          32'h039300e4;      //parallel - 17.4 - same with clean remote directory - bad
+//      parameter FPGA_VERSION =          32'h039300e3;      //parallel - 17.4 - good
+//      parameter FPGA_VERSION =          32'h039300e2;      //parallel - 17.4 - no error, bad again
+//      parameter FPGA_VERSION =          32'h039300e1;      //parallel - 17.4 - changing attributes to match old -bad!
+//      parameter FPGA_VERSION =          32'h039300e0;      //parallel - 17.4 - disabled all debug - OK 
+//      parameter FPGA_VERSION =          32'h039300df;      //parallel - 17.4 - all debug ==0 - met, OK 
+//      parameter FPGA_VERSION =          32'h039300de;      //parallel - 17.4 - changing clock,met, good (clock - hclk) 
+//      parameter FPGA_VERSION =          32'h039300dd;      //parallel - 17.4 - adding debug to SAXI1GP - OK 
+//      parameter FPGA_VERSION =          32'h039300dc;      //parallel - 15.3 - adding debug to SAXI1GP -  -0.114 
+//      parameter FPGA_VERSION =          32'h039300db;      //parallel - trying to migrate to 17.04 
+//      parameter FPGA_VERSION =          32'h039300da;      //parallel - sata v.13 - tolerating elidle from device during comreset/cominit -0.014 /1, 81.38%, 
 //      parameter FPGA_VERSION =          32'h039300d9;      //parallel - correcting histograms -0.022/1, 79.60%
 //      parameter FPGA_VERSION =          32'h039300d8;      //parallel - SATA is now logging irq on/off -0.054 /16, 80.50%
 //      parameter FPGA_VERSION =          32'h039300d7;      //parallel - updated SATA (v12) all met, 80.32%

memctrl/mcntrl_buf_rd.v

@@ -81,6 +81,7 @@ module  mcntrl_buf_rd #(
     end
 //    ram_512x64w_1kx32r #(
     ram_var_w_var_r #(
+        .COMMENT("mcntrl_buf_rd"),
         .REGISTERS(1),
         .LOG2WIDTH_WR(6),
         .LOG2WIDTH_RD(LOG2WIDTH_RD)

memctrl/mcntrl_buf_wr.v

@@ -71,6 +71,7 @@ module  mcntrl_buf_wr #(
     end
 
     ram_var_w_var_r #(
+        .COMMENT("mcntrl_buf_wr"),
         .REGISTERS(1),
         .LOG2WIDTH_WR(LOG2WIDTH_WR),
         .LOG2WIDTH_RD(6)

sensor/sens_histogram_snglclk.v

@@ -602,6 +602,7 @@ module sens_hist_ram_snglclk_32(
     end
     
     ramt_var_w_var_r #(
+        .COMMENT("sens_hist_ram_snglclk_32_ramt_var_w_var_r_even_i"),
         .REGISTERS_A(1),
         .REGISTERS_B(1),
         .LOG2WIDTH_A(5),
@@ -626,6 +627,7 @@ module sens_hist_ram_snglclk_32(
     );
 
     ramt_var_w_var_r #(
+        .COMMENT("sens_hist_ram_snglclk_32_ramt_var_w_var_r_odd_i"),
         .REGISTERS_A(1),
         .REGISTERS_B(1),
         .LOG2WIDTH_A(5),
@@ -685,6 +687,7 @@ module sens_hist_ram_snglclk_18(
     end
     
     ram18tp_var_w_var_r #(
+        .COMMENT("sens_hist_ram_snglclk_18_ramt_var_w_var_r_even_i"),
         .REGISTERS_A(1),
         .REGISTERS_B(1),
         .LOG2WIDTH_A(4),
@@ -709,6 +712,7 @@ module sens_hist_ram_snglclk_18(
     );
 
     ram18tp_var_w_var_r #(
+        .COMMENT("sens_hist_ram_snglclk_18_ramt_var_w_var_r_odd_i"),
         .REGISTERS_A(1),
         .REGISTERS_B(1),
         .LOG2WIDTH_A(4),

sensor/sensor_i2c.v

@@ -478,6 +478,7 @@ module  sensor_i2c#(
     
     
     ram_var_w_var_r #(
+        .COMMENT("sensor_i2c"),
         .REGISTERS(1), // try to delay i2c_byte_start by one more cycle
         .LOG2WIDTH_WR(5),
         .LOG2WIDTH_RD(3)

sensor/sensor_i2c_prot.v

@@ -334,6 +334,7 @@ module  sensor_i2c_prot#(
     end
     
     ram18_var_w_var_r #(
+        .COMMENT("sensor_i2c_prot"),
         .REGISTERS    (1),
         .LOG2WIDTH_WR (5),
         .LOG2WIDTH_RD (5),

util_modules/cmd_frame_sequencer.v

@@ -336,6 +336,7 @@ module  cmd_frame_sequencer#(
     generate
         if (CMDFRAMESEQ_DEPTH == 32) begin
             ram_var_w_var_r #(
+                .COMMENT("cmd_frame_sequencer_CMDFRAMESEQ_DEPTH_32"),
                 .REGISTERS(1),
                 .LOG2WIDTH_WR(6),
                 .LOG2WIDTH_RD(6),
@@ -425,6 +426,7 @@ module  cmd_frame_sequencer#(
         
         else if (CMDFRAMESEQ_DEPTH == 128)  begin
             ram_var_w_var_r #(
+                .COMMENT("cmd_frame_sequencer_CMDFRAMESEQ_DEPTH_128A"),
                 .REGISTERS(1),
                 .LOG2WIDTH_WR(4),
                 .LOG2WIDTH_RD(4),
@@ -446,6 +448,7 @@ module  cmd_frame_sequencer#(
             );
         
             ram_var_w_var_r #(
+                .COMMENT("cmd_frame_sequencer_CMDFRAMESEQ_DEPTH_128B"),
                 .REGISTERS(1),
                 .LOG2WIDTH_WR(4),
                 .LOG2WIDTH_RD(4),
@@ -466,6 +469,7 @@ module  cmd_frame_sequencer#(
             );
         
             ram_var_w_var_r #(
+                .COMMENT("cmd_frame_sequencer_CMDFRAMESEQ_DEPTH_128C"),
                 .REGISTERS(1),
                 .LOG2WIDTH_WR(4),
                 .LOG2WIDTH_RD(4),

util_modules/debug_read.v

+/*!
+ * <b>Module:</b> debug_read
+ * @file debug_read.v
+ * @date 2018-02-01  
+ * @author Andrey Filippov
+ *     
+ * @brief read wide data by providing address
+ *
+ * @copyright Copyright (c) 2018 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ *
+ * <b>License </b>
+ *
+ * debug_read.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * debug_read.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ */
+`timescale 1ns/1ps
+
+module  debug_read#(
+    parameter DEBUG_NUM  =                     16, // number of 32-bit input registers
+    parameter DEBUG_PAYLOAD =                  2,  // number of debug bits to watch for change
+    parameter DEBUG_STATUS =                  'h714, //
+    parameter DEBUG_STATUS_MASK =             'h7ff,
+    parameter DEBUG_STATUS_REG_ADDR =         'hf0,  // 1 location
+    parameter DEBUG_STATUS_PAYLOAD_ADDR =     'he0  // 16 locations
+)(
+    input                           mclk,        // system clock
+    input                           mrst,        // @ posedge mclk - sync reset
+    // programming interface
+    input                     [7:0] cmd_ad,      // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 
+    input                           cmd_stb,     // strobe (with first byte) for the command a/d
+    output                    [7:0] status_ad,   // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
+    output                          status_rq,   // input request to send status downstream
+    input                           status_start, // Acknowledge of the first status packet byte (address)
+    input  [DEBUG_NUM * 32 - 1 : 0] dbg_in,
+    input   [DEBUG_PAYLOAD - 1 : 0] dbg_watch
+);
+
+    wire           [31:0] cmd_data; 
+    wire                  cmd_status;
+
+    cmd_deser #(
+        .ADDR       (DEBUG_STATUS),
+        .ADDR_MASK  (DEBUG_STATUS_MASK),
+        .NUM_CYCLES (6),
+        .ADDR_WIDTH (1),
+        .DATA_WIDTH (32)
+        
+    ) cmd_deser_32bit_i (
+        .rst        (1'b0),         //rst),         // input
+        .clk        (mclk),        // input
+        .srst       (mrst),        // input
+        .ad         (cmd_ad),      // input[7:0] 
+        .stb        (cmd_stb),     // input
+        .addr       (),            // output[3:0] // not used 
+        .data       (cmd_data),    // output[31:0] 
+        .we         (cmd_status)   // output
+    );
+
+    status_generate #(
+        .STATUS_REG_ADDR     (DEBUG_STATUS_REG_ADDR),
+        .PAYLOAD_BITS        (DEBUG_PAYLOAD),
+        .REGISTER_STATUS     (1),
+        .EXTRA_WORDS         (DEBUG_NUM),
+        .EXTRA_REG_ADDR      (DEBUG_STATUS_PAYLOAD_ADDR)
+        
+    ) status_generate_i (
+        .rst           (1'b0),                  //  rst),                   // input
+        .clk           (mclk),                  // input
+        .srst          (mrst),                  // input
+        .we            (cmd_status),            // input
+        .wd            (cmd_data[7:0]),         // input[7:0] 
+        .status        ({dbg_in, dbg_watch }),  // input[25:0] // 2 LSBs - may add "real" status 
+        .ad            (status_ad),             // output[7:0] 
+        .rq            (status_rq),             // output
+        .start         (status_start)           // input
+    );
+
+
+endmodule
+

util_modules/debug_saxigp.v

+/*!
+ * <b>Module:</b> debug_saxigp
+ * @file debug_saxigp.v
+ * @date 2018-02-02  
+ * @author Andrey Filippov
+ *     
+ * @brief Debugging loss of SAXIGP communication after upgrading Vivado 15.3->17.4
+ *
+ * @copyright Copyright (c) 2018 <set up in Preferences-Verilog/VHDL Editor-Templates> .
+ *
+ * <b>License </b>
+ *
+ * debug_saxigp.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * debug_saxigp.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any encrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ */
+`timescale 1ns/1ps
+
+module  debug_saxigp #(
+    parameter DEBUG_STATUS =                  'h714, //
+    parameter DEBUG_STATUS_MASK =             'h7ff,
+    parameter DEBUG_STATUS_REG_ADDR =         'hf0,  // 1 location
+    parameter DEBUG_STATUS_PAYLOAD_ADDR =     'he0  // 16 locations
+)(
+    input                           mclk,        // system clock
+    input                           mrst,        // @ posedge mclk - sync reset
+    // programming interface
+    input                     [7:0] cmd_ad,      // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 
+    input                           cmd_stb,     // strobe (with first byte) for the command a/d
+    output                    [7:0] status_ad,   // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
+    output                          status_rq,   // input request to send status downstream
+    input                           status_start, // Acknowledge of the first status packet byte (address)
+
+    input                           saxi_aclk,  //    = hclk; // 150KHz
+    input                    [31:0] saxi_awaddr,
+    input                           saxi_awvalid,
+    input                           saxi_awready,
+    input                    [ 5:0] saxi_awid,
+     
+    input                    [ 1:0] saxi_awlock, 
+    input                    [ 3:0] saxi_awcache, 
+    input                    [ 2:0] saxi_awprot, 
+    input                    [ 3:0] saxi_awlen, 
+    input                    [ 1:0] saxi_awsize, 
+    input                    [ 1:0] saxi_awburst, 
+    input                    [ 3:0] saxi_awqos,
+     
+    input                    [31:0] saxi_wdata, 
+    input                           saxi_wvalid,
+    input                           saxi_wready,
+    input                    [ 5:0] saxi_wid, 
+    input                           saxi_wlast, // 
+    
+    input                    [ 3:0] saxi_wstrb, 
+    input                           saxi_bvalid,
+    input                           saxi_bready,
+    input                    [ 5:0] saxi_bid, 
+    input                    [ 1:0] saxi_bresp 
+);
+
+    reg [15:0] cntr_clk;
+    reg [15:0] cntr_aw;
+    reg [15:0] cntr_w;
+    reg [15:0] cntr_b;
+    reg        hrst;
+    
+    wire [159:0] dbg_in = {
+        cntr_b,                                                  // 16 
+        cntr_w,                                                  // 16 
+        cntr_aw,                                                 // 16
+        cntr_clk,                                                // 16
+        saxi_awaddr,                                             // 32
+        saxi_wdata,                                              // 32
+         
+        saxi_wvalid, saxi_wready, saxi_wid,                      // 8
+        2'b0, saxi_awlock, saxi_awcache,                         // 8  
+        1'b0, saxi_awprot, saxi_awlen,                           // 8
+        saxi_awsize, saxi_awburst, saxi_awqos};                  // 8
+        
+    wire [25:0] dbg_watch = {
+        saxi_awvalid, saxi_awready, saxi_awid, // 8
+        1'b0, saxi_wlast, saxi_wstrb, saxi_bresp, saxi_bvalid,  saxi_bready, saxi_bid,   // 16
+        saxi_awvalid && saxi_awready,
+        saxi_wvalid && saxi_wready};
+        
+    
+    always @ (posedge saxi_aclk) begin
+        hrst <= mrst;
+        if (hrst) cntr_clk <= 0;
+        else      cntr_clk <= cntr_clk + 1;
+        
+        if      (hrst)                         cntr_aw <= 0;
+        else if (saxi_awvalid && saxi_awready) cntr_aw <= cntr_aw + 1;
+        
+        if      (hrst)                         cntr_w <= 0;
+        else if (saxi_wvalid && saxi_wready)   cntr_w <= cntr_w + 1;
+        
+        if      (hrst)                         cntr_b <= 0;
+        else if (saxi_bvalid && saxi_bready)   cntr_b <= cntr_b + 1;
+    end
+
+    debug_read #(
+        .DEBUG_NUM                 (5),
+        .DEBUG_PAYLOAD             (26),
+        .DEBUG_STATUS              (DEBUG_STATUS),
+        .DEBUG_STATUS_MASK         (DEBUG_STATUS_MASK),
+        .DEBUG_STATUS_REG_ADDR     (DEBUG_STATUS_REG_ADDR),
+        .DEBUG_STATUS_PAYLOAD_ADDR (DEBUG_STATUS_PAYLOAD_ADDR)
+    ) debug_read_i (
+        .mclk                      (mclk),         // input
+        .mrst                      (mrst),         // input
+        .cmd_ad                    (cmd_ad),       // input[7:0] 
+        .cmd_stb                   (cmd_stb),      // input
+        .status_ad                 (status_ad),    // output[7:0] 
+        .status_rq                 (status_rq),    // output
+        .status_start              (status_start), // input
+        .dbg_in                    (dbg_in),       // input[511:0] 
+        .dbg_watch                 (dbg_watch)     // input[1:0] 
+    );
+
+
+endmodule
+

util_modules/dly01_16.v

@@ -45,7 +45,7 @@ module  dly01_16(
     input       din,
     output      dout
 );
-    reg [15:0] sr=0;
+(* shreg_extract = "yes" *) reg [15:0] sr=0;
 `ifdef SHREG_SEQUENTIAL_RESET
     always @ (posedge clk) begin
         sr <= {sr[14:0], din & ~rst}; 

wrap/ram18_var_w_var_r.v

@@ -96,6 +96,7 @@
 */
 module  ram18_var_w_var_r
 #(
+  parameter         COMMENT = "",
   parameter integer REGISTERS    = 0, // 1 - registered output
   parameter integer LOG2WIDTH_WR = 5, // WIDTH= 9  << (LOG2WIDTH - 3)
   parameter integer LOG2WIDTH_RD = 5, // WIDTH= 9  << (LOG2WIDTH - 3)
@@ -120,6 +121,9 @@ module  ram18_var_w_var_r
       input                     [ 3:0] web,      // write byte enable
       input  [(1 << LOG2WIDTH_WR)-1:0] data_in   // data out
     );
+    initial begin
+        if (COMMENT != "") $display(COMMENT);
+    end
     generate
         if (DUMMY)
             ram18_dummy #(

wrap/ram18tp_var_w_var_r.v

@@ -98,6 +98,7 @@
 
 module  ram18tp_var_w_var_r
 #(
+  parameter         COMMENT = "",
   parameter integer REGISTERS_A = 0, // 1 - registered output
   parameter integer REGISTERS_B = 0, // 1 - registered output
   parameter integer LOG2WIDTH_A = 4,  // WIDTH= 9  << (LOG2WIDTH - 3)
@@ -151,6 +152,10 @@ module  ram18tp_var_w_var_r
     wire [WIDTH_BP+1:0] datap_in_ext_b = {2'b0,data_in_b[WIDTH_B+:WIDTH_BP]};
     wire          [1:0] datap_in2_b=     datap_in_ext_b[1:0];
 
+    initial begin
+        if (COMMENT != "") $display(COMMENT);
+    end
+
     RAMB18E1
     #(
     .RSTREG_PRIORITY_A         ("RSTREG"),       // Valid: "RSTREG" or "REGCE"

wrap/ram_var_w_var_r.v

@@ -80,6 +80,7 @@
 */
 module  ram_var_w_var_r
 #(
+  parameter         COMMENT = "",
   parameter integer REGISTERS    = 0, // 1 - registered output
   parameter integer LOG2WIDTH_WR = 6,  // WIDTH= 1  << LOG2WIDTH
   parameter integer LOG2WIDTH_RD = 6,  // WIDTH= 1  << LOG2WIDTH
@@ -107,12 +108,14 @@ module  ram_var_w_var_r
     generate
         if (DUMMY)
             ram_dummy #(
+                .COMMENT(COMMENT),
                 .LOG2WIDTH_RD(LOG2WIDTH_RD)
             ) ramp_dummy_i (
                 .data_out(data_out) 
             );
         else if ((LOG2WIDTH_WR == 6) && (LOG2WIDTH_RD == 6))
             ram_64w_64r #(
+                .COMMENT(COMMENT),
                 .REGISTERS    (REGISTERS)
 `ifdef PRELOAD_BRAMS
     `include "includes/ram36_pass_init.vh"
@@ -131,6 +134,7 @@ module  ram_var_w_var_r
             );
         else if ((LOG2WIDTH_WR == 6) && (LOG2WIDTH_RD < 6))
             ram_64w_lt64r #(
+                .COMMENT(COMMENT),
                 .REGISTERS    (REGISTERS),
                 .LOG2WIDTH_RD (LOG2WIDTH_RD)
 `ifdef PRELOAD_BRAMS
@@ -150,6 +154,7 @@ module  ram_var_w_var_r
             );
         else if ((LOG2WIDTH_WR < 6) && (LOG2WIDTH_RD == 6))
             ram_lt64w_64r #(
+                .COMMENT(COMMENT),
                 .REGISTERS    (REGISTERS),
                 .LOG2WIDTH_WR (LOG2WIDTH_WR)
 `ifdef PRELOAD_BRAMS
@@ -169,6 +174,7 @@ module  ram_var_w_var_r
             );
         else if ((LOG2WIDTH_WR < 6) && (LOG2WIDTH_RD < 6))
             ram_lt64w_lt64r #(
+                .COMMENT(COMMENT),
                 .REGISTERS    (REGISTERS),
                 .LOG2WIDTH_WR (LOG2WIDTH_WR),
                 .LOG2WIDTH_RD (LOG2WIDTH_RD)
@@ -193,6 +199,7 @@ endmodule
 // Both ports with 64 bit widths
 module  ram_64w_64r
 #(
+  parameter         COMMENT = "",
   parameter integer REGISTERS    = 0 // 1 - registered output
 `ifdef PRELOAD_BRAMS
     ,
@@ -214,7 +221,9 @@ module  ram_64w_64r
     );
     localparam  PWIDTH_WR=72;
     localparam  PWIDTH_RD=72;
-    
+    initial begin
+        if (COMMENT != "") $display(COMMENT);
+    end
     RAMB36E1
     #(
     .RSTREG_PRIORITY_A         ("RSTREG"),       // Valid: "RSTREG" or "REGCE"
@@ -284,6 +293,7 @@ endmodule
 // Both ports with less than 64 bit widths - TODO: see if it is still possible to use SDP
 module  ram_lt64w_lt64r
 #(
+  parameter         COMMENT = "",
   parameter integer REGISTERS    = 0, // 1 - registered output
   parameter integer LOG2WIDTH_WR = 5,  // WIDTH= 1  << LOG2WIDTH
   parameter integer LOG2WIDTH_RD = 5   // WIDTH= 1  << LOG2WIDTH
@@ -314,6 +324,9 @@ module  ram_lt64w_lt64r
     wire [WIDTH_WR+31:0] data_in_ext = {32'b0,data_in};
     wire          [31:0] data_in32=data_in_ext[31:0];
     assign data_out=data_out32[WIDTH_RD-1:0];
+    initial begin
+        if (COMMENT != "") $display(COMMENT);
+    end
     RAMB36E1
     #(
     .RSTREG_PRIORITY_A         ("RSTREG"),       // Valid: "RSTREG" or "REGCE"
@@ -399,6 +412,7 @@ endmodule
 // Write port less than 64bits, read port 64 bit widths
 module  ram_lt64w_64r
 #(
+  parameter         COMMENT = "",
   parameter integer REGISTERS    = 0, // 1 - registered output
   parameter integer LOG2WIDTH_WR = 5  // WIDTH= 1  << LOG2WIDTH
 `ifdef PRELOAD_BRAMS
@@ -426,6 +440,9 @@ module  ram_lt64w_64r
 //    localparam  WIDTH_RD  = 64;
     wire [WIDTH_WR+31:0] data_in_ext = {32'b0,data_in};
     wire          [31:0] data_in32=data_in_ext[31:0];
+    initial begin
+        if (COMMENT != "") $display(COMMENT);
+    end
     RAMB36E1
     #(
     .RSTREG_PRIORITY_A         ("RSTREG"),       // Valid: "RSTREG" or "REGCE"
@@ -496,6 +513,7 @@ endmodule
 // Write port 64 bita, read port - less than 64 bits
 module  ram_64w_lt64r
 #(
+  parameter         COMMENT = "",
   parameter integer REGISTERS    = 0, // 1 - registered output
 //  parameter integer LOG2WIDTH_WR = 5,  // WIDTH= 1  << LOG2WIDTH
   parameter integer LOG2WIDTH_RD = 5   // WIDTH= 1  << LOG2WIDTH
@@ -523,6 +541,10 @@ module  ram_64w_lt64r
     localparam  WIDTH_RD  = 1 << LOG2WIDTH_RD;
     wire          [31:0] data_out32;
     assign data_out=data_out32[WIDTH_RD-1:0];
+    initial begin
+        if (COMMENT != "") $display(COMMENT);
+    end
+    
     RAMB36E1
     #(
     .RSTREG_PRIORITY_A         ("RSTREG"),       // Valid: "RSTREG" or "REGCE"
@@ -592,11 +614,16 @@ endmodule
 
 module  ram_dummy
 #(
+  parameter         COMMENT = "",
   parameter integer LOG2WIDTH_RD = 5   // WIDTH= 1  << LOG2WIDTH
  )
    (
       output [(1 << LOG2WIDTH_RD)-1:0] data_out // data out
    );
    assign data_out=0;
+    initial begin
+        if (COMMENT != "") $display(COMMENT);
+    end
+   
 endmodule
 

wrap/ramt_var_w_var_r.v

@@ -98,6 +98,7 @@
 
 module  ramt_var_w_var_r
 #(
+  parameter         COMMENT = "",
   parameter integer REGISTERS_A = 0, // 1 - registered output
   parameter integer REGISTERS_B = 0, // 1 - registered output
   parameter integer LOG2WIDTH_A = 5,  // WIDTH= 9  << (LOG2WIDTH - 3)
@@ -143,6 +144,10 @@ module  ramt_var_w_var_r
     wire [WIDTH_B+31:0] data_in_ext_b =  {32'b0,data_in_b[WIDTH_B-1:0]};
     wire         [31:0] data_in32_b =    data_in_ext_b[31:0];
 
+    initial begin
+        if (COMMENT != "") $display(COMMENT);
+    end
+
     RAMB36E1
     #(
     .RSTREG_PRIORITY_A         ("RSTREG"),       // Valid: "RSTREG" or "REGCE"

wrap/ramt_var_wb_var_r.v

@@ -98,6 +98,7 @@
 
 module  ramt_var_wb_var_r
 #(
+  parameter         COMMENT = "",
   parameter integer REGISTERS_A = 0, // 1 - registered output
   parameter integer REGISTERS_B = 0, // 1 - registered output
   parameter integer LOG2WIDTH_A = 5,  // WIDTH= 9  << (LOG2WIDTH - 3)
@@ -148,6 +149,9 @@ module  ramt_var_wb_var_r
     
     wire [3:0] we_a4= (LOG2WIDTH_A > 3)? ((LOG2WIDTH_A > 4)? we_a : {2{we_a}} ):{4{we_a}};
     wire [3:0] we_b4= (LOG2WIDTH_B > 3)? ((LOG2WIDTH_B > 4)? we_b : {2{we_b}} ):{4{we_b}};
+    initial begin
+        if (COMMENT != "") $display(COMMENT);
+    end
 
     RAMB36E1
     #(

x393.v

@@ -36,6 +36,7 @@
  * contains all the components and scripts required to completely simulate it
  * with at least one of the Free Software programs.
  */
+//`define DEBUG_SAXI1 1
 `timescale 1ns/1ps
 `include "system_defines.vh" 
 module  x393 #(
@@ -396,7 +397,15 @@ module  x393 #(
     
     wire [DEBUG_RING_LENGTH:0]    debug_ring; // TODO: adjust number of bits
     wire                          debug_sl;   // debug shift/load:  0 - idle, (1,0) - shift, (1,1) - load
-`endif    
+`endif
+
+`ifdef DEBUG_SAXI1
+    wire                  [7:0] status_debug_saxi_ad; // saxi1 - logger data Other status byte-wide address/data
+    wire                        status_debug_saxi_rq; // Other status request   
+    wire                        status_debug_saxi_start;  // S uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
+`endif
+
+    
     // Insert register layer if needed
     reg  [7:0] cmd_mcontr_ad;
     reg        cmd_mcontr_stb;
@@ -435,6 +444,12 @@ module  x393 #(
     reg  [7:0] cmd_debug_ad;
     reg        cmd_debug_stb;
 `endif
+`ifdef DEBUG_SAXI1
+    reg  [7:0] cmd_debug_saxi1_ad;
+    reg        cmd_debug_saxi1_stb;
+`endif
+
+
 // membridge
     wire                        frame_start_chn1; // input
     wire                        next_page_chn1; // input
@@ -725,7 +740,14 @@ module  x393 #(
 `ifdef DEBUG_RING
         cmd_debug_ad <=      cmd_root_ad;
         cmd_debug_stb <=     cmd_root_stb;
-`endif        
+`endif
+
+`ifdef DEBUG_SAXI1
+    cmd_debug_saxi1_ad <=      cmd_root_ad;
+    cmd_debug_saxi1_stb <=     cmd_root_stb;
+`endif
+
+        
     end
 
 // For now - connect status_test01 to status_other, if needed - increase number of multiplexer inputs)
@@ -1121,10 +1143,17 @@ assign axi_grst = axi_rst_pre;
         .db_in11   (8'b0),                    // input[7:0] 
         .rq_in11   (1'b0),                    // input
         .start_in11(),                        // output
-`endif        
+`endif
+
+`ifdef DEBUG_SAXI1
+        .db_in12   (status_debug_saxi_ad),    // input[7:0] 
+        .rq_in12   (status_debug_saxi_rq),    // input
+        .start_in12(status_debug_saxi_start), // output
+`else        
         .db_in12   (8'b0),                    // input[7:0] 
         .rq_in12   (1'b0),                    // input
         .start_in12(),                        // output
+`endif        
         
         .db_in13   (8'b0),                    // input[7:0] 
         .rq_in13   (1'b0),                    // input
@@ -2522,7 +2551,7 @@ assign axi_grst = axi_rst_pre;
         .rst    ({hrst,        arst,     lrst,            crst,            xrst,        prst,        mrst})          // output[6:0] 
     );
 
-// Changed aclk to master (itg is the source of most orthers)
+// Changed aclk to master (it is the source of most orthers)
 /*
     sync_resets #(
         .WIDTH(7),
@@ -3502,4 +3531,84 @@ sata_ahci_top sata_top(
     .PSPORB(),                   // PS PSPORB, inout
     .PSSRSTB()                  // PS PSSRSTB, inout
   );
+  
+`ifdef DEBUG_SAXI1
+/*
+    debug_saxigp #(
+        .DEBUG_STATUS              ('h714),
+        .DEBUG_STATUS_MASK         ('h7ff),
+        .DEBUG_STATUS_REG_ADDR     ('he5),// 1 dword
+        .DEBUG_STATUS_PAYLOAD_ADDR ('he0) // 5 dwords
+    ) debug_saxigp_i (
+        .mclk                      (mclk),       // input
+        .mrst                      (mrst),       // input
+        .cmd_ad       (cmd_debug_saxi1_ad),      // input[7:0] 
+        .cmd_stb      (cmd_debug_saxi1_stb),     // input
+        .status_ad    (status_debug_saxi_ad),    // output[7:0] 
+        .status_rq    (status_debug_saxi_rq),    // output
+        .status_start (status_debug_saxi_start), // input
+        .saxi_aclk    (hclk), // saxi1_aclk),              // input
+        .saxi_awaddr  (32'b0), // saxi1_awaddr),            // input[31:0] 
+        .saxi_awvalid (1'b0), // saxi1_awvalid),           // input
+        .saxi_awready (1'b0), // saxi1_awready),           // input
+        .saxi_awid    (6'b0), // saxi1_awid),              // input[5:0] 
+        .saxi_awlock  (2'b0), // saxi1_awlock),            // input[1:0] 
+        .saxi_awcache (4'b0), // saxi1_awcache),           // input[3:0] 
+        .saxi_awprot  (3'b0), // saxi1_awprot),            // input[2:0] 
+        .saxi_awlen   (4'b0), // saxi1_awlen),             // input[3:0] 
+        .saxi_awsize  (2'b0), // saxi1_awsize),            // input[1:0] 
+        .saxi_awburst (2'b0), // saxi1_awburst),           // input[1:0] 
+        .saxi_awqos   (4'b0), // saxi1_awqos),             // input[3:0] 
+        .saxi_wdata   (32'b0), // saxi1_wdata),             // input[31:0] 
+        .saxi_wvalid  (1'b0), // saxi1_wvalid),            // input
+        .saxi_wready  (1'b0), // saxi1_wready),            // input
+        .saxi_wid     (6'b0), // saxi1_wid),               // input[5:0] 
+        .saxi_wlast   (1'b0), // saxi1_wlast),             // input
+        .saxi_wstrb   (4'b0), // saxi1_wstrb),             // input[3:0] 
+        .saxi_bvalid  (1'b0), // saxi1_bvalid),            // input
+        .saxi_bready  (1'b0), // saxi1_bready),            // input
+        .saxi_bid     (6'b0), // saxi1_bid),               // input[5:0] 
+        .saxi_bresp   (2'b0)  // saxi1_bresp)              // input[1:0] 
+    );
+*/
+    debug_saxigp #(
+        .DEBUG_STATUS              ('h714),
+        .DEBUG_STATUS_MASK         ('h7ff),
+        .DEBUG_STATUS_REG_ADDR     ('he5),// 1 dword
+        .DEBUG_STATUS_PAYLOAD_ADDR ('he0) // 5 dwords
+    ) debug_saxigp_i (
+        .mclk                      (mclk),       // input
+        .mrst                      (mrst),       // input
+        .cmd_ad       (cmd_debug_saxi1_ad),      // input[7:0] 
+        .cmd_stb      (cmd_debug_saxi1_stb),     // input
+        .status_ad    (status_debug_saxi_ad),    // output[7:0] 
+        .status_rq    (status_debug_saxi_rq),    // output
+        .status_start (status_debug_saxi_start), // input
+        .saxi_aclk    (saxi1_aclk), // hclk), // saxi1_aclk),              // input
+        .saxi_awaddr  (saxi1_awaddr),            // input[31:0] 
+        .saxi_awvalid (saxi1_awvalid),           // input
+        .saxi_awready (saxi1_awready),           // input
+        .saxi_awid    (saxi1_awid),              // input[5:0] 
+        .saxi_awlock  (saxi1_awlock),            // input[1:0] 
+        .saxi_awcache (saxi1_awcache),           // input[3:0] 
+        .saxi_awprot  (saxi1_awprot),            // input[2:0] 
+        .saxi_awlen   (saxi1_awlen),             // input[3:0] 
+        .saxi_awsize  (saxi1_awsize),            // input[1:0] 
+        .saxi_awburst (saxi1_awburst),           // input[1:0] 
+        .saxi_awqos   (saxi1_awqos),             // input[3:0] 
+        .saxi_wdata   (saxi1_wdata),             // input[31:0] 
+        .saxi_wvalid  (saxi1_wvalid),            // input
+        .saxi_wready  (saxi1_wready),            // input
+        .saxi_wid     (saxi1_wid),               // input[5:0] 
+        .saxi_wlast   (saxi1_wlast),             // input
+        .saxi_wstrb   (saxi1_wstrb),             // input[3:0] 
+        .saxi_bvalid  (saxi1_bvalid),            // input
+        .saxi_bready  (saxi1_bready),            // input
+        .saxi_bid     (saxi1_bid),               // input[5:0] 
+        .saxi_bresp   (saxi1_bresp)              // input[1:0] 
+    );
+`endif        
+  
+  
+  
 endmodule

x393_sata/ahci/ahci_dma.v

@@ -162,6 +162,7 @@ module  ahci_dma (
 //    localparam AFI_FIFO_LAT = 2; // >=2
    localparam SAFE_RD_BITS =   3; //2; // 3;
 
+//    (* ram_style = "block" *)
     reg     [31:0] ct_data_ram [0:31];
     reg      [3:0] int_data_addr;    // internal (ct,prd) data address
 //    reg     [31:7] ctba_r;
@@ -262,7 +263,7 @@ module  ahci_dma (
     
     wire           fifo_nempty_mclk;
     reg            en_extra_din_r;
-    reg     [31:0] ct_data_reg;
+    reg     [31:0] ct_data_register;
 //    reg            abort_busy_hclk;
     reg            hrst_r;
     wire           abort_or_reset = cmd_abort_hclk || (hrst_r && !hrst);
@@ -335,7 +336,7 @@ module  ahci_dma (
     assign afi_arqos =         4'h0;
     assign afi_rdissuecap1en = 1'b0;
     assign extra_din = en_extra_din_r && fifo_nempty_mclk;
-//    reg             [31:0] ct_data_reg;
+//    reg             [31:0] ct_data_register;
     always @ (posedge mclk) begin
     
         if (mrst) afi_dirty_mclk <= 0;
@@ -347,8 +348,8 @@ module  ahci_dma (
         if (mrst || abort_done) abort_busy_mclk <= 0;
         else if (cmd_abort)     abort_busy_mclk <= 1;
     
-        if (ct_re[0]) ct_data_reg <=  ct_data_ram[ct_addr];
-        if (ct_re[1]) ct_data <=      ct_data_reg;
+        if (ct_re[0]) ct_data_register <=  ct_data_ram[ct_addr];
+        if (ct_re[1]) ct_data <=           ct_data_register;
         
 //        if (ctba_ld) ctba_r <=        ctba[31:7];
         if (ctba_ld) ctba_r <=        ctba[31:4];

x393_sata/ahci/axi_ahci_regs.v

@@ -466,6 +466,7 @@ sata_phy_rst_out will be released after the sata clock is stable
     // in the system memory.
 
     ramt_var_wb_var_r #(
+        .COMMENT("axi_ahci_regs_ahci_regs"),
         .REGISTERS_A (0),
         .REGISTERS_B (1),
         .LOG2WIDTH_A (5),
@@ -492,6 +493,7 @@ sata_phy_rst_out will be released after the sata clock is stable
     );
 
     ram_var_w_var_r #(
+        .COMMENT("axi_ahci_regs_ahci_regs_type"),
         .REGISTERS    (0),
         .LOG2WIDTH_WR (6),
         .LOG2WIDTH_RD (6),
@@ -512,6 +514,7 @@ sata_phy_rst_out will be released after the sata clock is stable
     
 `ifdef USE_DATASCOPE
         ram_var_w_var_r #(
+            .COMMENT("axi_ahci_regsdatascope0_mem"),
             .REGISTERS    (0),
             .LOG2WIDTH_WR (5),
             .LOG2WIDTH_RD (5),
@@ -530,6 +533,7 @@ sata_phy_rst_out will be released after the sata clock is stable
         );
 
         ram_var_w_var_r #(
+            .COMMENT("axi_ahci_regsdatascope1_mem"),
             .REGISTERS    (0),
             .LOG2WIDTH_WR (5),
             .LOG2WIDTH_RD (5),

x393_sata/host/gtx_10x8dec.v

@@ -138,6 +138,7 @@ assign  disperror = ~{table_pos_disp0 & expected_disparity | table_neg_disp0 & ~
 
 // TODO change mem to 18 instead of 36, so the highest address bit could be dropped
 ramt_var_w_var_r #(
+    .COMMENT("gtx_10x8dec"),
     .REGISTERS_A    (1),
     .REGISTERS_B    (1),
     .LOG2WIDTH_A    (4),

x393_sata/host/gtx_8x10enc.v

@@ -101,6 +101,7 @@ always @ (posedge clk)
     outdata_l <= {enc1, enc0};
 
 ramt_var_w_var_r #(
+    .COMMENT("gtx_8x10enc"),
     .REGISTERS_A    (1),
     .REGISTERS_B    (1),
     .LOG2WIDTH_A    (5),